CVAX CPU CHIP DESIGN SPECIFICATION
DC 341
21-24674-01
Rev. 3.00
Contact: Andy Olesin (RICKS::OLESIN)
C O M P A N Y C O N F I D E N T I A L
Copyright (C) 1985, 1986, 1987 by Digital Equipment Corporation
The information in this document is subject to change without notice and
should not be construed as a commitment by Digital Equipment Corporation.
Digital Equipment Corporation assumes no responsibility for any errors
that may occur in this document.
This specification does not describe any program or product which is
currently available from Digital Equipment Corporation. Nor does Digital
Equipment Corporation commit to implement this specification in any
product or program. Digital Equipment Corporation makes no commitment
that this document accurately describes any product it might ever make.
CVAX CPU CHIP DESIGN SPECIFICATION Page 2
TABLE OF CONTENTS
CONTENTS
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . 3
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Applicable Documents . . . . . . . . . . . . . . . 3
1.3 CVAX CPU Chip Organization . . . . . . . . . . . . 3
1.3.1 Instruction Unit (I Box) . . . . . . . . . . . . 3
1.3.2 Execution Unit (E Box) . . . . . . . . . . . . . 3
1.3.3 Memory Translation Unit (M Box) . . . . . . . . 3
1.3.4 Bus Interface Unit (BIU) . . . . . . . . . . . . 4
1.3.5 Microsequencer . . . . . . . . . . . . . . . . . 4
1.3.6 Interrupt Logic . . . . . . . . . . . . . . . . 4
1.3.7 Control Store . . . . . . . . . . . . . . . . . 4
1.3.8 Cache . . . . . . . . . . . . . . . . . . . . . 4
1.3.9 Clock Logic . . . . . . . . . . . . . . . . . . 4
1.4 Block Diagram . . . . . . . . . . . . . . . . . . 4
2 INSTRUCTION (I) BOX . . . . . . . . . . . . . . . . 5
2.1 Prefetcher . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Prefetcher Data Path . . . . . . . . . . . . . . 5
2.1.1.1 Instruction Prefetch Queue . . . . . . . . . . 6
2.1.1.2 Instruction Byte Rotator . . . . . . . . . . . 6
2.1.1.3 Instruction Data (ID) Register . . . . . . . . 6
2.1.2 Prefetch Controller . . . . . . . . . . . . . . 7
2.2 The Instruction PLA (IPLA) . . . . . . . . . . . . 7
2.3 Microaddress Generator . . . . . . . . . . . . . . 9
2.3.1 IID Dispatch (used When SPEC.CTR = 0) . . . . . 9
2.3.1.1 IID Exception Dispatch . . . . . . . . . . . . 9
2.3.1.2 IID Execution Dispatch . . . . . . . . . . . 10
2.3.1.3 Specifier Dispatch . . . . . . . . . . . . . 10
2.3.2 Second IID Dispatch ( Spec Counter = 0) . . . 11
2.3.3 Specifier Decode Dispatches . . . . . . . . . 12
2.3.4 MicroAddress Format . . . . . . . . . . . . . 13
2.3.5 Delta PC Logic . . . . . . . . . . . . . . . . 14
2.4 Miscellaneous Register Descriptions . . . . . . 15
2.4.1 Current Specifier / Register Number Latch
(SPEC.RN) . . . . . . . . . . . . . . . . . . 16
2.4.2 FPU Present . . . . . . . . . . . . . . . . . 16
2.4.3 VAX Trap Request . . . . . . . . . . . . . . . 16
2.4.4 Specifier Counter . . . . . . . . . . . . . . 16
2.4.5 Data Length And Access Type . . . . . . . . . 17
2.4.6 PSL Bits . . . . . . . . . . . . . . . . . . . 17
2.4.7 Second IID Flag . . . . . . . . . . . . . . . 18
2.4.8 Index Expected Flag . . . . . . . . . . . . . 18
2.5 I Box Initialization At RESET Signal . . . . . . 18
2.6 I Box Related Microinstructions . . . . . . . . 18
2.7 Microcode Restriction Summary . . . . . . . . . 20
2.8 SN Output . . . . . . . . . . . . . . . . . . . 21
2.9 I Box Testability Hardware . . . . . . . . . . . 21
2.10 I Box Schematics And Their Functions . . . . . . 23
2.10.1 I_ADDRESS_GENERATOR (IAG) . . . . . . . . . . 23
2.10.2 I_AT_DL_REG (IAD) . . . . . . . . . . . . . . 23
2.10.3 I_DATAPATH (IDP) . . . . . . . . . . . . . . . 23
2.10.4 I_DP_DRIVERS (IDD) . . . . . . . . . . . . . . 23
2.10.5 I_DISPATCH_PLA (IP1) . . . . . . . . . . . . . 23
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2.10.5.1 I_DISPATCH_PLA PLAD File . . . . . . . . . . 23
2.10.5.2 I_DISPATCH_PLA Binary File... . . . . . . . 27
2.10.6 I_FPA_BUFFERS (IFB) . . . . . . . . . . . . . 28
2.10.7 I_IID_LOGIC (IIL) . . . . . . . . . . . . . . 28
2.10.8 I_IPLA (IPL) . . . . . . . . . . . . . . . . . 28
2.10.9 I_MIB_DECODE (IMD) . . . . . . . . . . . . . . 29
2.10.10 I_MISC_STATE (IMS) . . . . . . . . . . . . . . 29
2.10.11 I_OP_MUX (IOM) . . . . . . . . . . . . . . . . 29
2.10.12 I_OTHER_MIB_DECODER (IM2) . . . . . . . . . . 29
2.10.13 I_PFQ_CONTROL (IQC) . . . . . . . . . . . . . 29
2.10.14 I_SECOND_IPLA (I2P) . . . . . . . . . . . . . 30
2.10.15 I_SPEC_COUNTER (ISC) . . . . . . . . . . . . . 30
2.10.16 I_SPEC_RN_REG (ISR) . . . . . . . . . . . . . 30
2.10.17 I_SPUR_UTEST_DRIVE (ISU) . . . . . . . . . . . 30
2.11 Tables . . . . . . . . . . . . . . . . . . . . . 31
2.11.1 Dispatch Types, STALL And UTrap Behavior . . 31
2.11.2 NOTE ON UPDATING I BOX STATE . . . . . . . . . 31
2.11.3 CVAX IPLA Assignments . . . . . . . . . . . . 33
2.11.4 Other Opcodes . . . . . . . . . . . . . . . . 42
2.11.5 Internal/External Signal Timing . . . . . . . 43
2.12 Glossary Of Mnemonics . . . . . . . . . . . . . 87
2.13 CHANGE REQUESTS THAT HAVE BEEN INCLUDED HERE . . 88
2.14 ISSUES . . . . . . . . . . . . . . . . . . . . . 88
3 EXECUTION (E) BOX . . . . . . . . . . . . . . . . 91
3.1 Register File . . . . . . . . . . . . . . . . . 93
3.1.1 Triple Ported Registers (W Registers) . . . . 93
3.1.2 Dual Ported Registers (GP Registers) . . . . . 93
3.1.2.1 Data-Length Dependent Writes . . . . . . . . 93
3.1.3 Dual Ported Registers (T Registers) . . . . . 94
3.1.4 Functional Summary . . . . . . . . . . . . . . 94
3.1.4.1 Register File Addressing . . . . . . . . . . 94
3.1.4.2 Source Control . . . . . . . . . . . . . . . 96
3.1.4.3 Implementation Notes . . . . . . . . . . . . 96
3.1.4.4 Destination Control . . . . . . . . . . . . 97
3.1.4.5 Timing Of Writes And Control Signals From The
M BOX . . . . . . . . . . . . . . . . . . . 97
3.1.5 W_Bus . . . . . . . . . . . . . . . . . . . . 97
3.1.6 Zero Extension . . . . . . . . . . . . . . . . 97
3.1.7 W_SPUR . . . . . . . . . . . . . . . . . . . . 98
3.1.8 Microcode Restrictions . . . . . . . . . . . . 99
3.2 Program Counter (PC Register) . . . . . . . . . 100
3.2.1 PC Register . . . . . . . . . . . . . . . . . 100
3.2.2 PC Adder . . . . . . . . . . . . . . . . . . . 101
3.2.3 BPC Register . . . . . . . . . . . . . . . . . 101
3.2.4 Microcode Restrictions . . . . . . . . . . . . 101
3.3 Constant Generator . . . . . . . . . . . . . . . 102
3.3.1 Constants . . . . . . . . . . . . . . . . . . 102
3.3.1.1 KDL Constants . . . . . . . . . . . . . . . 102
3.3.1.2 SHIFT Microinstruction Constants . . . . . . 102
3.3.1.3 CONSTANT Microinstruction Constants . . . . 102
3.3.1.4 A_Bus Constants . . . . . . . . . . . . . . 103
3.3.2 Microcode Restrictions . . . . . . . . . . . . 103
3.4 Shift Counter (SC) . . . . . . . . . . . . . . . 104
3.4.1 Functional Summary . . . . . . . . . . . . . . 104
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3.4.2 UTest And The SC . . . . . . . . . . . . . . . 104
3.4.3 Microcode Restrictions . . . . . . . . . . . . 105
3.5 Shifter . . . . . . . . . . . . . . . . . . . . 106
3.5.1 Functional Summary . . . . . . . . . . . . . . 106
3.5.1.1 Implementation Note . . . . . . . . . . . . 107
3.5.2 Raw SHFT Condition Codes . . . . . . . . . . . 107
3.5.3 Microcode Restrictions . . . . . . . . . . . . 107
3.6 Arithmetic Logic Unit (ALU) . . . . . . . . . . 108
3.6.1 Functional Summary . . . . . . . . . . . . . . 108
3.6.1.1 ALU Implementation Notes . . . . . . . . . . 109
3.6.1.2 SMUL Step Definition . . . . . . . . . . . . 110
3.6.1.3 UDIV Step Definition . . . . . . . . . . . . 111
3.6.1.4 Raw ALU Condition Codes . . . . . . . . . . 112
3.6.2 Microcode Restrictions . . . . . . . . . . . . 113
3.7 Multiplier Quotient Register . . . . . . . . . . 114
3.7.1 Functional Summary . . . . . . . . . . . . . . 114
3.7.2 Microcode Restrictions . . . . . . . . . . . . 114
3.8 PSL Logic . . . . . . . . . . . . . . . . . . . 115
3.8.1 I BOX Usage Of The PSL And Trace Logic . . . . 115
3.8.2 M BOX, INT_CTRL And BIU Usage Of PSL . . . . . 115
3.8.3 PSL Distribution . . . . . . . . . . . . . . . 115
3.8.4 PSL<3:0> - Condition Code Bits . . . . . . . . 116
3.8.5 Microcode Restrictions . . . . . . . . . . . . 116
3.9 Condition Code Logic . . . . . . . . . . . . . . 117
3.9.1 PSL CC Register, PSL<3:0> . . . . . . . . . . 118
3.9.1.1 Loading Of The PSL CC Register . . . . . . . 118
3.9.1.2 PSL Condition Code Map . . . . . . . . . . . 119
3.9.2 ALU CC Register . . . . . . . . . . . . . . . 119
3.9.3 VAX Restart Flag . . . . . . . . . . . . . . . 120
3.9.4 Integer Overflow Logic . . . . . . . . . . . . 121
3.9.5 Branch Test Logic . . . . . . . . . . . . . . 121
3.9.6 Microcode Restrictions . . . . . . . . . . . . 122
3.10 RLOG . . . . . . . . . . . . . . . . . . . . . . 123
3.10.1 Implementation Notes . . . . . . . . . . . . . 123
3.10.2 Microcode Restrictions . . . . . . . . . . . . 123
3.11 State Logic . . . . . . . . . . . . . . . . . . 124
3.11.1 Microcode Restrictions . . . . . . . . . . . . 125
3.12 Opcode Register . . . . . . . . . . . . . . . . 126
3.12.1 Microcode Restrictions . . . . . . . . . . . . 126
3.13 Summary Of E BOX Microcode Restrictions . . . . 127
3.13.1 Register File . . . . . . . . . . . . . . . . 127
3.13.2 Program Counter (PC Register) . . . . . . . . 127
3.13.3 Constant Generator . . . . . . . . . . . . . . 127
3.13.4 SC Logic . . . . . . . . . . . . . . . . . . . 127
3.13.5 Shifter . . . . . . . . . . . . . . . . . . . 127
3.13.6 ALU . . . . . . . . . . . . . . . . . . . . . 128
3.13.7 Q Register . . . . . . . . . . . . . . . . . . 128
3.13.8 PSL Logic . . . . . . . . . . . . . . . . . . 128
3.13.9 CC Logic . . . . . . . . . . . . . . . . . . . 128
3.13.10 RLOG . . . . . . . . . . . . . . . . . . . . . 128
3.13.11 STATE . . . . . . . . . . . . . . . . . . . . 129
3.13.12 OPCODE REGISTER . . . . . . . . . . . . . . . 129
3.14 E BOX Microcode Visible State . . . . . . . . . 130
3.15 E BOX Schematic Inventory . . . . . . . . . . . 131
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3.16 E BOX Global Signal Timing . . . . . . . . . . . 133
3.17 E BOX Internal Signal Timing . . . . . . . . . . 140
3.18 Change Requests (ECO) . . . . . . . . . . . . . 171
3.19 ISSUES . . . . . . . . . . . . . . . . . . . . . 172
4 MEMORY (M) BOX . . . . . . . . . . . . . . . . . . 173
4.1 M Box Overview . . . . . . . . . . . . . . . . . 173
4.1.1 Introduction . . . . . . . . . . . . . . . . . 173
4.1.2 Microinstruction Control Of The M Box . . . . 173
4.1.2.1 Memory Requests . . . . . . . . . . . . . . 174
4.1.2.2 Non Memory Request Microinstructions . . . . 178
4.1.3 Translation Buffer Description . . . . . . . . 178
4.1.4 Microcode Flows . . . . . . . . . . . . . . . 179
4.1.4.1 Longword References . . . . . . . . . . . . 180
4.1.4.2 Memory References That Use DL . . . . . . . 181
4.1.5 Registers . . . . . . . . . . . . . . . . . . 182
4.2 Function Descriptions . . . . . . . . . . . . . 183
4.2.1 Memory Address Logic . . . . . . . . . . . . 184
4.2.1.1 VA (Virtual Address) Register . . . . . . . 184
4.2.1.2 VAP (VA Prime) Register . . . . . . . . . . 184
4.2.1.3 VIBA (Virtual Instruction Buffer Address)
Register . . . . . . . . . . . . . . . . . . 185
4.2.1.4 + 4 Adder . . . . . . . . . . . . . . . . . 185
4.2.2 TB . . . . . . . . . . . . . . . . . . . . . . 185
4.2.2.1 PTEs . . . . . . . . . . . . . . . . . . . . 186
4.2.2.2 NLU . . . . . . . . . . . . . . . . . . . . 188
4.2.2.3 TB Data Path . . . . . . . . . . . . . . . . 188
4.2.2.4 TB Fills From Memory . . . . . . . . . . . . 190
4.2.2.5 TB Invalidate Logic . . . . . . . . . . . . 191
4.2.2.6 TB Miss Logic . . . . . . . . . . . . . . . 191
4.2.2.7 TB Summary . . . . . . . . . . . . . . . . . 191
4.2.3 Access Logic . . . . . . . . . . . . . . . . . 193
4.2.3.1 Privilege Check Logic . . . . . . . . . . . 193
4.2.3.2 Length Check Logic . . . . . . . . . . . . . 193
4.2.3.3 Inhibit IB Fill Logic . . . . . . . . . . . 194
4.2.3.4 MMGT.STATUS . . . . . . . . . . . . . . . . 194
4.2.3.5 MBOX.STATUS . . . . . . . . . . . . . . . . 195
4.2.3.6 MREF.STATUS . . . . . . . . . . . . . . . . 196
4.2.4 Memory Management Microtrap Logic . . . . . . 196
4.2.4.1 Partial PSL Logic . . . . . . . . . . . . . 196
4.2.4.2 Cross Page Detection Logic . . . . . . . . . 197
4.2.4.3 Microtrap And Abort Determination Logic . . 197
4.2.5 Memory Management Controller . . . . . . . . . 199
4.2.5.1 Trap Disable Logic . . . . . . . . . . . . . 199
4.2.5.2 Reexecute Reference Logic . . . . . . . . . 199
4.2.5.3 REPROBE Flag - . . . . . . . . . . . . . . . 200
4.2.5.4 Memory Management Enable Logic . . . . . . . 200
4.2.6 Second IDAL Cycle Detection Logic . . . . . . 200
4.2.6.1 REQ_2ND_REF Logic . . . . . . . . . . . . . 201
4.2.7 M Box Data Latches And Positioners . . . . . . 201
4.2.7.1 M Box Data Latch And Byte Rotator . . . . . 201
4.2.7.2 Internal Byte Mask . . . . . . . . . . . . . 202
4.2.8 Control Signals Sent To BIU . . . . . . . . . 203
4.2.8.1 BIU_NOP . . . . . . . . . . . . . . . . . . 203
4.2.9 IB_FILL_VALID . . . . . . . . . . . . . . . . 203
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4.2.10 MBOXBM . . . . . . . . . . . . . . . . . . . . 204
4.2.11 Control Signals Sent To E Box . . . . . . . . 204
4.2.11.1 WSEL_UPDATE_H . . . . . . . . . . . . . . . 204
4.2.11.2 REG_WRITE_H . . . . . . . . . . . . . . . . 204
4.2.11.3 SET_RESTART . . . . . . . . . . . . . . . . 204
4.2.11.4 NOT_MEM_REQ_R_H . . . . . . . . . . . . . . 204
4.2.11.5 MW_TO_W_H . . . . . . . . . . . . . . . . . 205
4.3 M Box Intersection And Intrasection Signals . . 205
4.3.1 M BOX Global Signal Timing . . . . . . . . . . 205
4.3.2 M BOX Internal Signal Timing . . . . . . . . . 214
4.4 ISSUES . . . . . . . . . . . . . . . . . . . . . 251
5 CACHE . . . . . . . . . . . . . . . . . . . . . . 253
5.1 Ram Array And Sense Amps . . . . . . . . . . . . 254
5.2 Address Selection And Decode . . . . . . . . . . 255
5.3 Tag Data Path . . . . . . . . . . . . . . . . . 256
5.3.1 M Box Address Latch . . . . . . . . . . . . . 258
5.3.2 Parity Generator/Checker . . . . . . . . . . . 258
5.3.3 Match Address Latch . . . . . . . . . . . . . 258
5.3.4 Address Match Detection . . . . . . . . . . . 258
5.3.5 Tag Write Mux . . . . . . . . . . . . . . . . 258
5.4 Data Array Drivers . . . . . . . . . . . . . . . 259
5.4.1 IDAL Input Buffer . . . . . . . . . . . . . . 260
5.4.2 Data Multiplexer . . . . . . . . . . . . . . . 261
5.4.3 IDAL Output Buffer . . . . . . . . . . . . . . 261
5.5 Cache Control . . . . . . . . . . . . . . . . . 261
5.5.1 Operation Decode . . . . . . . . . . . . . . . 262
5.5.2 Set Selection . . . . . . . . . . . . . . . . 263
5.5.3 Multiple Write Control . . . . . . . . . . . . 264
5.5.4 Refresh Counter . . . . . . . . . . . . . . . 264
5.6 Cache Timing . . . . . . . . . . . . . . . . . . 264
6 BUS INTERFACE UNIT (BIU)- . . . . . . . . . . . . 266
6.1 BIU Controlled Pins . . . . . . . . . . . . . . 266
6.1.1 Internal Pin Names . . . . . . . . . . . . . . 267
6.2 BIU Controlled Internal Bus - IDAL BUS
(G_S%IDAL_H<31:0>) . . . . . . . . . . . . . . . 267
6.3 BIU Logic Blocks . . . . . . . . . . . . . . . . 267
6.3.1 IDAL Control Machine . . . . . . . . . . . . . 267
6.3.2 DAL Control Machine . . . . . . . . . . . . . 268
6.3.3 Cache Disable Register (CADR) . . . . . . . . 268
6.3.4 Low Memory System Error Register (MSER) . . . 269
6.3.4.1 DAL H Parity . . . . . . . . . . . . . . . 270
6.3.5 MIB Decoder . . . . . . . . . . . . . . . . . 271
6.3.6 CFPA Machine . . . . . . . . . . . . . . . . . 272
6.4 Descriptions Of BIU Cycles . . . . . . . . . . . 272
6.4.1 DMA Cycle - . . . . . . . . . . . . . . . . . 273
6.4.2 Data Read Cycle - . . . . . . . . . . . . . . 273
6.4.3 Data Write Cycle - . . . . . . . . . . . . . . 274
6.4.4 CFPA Cycles - . . . . . . . . . . . . . . . . 274
6.4.4.1 Passing Opcode Information To The CFPA . . . 274
6.4.4.2 Passing Operands To The CFPA . . . . . . . . 276
6.4.4.3 Passing Results Back From The CFPA . . . . . 277
6.4.4.4 POLY Protocol . . . . . . . . . . . . . . . 278
6.4.4.5 CFPA Present Indication . . . . . . . . . . 279
6.4.4.6 CFPA Forced Termination . . . . . . . . . . 279
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6.4.4.7 Sample CFPA Timing . . . . . . . . . . . . . 279
6.4.4.8 CFPA Interface Overhead . . . . . . . . . . 285
6.4.5 Instruction Stream Read Cycle . . . . . . . . 287
6.4.6 IDLE Cycle - . . . . . . . . . . . . . . . . . 288
6.4.7 Output Pin Status On RESET L . . . . . . . . . 288
6.4.8 Table Of Interesting Pad Values And Chip
Functions During Memory Cycles . . . . . . . . 288
6.5 IDAL State Machine Definition . . . . . . . . . 289
6.6 DAL State Machine Definition . . . . . . . . . . 291
6.7 Stall And Trap Behavior Of The BIU - A Summary . 292
6.7.1 Mbox_stall - What It Means And When It's Used 292
6.7.2 Stall . . . . . . . . . . . . . . . . . . . . 293
6.7.3 BIU Trap Request . . . . . . . . . . . . . . . 293
6.7.4 BIU Trap Vectors . . . . . . . . . . . . . . . 293
6.7.5 CFPA Trap Request . . . . . . . . . . . . . . 293
6.7.6 CFPA Exception Trap Vectors . . . . . . . . . 294
6.8 BIU Internal Signal Timing . . . . . . . . . . . 295
6.9 BIU Internal Signal Timing . . . . . . . . . . . 296
7 MICROSEQUENCER . . . . . . . . . . . . . . . . . . 333
7.1 Busses . . . . . . . . . . . . . . . . . . . . . 333
7.1.1 Microaddress Bus (MAB) <10:0> . . . . . . . . 333
7.1.2 I Box Microaddress Bus (IMAB) <10:0> . . . . 333
7.1.3 Microtest Bus (UTEST) <2:0> . . . . . . . . . 334
7.1.4 Microinstruction Bus (MIB) <40:0> . . . . . . 334
7.1.5 Current Microaddress Bus (CMAB) <10:0> . . . . 334
7.1.6 Incremented Current Microaddress Bus (ICMAB)
<10:0> . . . . . . . . . . . . . . . . . . . . 334
7.1.7 Microstack Input Bus (USIB) <10:0> . . . . . . 334
7.1.8 Microstack Data Bus (USDB) <10:0> . . . . . . 335
7.1.9 Microstack Output Bus (USOB) <10:0> . . . . . 335
7.1.10 Test_MAB Bus (TEST_MAB) <10:0> . . . . . . . . 335
7.1.11 Microtrap Address Bus (UTRAB) <6:4> . . . . . 335
7.2 Microsequencer Sections . . . . . . . . . . . . 335
7.2.1 Microstack (USTACK) [0:7] . . . . . . . . . . 335
7.2.2 Current Microaddress Latch (CMAL) . . . . . . 336
7.2.3 Current Microaddress Incrementer And Latch
(CMAI) . . . . . . . . . . . . . . . . . . . . 336
7.2.3.1 Microcode Notes (MICROCODE ALLOCATION
RESTRICTION) . . . . . . . . . . . . . . . . 336
7.2.4 Microstack Input Mux (USIM) . . . . . . . . . 336
7.2.5 Microstack Write Buffer (USWB) . . . . . . . . 337
7.2.6 Microaddress Bus Mux (MAB Mux) . . . . . . . . 337
7.2.7 Microaddress Bus Latch (MAB Latch) . . . . . . 338
7.2.8 Microtrap Address Generator (UTRAG) . . . . . 338
7.2.9 STALL Latch (SL) . . . . . . . . . . . . . . . 338
7.3 Control Logic . . . . . . . . . . . . . . . . . 339
7.3.1 MAB Mux Control Logic . . . . . . . . . . . . 339
7.4 Timing Summary . . . . . . . . . . . . . . . . . 340
7.5 Functional Description . . . . . . . . . . . . . 340
7.5.1 Microsequencer Control Interpretation . . . . 340
7.5.2 Branch Format . . . . . . . . . . . . . . . . 341
7.5.3 Branch Offset (BO) MIB<6:0> . . . . . . . . . 341
7.5.4 Branch Condition Select (BCS) MIB<11:7> . . . 342
7.5.5 Jump Format . . . . . . . . . . . . . . . . . 342
CVAX CPU CHIP DESIGN SPECIFICATION Page 8
TABLE OF CONTENTS
7.5.6 Subroutine Control Bit (SB) MIB<11> . . . . . 343
7.5.7 Jump Address Field MIB<10:0> . . . . . . . . . 343
7.5.8 Microtrap Mechanism . . . . . . . . . . . . . 343
7.5.9 Microsequencer Test Mode . . . . . . . . . . . 344
7.6 Microsequencer Test Hooks . . . . . . . . . . . 344
7.7 Microsequencer Global Signal Dictionary . . . . 345
7.8 Microsequencer Internal Signal Dictionary . . . 348
7.9 Microsequencer Block Diagram . . . . . . . . . . 351
7.10 Change Requests ( ECO ) . . . . . . . . . . . . 352
7.11 ISSUES . . . . . . . . . . . . . . . . . . . . . 352
8 CONTROL STORE . . . . . . . . . . . . . . . . . . 354
8.1 Functional Summary . . . . . . . . . . . . . . . 354
8.2 MIB Latch/MIB Drivers . . . . . . . . . . . . . 355
8.3 Control Store Test Hooks . . . . . . . . . . . . 355
8.4 Control Store Block Diagram . . . . . . . . . . 356
8.5 Control Store Signal Dictionary . . . . . . . . 357
8.6 Change Requests ( ECO ) . . . . . . . . . . . . 359
8.7 Issues . . . . . . . . . . . . . . . . . . . . . 359
9 INTERRUPT LOGIC . . . . . . . . . . . . . . . . . 361
9.1 Interrupt Latches . . . . . . . . . . . . . . . 361
9.2 Highest Software Interrupt Register (HSIR). . . 361
9.3 Interrupt Priority Encoder . . . . . . . . . . 362
9.4 Interrupt IPL And Comparator . . . . . . . . . . 363
9.5 Microcode Notes . . . . . . . . . . . . . . . . 363
9.6 Microcode Restrictions . . . . . . . . . . . . . 364
9.7 Block Diagram . . . . . . . . . . . . . . . . . 365
9.8 OPEN ISSUES . . . . . . . . . . . . . . . . . . 366
10 CLOCK LOGIC . . . . . . . . . . . . . . . . . . . 367
10.1 Clock Input Buffer - Phase Separator . . . . . . 368
10.2 RESET_L Input Buffer . . . . . . . . . . . . . . 368
10.3 Phase Select Logic . . . . . . . . . . . . . . . 368
11 CONTROL FIELDS SUMMARY . . . . . . . . . . . . . . 369
11.1 Data Path Control Formats . . . . . . . . . . . 369
11.2 Microsequencer Control Formats . . . . . . . . . 369
11.3 General Fields . . . . . . . . . . . . . . . . . 371
11.3.1 B_Bus Select (B) Field . . . . . . . . . . . . 371
11.3.2 Destination (DST) Field . . . . . . . . . . . 371
11.3.3 Condition Code (CC) Field . . . . . . . . . . 371
11.3.4 A_Bus Select (A) Field . . . . . . . . . . . . 372
11.3.5 Miscellaneous (MISC) Field . . . . . . . . . 372
11.4 BASIC Microinstruction . . . . . . . . . . . . . 374
11.4.1 BASIC Function (BASIC.FNC) Field . . . . . . . 374
11.4.2 Length (L) Field . . . . . . . . . . . . . . . 375
11.5 CONSTANT Microinstruction . . . . . . . . . . . 376
11.5.1 CONSTANT Position (POS) Field . . . . . . . . 376
11.5.2 CONSTANT Destination (DS) Field . . . . . . . 376
11.5.3 CONSTANT Function (CONST.FNC) Field . . . . . 376
11.6 SHIFT Microinstruction . . . . . . . . . . . . . 378
11.6.1 SHIFT Value (SHIFT.VAL) Field . . . . . . . . 378
11.6.2 SHIFT Function Fields (SHIFT.DIR, DST) . . . . 378
11.7 MEM REQ Microinstruction . . . . . . . . . . . . 379
11.7.1 MEM REQ Function (MEMREQ.FNC) Field . . . . . 379
11.7.2 MEM REQ Length (L) Field . . . . . . . . . . . 380
11.7.3 MEM REQ Read/Write (RW) Field . . . . . . . . 380
CVAX CPU CHIP DESIGN SPECIFICATION Page 9
TABLE OF CONTENTS
11.7.4 MEM REQ Access Control (MEMREQ.ACC) Field . . 380
11.8 SPECIAL Microinstruction . . . . . . . . . . . . 383
11.8.1 SPECIAL Condition Code (MISC1) Field . . . . . 383
11.8.2 SPECIAL Function (MISC2) Field . . . . . . . . 383
11.8.3 SPECIAL Control Flags (MISC3) Field . . . . . 384
11.9 BRANCH Microinstruction . . . . . . . . . . . . 385
11.9.1 Branch Condition Select (BCS) Field . . . . . 385
11.9.2 Branch Offset (BO) Field . . . . . . . . . . . 386
11.10 JUMP Microinstruction . . . . . . . . . . . . . 387
11.10.1 Subroutine (SB) Field . . . . . . . . . . . . 387
11.10.2 Jump Address Field . . . . . . . . . . . . . . 387
12 TEST LOGIC . . . . . . . . . . . . . . . . . . . . 388
12.1 Observability Logic . . . . . . . . . . . . . . 388
12.1.1 CWB Logic . . . . . . . . . . . . . . . . . . 388
12.2 Control Logic . . . . . . . . . . . . . . . . . 388
12.2.1 Normal State . . . . . . . . . . . . . . . . . 389
12.2.2 Test State . . . . . . . . . . . . . . . . . . 389
12.2.2.1 TEST Pin . . . . . . . . . . . . . . . . . . 389
12.2.2.2 Internal MAB . . . . . . . . . . . . . . . . 389
12.2.2.3 External MAB . . . . . . . . . . . . . . . . 389
12.2.2.4 Force Broadcast . . . . . . . . . . . . . . 389
12.2.2.5 Configuration Latch . . . . . . . . . . . . 390
12.2.2.6 Loading Configuration Latch . . . . . . . . 390
12.3 Shift Register Locations . . . . . . . . . . . . 390
12.3.1 MIB (Shift Register #1) . . . . . . . . . . . 390
12.3.2 I Box IPLA (Shift Register #2) . . . . . . . . 391
12.3.3 Cache Refresh Address Generator/Reducer (Shift
Register #3) . . . . . . . . . . . . . . . . . 392
12.3.4 Main Reducer (Shift Register #4) . . . . . . . 392
12.4 Test Control Pins . . . . . . . . . . . . . . . 393
12.5 Block Diagram . . . . . . . . . . . . . . . . . 394
13 APPENDIX: GLOBAL SIGNAL DICTIONARY . . . . . . . . 395
14 APPENDIX: BLOCK DIAGRAM . . . . . . . . . . . . . 414
15 APPENDIX: CHIP INTERCONNECT DIAGRAM . . . . . . . 416
CVAX CPU CHIP DESIGN SPECIFICATION Page 10
REVISION HISTORY
REVISION HISTORY
----------------
REV DATE REASON
--- ---- ------
3.00 Pass 3.00 changes incorporated into spec.
2.00 20-Feb-87 Pass 2.00 changes incorporated into spec.
1.06 23-Jun-86 ALL ECOs (as of 1-Jun-86) incorporated into spec.
1.05 28-Oct-85 ALL ECOs (as of 15-Oct-85) incorporated into spec.
Section 6: rewritten to reflect microarchitecture.
Section 12 : Renamed TEST_0 to TEST and TEST_1 to TEST_OUT (mux'ed with CWB, all registers now sample on PHI1.
Section 14 : deleted CM and BR, added CWB, INHIB_CP_OUT and MW_TO_W,
changed TEST_0 to TEST, TEST_1 to TEST_OUT, FPU_CC<2:0> to FPU_CCZ, FPU_CCV, FPU_CCN
changed timing on LOAD_PSL
1.04 6-Sep-85 Section 12.4.3 : Changed BROADCAST bit definition to forcing BASIC_BROADCAST only.
Section 14 : deleted BCOND_TRUE, added all test reducer outputs and scan/reducer controls
added TEST_BRO and ONE_SLOT_FREE.
1.03 20-Aug-85 All ECOs (as of 5-14-Aug-85) incorporated into spec.
Section 9 : changed microcode restriction on use of BRANCH IID after changing HSIR,IPL, or ICCS<6>,
changed value of WSPUR<7:4> during a READ HSIR to 111, added restrictions on
what kind of cycle can immediately follow a READ INT.ID
Section 14 : add LD_VIBA_AND_PC, remove WILL_LOAD_VIBA and WILL_LOAD_PC, modify waveforms on
IID_IRQ and FPD_INT_PENDING, assertion of IB_FILL_ERR is now LOW
Section 14 : added ICCS_6, deleted DPC_VALID, modified timing of DELTA_PC,IB_FILL_REQ,IID_LD
1.02 26-Jun-85 Section 2 : fixed address specifications, added WSN definition, fixed testability stuff
Section 3.9 : Change CC Logic to reflect FPU CCs being mapped through CC Map. Also added
ACBD, ACBF, and ACBD to Branch Test Logic.
Section 3.11 : Change State Logic to reflect bit clearing groups.
Section 3.14 : Updated Microcode Restrictions for Q Register, PSL and RLOG.
Section 9 : modified spec to reflect redefinition of SISR to HSIR
Section 10 : modified spec to reflect change in method of inplementing phase synchronization
Section 14 : added G_S%FLUSH_H chged CLK1_IN to CLKA and CLK2_IN to CLKB and LD_PSL_FROM_FPU to LOAD_FPU_CC
Section 14 : added G_S%FPD_INT_PENDING_H AND G_S%FP_INTEGER_H deleted IBOX_TRAP_DRY and IBOX_TRAP_HLT
Section 14 : added G_S%PSL_T and G_S%READ_HIT
1.01 3-May-85 Section 2 : edits based on RMS's comments...notably integer overflow, 2.1.2 was wrong, syntax problems
Sections 2.3.1,2.3.4 : Changed I-box microaddress format for execution dispatch, specifier dispatch
Section 3.1.4.1: Removed dual A-Bus addresses where not needed
Section 3.5.1: Changed default ALU operation to PASS.B for MEMREF/MXPR/READ.
Section 3.5.1.3: Defined PSL.V for SMULS Step
Section 3.8.3: Removed notes section and added PSL Distribution Section
Section 3.9.4: Modified Integer Overflow Logic. It is now a trap line to uSEQ.
Section 9.* : Added SISR to spec
Section 9.2 : Changed MXPS[INT.ID] to read out to W_SPUR<4:0>
Section 9.4 : Added MEMERR and CRD to verbal description
Section 11.* : Control field summary changed to reflect actual microcode
Section 12.3 : Added internal pull-down resistor on TEST_0
Section 12.6 : Changed CP to CP.STA and CP.DAT
Section 13.0 : Eliminated from Design Specification
Section 14.* : Added BIU <-> CACHE signals
Section 14.* : Added WILL_LOAD_VIBA,chg'd LD_PSL_FROM_FPU,LOAD_PSL,READ_DATA_PRS
Section 14.* : Added MBOX_BM,MW_BUS,MW_DRIVE to signal list, chg assertion of all traps and STALL
to '_L', chg spacing to allow longer names. Added chip pins, and bus capacitance
removed MBOX from IB_DATA_PRS dest.
1.00 26-Mar-85 Preliminary version.
CVAX CPU CHIP DESIGN SPECIFICATION Page 11
INTRODUCTION
1 INTRODUCTION
1.1 Scope
This document specifies the design of a CMOS/VLSI chip (CVAX) that
implements a VAX central processor. This specification describes the
internal organization and characteristics of the CPU chip. This
specification does not describe the operation of CVAX. For further
information, the applicable documents should be consulted.
1.2 Applicable Documents
VAX Architecture Standard (DEC Standard 032)
CVAX CPU Chip Engineering Specification
CVAX Clock Chip Engineering Specification
CVAX Microcode
1.3 CVAX CPU Chip Organization
The CVAX CPU chip consists of the following major sections.
1.3.1 Instruction Unit (I Box) -
The Instruction Unit contains the instruction prefetch buffer, the initial
decode PLA, and associated logic. It prefetches the instruction stream,
generates microprogram fork addresses, and provides instruction data to
the E Box.
1.3.2 Execution Unit (E Box) -
The Execution Unit contains the VAX register file, the microcode scratch
register file, the page table base registers, the arithmetic/logical unit
(ALU), and other computational facilities. It performs address and data
computations for executing VAX instructions and address translations.
1.3.3 Memory Translation Unit (M Box) -
The Memory Translation Unit contains the translation buffer, the page
table length registers and comparators, and the address translation logic.
It performs virtual to physical address translations. In addition, the M
Box controls the incoming and outgoing data latches, rotators, and
swappers.
CVAX CPU CHIP DESIGN SPECIFICATION Page 12
INTRODUCTION
1.3.4 Bus Interface Unit (BIU) -
The Bus Interface Unit controls the arbitration of the major intrachip
data bus (IDAL); the protocol on the external interface; and the operation
of the Cache.
1.3.5 Microsequencer -
The Microsequencer determines the address of the next microword to be
fetched and executed from the Control Store. It also oversees the
generation and execution of microtraps.
1.3.6 Interrupt Logic -
The Interrupt Logic mediates hardware interrupt requests against the
current IPL and generates an interrupt request to the I Box, if necessary.
1.3.7 Control Store -
The Control Store contains 1600 x 41 words of microcode which direct all
operations in the chip.
1.3.8 Cache -
The onchip Cache contains 1k bytes of high-speed memory for local storage
of frequently referenced memory data.
1.3.9 Clock Logic -
The Clock Logic shapes the two MOS level input clocks into the four
precision internal clocks.
1.4 Block Diagram
A block diagram of the chip may be found at the end of this specification.
CVAX CPU CHIP DESIGN SPECIFICATION Page 13
INSTRUCTION (I) BOX
2 INSTRUCTION (I) BOX
The I Box controls instruction sequencing and prefetching. During the
microcycle, the I box predicts what the next dispatch should be. Once the
microinstruction arrives, the I Box executes the appropriate dispatch and
state changes.
The I Box cycle begins when the Microsequencer issues a microinstruction
with a DEC.NEXT code in the Branch Condition Select (BCS) field and the
specifier counter is set to 0 (by the completion of a previous instruction
or the execution of a LOAD_V&PC microinstruction). At IID, the I Box
selects a microcode address to drive to the Microsequencer. This
microcode address points to the start of the microprogram for the
instruction being processed. If the instruction has specifiers, the
microaddress dispatches to the appropriate Specifier Decode routine. If
there are no specifiers, the microaddress points at the execution flow for
the instruction, and the execution phase happens immediately.
The specifier flows end with a microinstruction that contains another
DEC.NEXT command in the BCS field. At this point, the I Box sends either
the address for the routine to analyze the second specifier, or, if there
are no other specifiers, the address of the execution microcode for the
instruction. The specifier flows are called for each specifier in the
instruction. Once all specifiers have been decoded, the I box sends a
dispatch address for the execution flow for the instruction.
The I Box instruction prefetcher operates in parallel with the execution
hardware on the chip. Whenever a longword in the queue is empty, the
queue is not halted, and the BIU has free cycles, a request is issued to
read the next aligned longword in the instruction stream. This longword
is copied into the PFQ. When a LOAD_V&PC microinstruction is detected,
the PFQ is flushed, and new instructions must be fetched before the
processor can proceed. In this case, the I Box sends a dummy address as a
reply to any DEC.NEXT request, and microcode casing handles all LOAD_ID
requests. In either case, the microcode enters a loop until instruction
data arrives at the I Box.
The I Box has four sections: the Prefetcher, the IPLA, the Next Address
Generator, and some miscellaneous registers and control.
2.1 Prefetcher
2.1.1 Prefetcher Data Path -
The Prefetcher Data Path handles I Stream data. It holds up to 3
prefetched longwords from memory, rotates the instructions to bring the
opcode to the front, and stores literals and displacements for the E Box.
The datapath is maintained by the Prefetcher Control and consists of the
following blocks:
CVAX CPU CHIP DESIGN SPECIFICATION Page 14
INSTRUCTION (I) BOX
2.1.1.1 Instruction Prefetch Queue -
The Instruction Prefetch Queue consists of three longword registers, each
of which can hold an aligned longword from memory. The registers comprise
a three-entry queue. Data is loaded into the tail of the queue from the
the Internal DAL and stored in the empty register closest to the head of
the queue.
2.1.1.2 Instruction Byte Rotator -
The Instruction Byte Rotator can select up to six contiguous bytes in the
Prefetch Queue (for example, an opcode, a specifier, and four bytes of
data) starting at any byte in the lowest longword. The position of the
starting byte is specified by the IB Pointer (low two bits of the PC).
2.1.1.3 Instruction Data (ID) Register -
This longword register is the mechanism by which the E Box data path gets
data from the instruction stream (displacements, etc.). Data is loaded
from the Byte Rotator, either automatically by the I Box or explicitly by
the microinstruction; it is sign extended to longword in the same cycle in
which it is loaded.
The ID register is automatically loaded by the I Box when:
o The Microaddress Generator detects that the opcode is a branch
instruction (opcodes 10-15,18-1F,30-31). The IDR is loaded with
the byte or word branch displacement and sign extended to
longword length.
o The Microaddress Generator detects that the specifier mode is
byte, word, or longword displacement (specifier mode A, B, C, D,
E, F). The bytes containing the byte, word, or longword
displacement are loaded. The register is then sign extended to
longword length. NOTE: Specifiers of type 8F are NOT included
here. Immediate operands must be explicitly moved to the IDR by
microcode.
o The Microaddress Generator detects that the specifier byte is 9F
(absolute). The four bytes containing the address of the operand
are loaded into the ID register.
Explicit loads of the ID register can be done by microcode CASE. The
amount of data extracted from the instruction stream is based on the Data
Length register. When LOAD ID CASE is issued, any of three things may
happen. The IDR may be loaded properly, not loaded because the PFQ is dry
and not halted, or not loaded because the PFQ is dry and halted. In the
second case, the microcode cases to a location which contains another LOAD
ID case, forcing a loop. In the third case, a different case target is
CVAX CPU CHIP DESIGN SPECIFICATION Page 15
INSTRUCTION (I) BOX
used; the target address contains a call to a subroutine to resolve the
prefetching problem.
The ID register is sign extended based on the value of the DL register.
Note that the sign extension may change from its original value if DL is
changed before the data is read. For example: suppose the ID register
was loaded with a word offset for a branch. Now suppose that the MISC
field DL.BYTE is issued before the data is read to the B-bus. The data in
the ID register will now look like a sign- extended byte, effectively
destroying half of the offset data. Now suppose the DL register is
changed to WORD again before the data is read. In this case, there will
be no change in the ID register contents, and it will still look like a
sign-extended byte. The ID register may be read to the B-bus. It is
addressed through the B port as register 0A#16.
2.1.2 Prefetch Controller -
The BIU fetches I stream data whenever the Prefetch Controller requests it
and the DAL is available. The Prefetch Controller signals the BIU that it
wants I Stream data by asserting the IB_REQ line. It asserts IB_REQ only
when the PFQ has an empty longword AND the prefetcher is not halted.
If the I Stream read results in any kind of error (TB miss, data parity
error, etc.), the Hardware Prefetch Halt Bit is set and no more
prefetching is done. This prevents prefetching from interfering with
memory management operations. When the Prefetch Stack runs out of data, a
special microaddress (IE.IB.HALTED) is sent to the Microsequencer; a
microcode subroutine then handles the problem. The I Box does not react
immediately to prefetching errors because the prefetched data may not be
used. The Hardware Prefetch Halt Bit is cleared by the RESTART PREFETCH
command, and as a side effect of the MISC fields that load VIBA and PC.
The microcode can stop prefetching by setting the Microcode Prefetch Halt
Bit in the I Box. This microcode-controllable bit can be set and cleared
by the commands DISABLE PREFETCH and ENABLE PREFETCH. It is cleared by
the RESTART PREFETCH command.
A four bit register called the IB Pointer is kept to point to the next
valid byte in the lowest longword of the Prefetch Queue. As data is drawn
out of the stack by the Microaddress Generator, this pointer is
incremented by Delta PC. When the macroinstruction stream branches,
nothing in the stack is usable. It is flushed as a side effect of the
MISC fields that load VIBA and PC. Prefetching is started up again, and
the IB Pointer is set to the start of the new instruction ,i.e. it is set
equal to bits <1:0> of the PC.
2.2 The Instruction PLA (IPLA)
The IPLA contains information about VAX macroinstructions. IPLA inputs
are the eight-bit opcode and a ninth bit called XFD, which indicates an
CVAX CPU CHIP DESIGN SPECIFICATION Page 16
INSTRUCTION (I) BOX
extended opcode. The IPLA stores the following data for all valid opcodes
with one or more specifiers:
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+
| FPO | FPA | Execution Dispatch Address |Data Length|Data Length|Data Length|
|Instr|Instr| | spec 1 | spec 2 | spec 3 |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+
8 7 6 5 4 3 2 1 0
+-----+-----+-----+-----+-----+-----+-----+-----+-----+
|Access Type|Access Type|Access Type| Number of |
| spec 1 | spec 2 | spec 3 | Specifiers |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+
<23> The FPO bit is true if the instruction is an integer
instruction that is accelerated via the FPA. This bit is used
in conjunction with the F Box Instruction bit and the FPA
Present bit to enable data broadcasts to the FPA.
<22> The F Box Instruction bit is true if the opcode is for an F, D,
or G floating point instruction. It is NOT true if the opcode
is served by the CFPA but included in "warm" FPA functions.
This prevents an illegal opcode dispatch on optimized integer
instructions when there is no FPA in the system. If this bit
is true and there is no FPA present, an illegal opcode dispatch
is taken.
<21:15> These bits represent 7 of 11 bits for the execution dispatch
address.
<14:3> The IPLA has a multiplexor on some of its outputs. This mux
selects one of the six Data Length fields and one of the six
Access Type fields. This data is loaded into the AT/DL
Register.
<2:0> The specifier counter field contains the number of operands the
instruction requires. At IID, this value is loaded into the
specifier counter, which is decremented every time a specifier
dispatch is given. When the counter reaches 1, an execution
dispatch is done. When the counter reaches 0, an IID is
executed.
EXTRA AT/DL PLA
There is a supplementary PLA which holds the AT and DL
values for specifiers four through six if an instruction
has more than three operands.
CVAX CPU CHIP DESIGN SPECIFICATION Page 17
INSTRUCTION (I) BOX
2.3 Microaddress Generator
The Microaddress Generator creates microaddresses for entry points into
microcode flows for instruction execution, illegal opcodes, and specifier
decode. During PHI2 and PHI3, the Microaddress Generator predicts the
next dispatch based on the data in the Prefetch Queue (PFQ). The next
values of important I Box state registers are also predicted. At PHI4,
the microinstruction is decoded and selection from the possible choices
begins.
2.3.1 IID Dispatch (used When SPEC.CTR = 0) -
The IID dispatch takes one of three forms: exception dispatch, if an
unusual condition is pending when IID is detected; execution dispatch, if
the IID PLA shows that an instruction has no operands or the instruction
is a simple branch; and first specifier dispatch, which is used for all
other cases. Priority for IID dispatches is determined from the following
list:
o Exception dispatches, as ordered in the exception dispatch table
o Execute dispatches for zero operand instructions as per the
execution dispatch table
o Specifier dispatches as per the specifier dispatch table
2.3.1.1 IID Exception Dispatch -
Several exception conditions are checked by the I Box prior to an IID
dispatch. If one of these conditions is present, a special microaddress
is driven to handle the problem. Note that IID is not asserted for these
cases. The following table shows the exceptional conditions recognized
and the dispatch taken for each:
| VAX |INTERRUPT|PSL<TP>| IB | uADDR
| TRAP | PENDING | | DRY | (hex)
| REQUEST | | | |
| | | | |
+----------+---------+-------+--------+-----------------------------------
| 1 | x | x | x | IE.VAX.ARITH.TRAP 280
| 0 | 1 | x | x | IE.VAX.INTERRUPT 302
| 0 | 0 | 1 | x | IE.VAX.TRACE.TRAP 200
| 0 | 0 | 0 | 1 | IE.IID.STALL 7FE
CVAX CPU CHIP DESIGN SPECIFICATION Page 18
INSTRUCTION (I) BOX
2.3.1.2 IID Execution Dispatch -
If no exceptions are pending at IID and the IID PLA output indicates that
the instruction being decoded has no operands, an execution dispatch is
issued immediately. Note that an opcode of FD will be treated as a
zero-operand instruction. An illegal opcode dispatch occurs if the
instruction is a floating point type and there is no FPU present in the
system, or if the opcode is illegal. Note that illegal opcodes are
treated as zero operand instructions by the I Box. The table below shows
dispatch addresses for execution flows reachable from IID, in order of
decreasing priority:
(PC) | PSL.FPD | ADDRESS | DELTA PC | IDR FUNCTION | COMMENTS
------------+-----------+-----------------------+----------+--------------+------------------
XXXXXXXX | X | RSRV.INST.FLT 282 | 0 | NONE | ILLEGAL OPCODE DISPATCH
------------+-----------+-----------------------+----------+--------------+------------------
NOT FD#16 | 1 | FPD 380 | 1 | NONE | FIRST PART DONE DISPATCH
------------+-----------+-----------------------+----------+--------------+------------------
00000XXX | 0 | SEE TABLE OF "OTHER | 1 | NONE | 0 OPERAND INSTRUCTIONS
00X10000 | 0 | OPCODES" IN SECTION | 1 + b,w | IDR <-IB(b,w)| BSBB...BSBW
00X10001 | 0 | 2.10.4 | "" | " | BRB...BRW
0001001X | 0 | | | |
0001010X | 0 | | "" | " | ALL BRANCH INSTRUCTIONS
00011XXX | 0 | | | |
00000011 | 0 | | 1 | NONE | BPT INSTRUCTION
11111100 | 0 | | 1 | NONE | XFC INSTRUCTION
11111101 | X | | 1 | NONE | XFD (TWO BYTE OPCODES)
2.3.1.3 Specifier Dispatch -
If an instruction has specifiers, detection of an IID will cause a
dispatch to the general specifier flows based on the first specifier. The
table below describes the dispatch possibilities:
CVAX CPU CHIP DESIGN SPECIFICATION Page 19
INSTRUCTION (I) BOX
<7:4> <3:0>
Specifier Type | Spec | RN | Dispatch Address | Delta PC | IDR LOAD |
| | | |(add 1 at IID)| FUNCTION |
-------------------+--------+-----+-----------------------------+--------------+-------------------+
short literal | 0-3 | 0-F | SPEC.SH.LIT 080 | 1 | NONE |
index | 4 | 0-E | SPEC.INDEX 082 | 1 | NONE |
index | 4 | F | SPEC.RSRV.ADDR 08A | 1 | NONE |
register | 5 | 0-E | SPEC.REG 084 | 1 | NONE |
register | 5 | F | SPEC.RSRV.ADDR 08A | 1 | NONE |
register deferred | 6 | 0-E | SPEC.REG.DEFER 086 | 1 | NONE |
register deferred | 6 | F | SPEC.RSRV.ADDR 08A | 1 | NONE |
autodecrement | 7 | 0-E | SPEC.AUTODEC 088 | 1 | NONE |
autodecrement | 7 | F | SPEC.RSRV.ADDR 08A | 1 | NONE |
autoincrement | 8 | 0-E | SPEC.AUTOINC 08C | 1 | NONE |
autoincrement def | 9 | 0-E | SPEC.AUTOINC.DEFER 090 | 1 | NONE |
displacement | A,C,E | 0-F | SPEC.BWL.DISP 094 | 2,3,5 | IDR <- IB(BWL).SXT|
displacement def | B,D,F | 0-F | SPEC.BWL.DISP.DEFER 096 | 2,3,5 | IDR <- IB(BWL).SXT|
immediate | 8 | F | SPEC.IMMEDIATE 08E | 1 | NONE |
absolute | 9 | F | SPEC.ABSOLUTE 092 | 5 | IDR <- IB(LW) |
-------------------+--------+-----+-----------------------------+--------------+-------------------+
The following table shows the dispatch addresses for INDEXED operands:
<7:4> <3:0>
Specifier Type | Spec | RN | Dispatch Address | Delta PC | IDR LOAD |
| | | |(add 1 at IID)| FUNCTION |
-------------------+--------+-----+-----------------------------+--------------+-------------------+
short literal | 0-3 | 0-F | INDEX.SH.LIT 0C0 | 1 | NONE |
index | 4 | 0-E | INDEX.INDEX 0C2 | 1 | NONE |
index | 4 | F | INDEX.RSRV.ADDR 0CA | 1 | NONE |
register | 5 | 0-E | INDEX.REG 0C4 | 1 | NONE |
register | 5 | F | INDEX.RSRV.ADDR 0CA | 1 | NONE |
register deferred | 6 | 0-E | INDEX.REG.DEFER 0C6 | 1 | NONE |
register deferred | 6 | F | INDEX.RSRV.ADDR 0CA | 1 | NONE |
autodecrement | 7 | 0-E | INDEX.AUTODEC 0C8 | 1 | NONE |
autodecrement | 7 | F | INDEX.RSRV.ADDR 0CA | 1 | NONE |
autoincrement | 8 | 0-E | INDEX.AUTOINC 0CC | 1 | NONE |
autoincrement def | 9 | 0-E | INDEX.AUTOINC.DEFER 0D0 | 1 | NONE |
displacement | A,C,E | 0-F | INDEX.BWL.DISP 0D4 | 2,3,5 | IDR <- IB(BWL).SXT|
displacement def | B,D,F | 0-F | INDEX.BWL.DISP.DEFER0D6 | 2,3,5 | IDR <- IB(BWL).SXT|
immediate | 8 | F | INDEX.IMMEDIATE 0CE | 1 | NONE |
absolute | 9 | F | INDEX.ABSOLUTE 0D2 | 5 | IDR <- IB(LW) |
-------------------+--------+-----+-----------------------------+--------------+-------------------+
2.3.2 Second IID Dispatch ( Spec Counter = 0) -
If the opcode at IID is FD, the microcode branches to a location which
reissues the IID. Furthermore, the E Box sets the opcode register to 0FD
CVAX CPU CHIP DESIGN SPECIFICATION Page 20
INSTRUCTION (I) BOX
and increments PC by 1. When the second IID is executed, the opcode
register is set to 1xx, where xx is the second opcode byte. With
second.iid set, the I Box interprets an IID operation differently. This
special IID acts much like the normal one, but interrupts and the trace
bit are ignored. Furthermore, second IID prevents the backup PC from
being loaded with the current PC (this is an E Box function). This keeps
the backup PC from pointing to the second byte of a two-byte opcode.
Second IID is also used by microcode while waiting for the PFQ to fill
after a dispatch to XFD (due to PFQ dry and not halted condition) takes
place. The following table describes the dispatch possibilities at Second
IID time, in order of decreasing priority:
Specifier Type | Dispatch Address | Delta PC | IDR LOAD |
or Condition | | | FUNCTION |
----------------------------------+------------------------------+--------------+-------------------+
PFQ DRY, NOT HALTED | XFD 7FE | 0 | NONE |
PFQ DRY, HALTED | DEC.NEXT.HALTED 382 | 0 | NONE |
----------------------------------+------------------------------+--------------+-------------------+
Execute Dispatch | As per IID dispatch | 0 | NONE |
----------------------------------+------------------------------+--------------+-------------------+
SPECIFIER DISPATCH | SEE SPECIFIER DISPATCH TABLE (TREAT AS IID) |
----------------------------------+-----------------------------------------------------------------+
2.3.3 Specifier Decode Dispatches -
The specifier dispatch causes the I Box to examine the specifier byte. As
described above, if the spec counter is 1, the dispatch will be to the
execution flows. If the spec counter is 2, the dispatch logic must
examine the specifier mode and dispatch to optimized execution flows if
the mode is 5 (register). Otherwise, the dispatch will be to the
specifier flows. If the dispatch is to the execution flows, the address
will look like this:
Specifier Type| Dispatch Address | Comments
==============+============================+===========
Register Mode | 10xxxxxxx10 | optimized
Other Mode | 10xxxxxxx00 | similar to IID opcode dispatch
The dispatch will be from the following table, in order of decreasing
priority:
CVAX CPU CHIP DESIGN SPECIFICATION Page 21
INSTRUCTION (I) BOX
Specifier Type | Dispatch Address | Delta PC | IDR LOAD |
or Condition | | | FUNCTION |
----------------------------------+---------------------+--------------+-------------------+
EXECUTE (SPEC COUNTER = 1) | EXECUTION FROM IPLA | 0 | NONE |
----------------------------------+---------------------+--------------+-------------------+
PFQ DRY, NOT HALTED | DEC.NEXT.STALL | 0 | NONE |
PFQ DRY, HALTED | DEC.NEXT.HALTED | 0 | NONE |
----------------------------------+---------------------+--------------+-------------------+
OPTIMIZE | DISP. TO OPTIMIZED | | |
(SPEC.MODE = 5,SPEC.CTR = 2) | EXECUTION FLOWS | 1 | NONE |
NOTE: THIS CLEARS SPEC COUNTER | AS PER ABOVE TABLE | | |
----------------------------------+---------------------+--------------+-------------------+
SPECIFIER DISPATCHES | SEE SPECIFIER DECODE TABLE |
-------------------------------------------------------------------------------------------+
Illegal addressing modes
The illegal mode/access combinations are Register Mode (5)
with access type of Address (A) and Short Literal (0-3)
with access types of Address, Modify, or Field (A,M, or
V). If such a condition is detected, the MICROCODE will
go to RSRV.ADDR.FLT.
*
The index mode prefix is treated as a one-byte specifier.
The microcode issues a DEC.NEXT to parse the real
specifier; the I box sets a flag at index dispatch time
that indicates to the next cycle I box decode the presence
of the index mode specifier.
2.3.4 MicroAddress Format -
The following table shows the format for the I box microaddress bus
contents.
CVAX CPU CHIP DESIGN SPECIFICATION Page 22
INSTRUCTION (I) BOX
Dispatch Type Spec Counter Microaddress Comments
---------------------+-------------+------------------------------------+-------------------------------------
Exception | 0 | Fixed CONSTANTS | SEE TABLE IN SECTION 2.3.1.1
Execute | 1 | 10xxxxxxx00 | SEE TABLE IN SECTION 2.10.3
Optimized Execute | 2 | 10xxxxxxx10 | SEE TABLE IN SECTION 2.10.3
0-operand Execute | 0 | 001100xxxx0 | SEE TABLE IN SECTION 2.10.3
Illegal Opcode | 0 | RSRV.INST.FLT 282 |
IB Dry | any | DEC.NEXT.STALL 300 |
IB Halted & Dry | any | DEC.NEXT.HALTED 382 |
Normal Specifier | > 1 | 000100xxxx0 | SEE TABLE IN SECTION 2.3.1.3
Indexed Specifier | > 1 | 000110xxxx0 | SEE TABLE IN SECTION 2.3.1.3
---------------------+-------------+------------------------------------+-------------------------------------
2.3.5 Delta PC Logic -
The Delta PC logic is integrated with microaddress generation. It
generates a three bit value to be added to the PC when the next piece of
instruction data is used. Whenever data is not being requested from the
Prefetch Stack, delta PC must be zero. Delta PC is used by the PC
function of the E Box data path, and by the Prefetch Controller. The
controller uses it to increment the IB Pointer that specifies the next
byte to be used in the Prefetch Stack.
PREFETCH QUEUE DRY CALCULATION
These values for Delta PC may also be interpreted as the
minimum number of valid bytes which must be in the PFQ
prior to a dispatch for the dispatch to be succesful and
the PFQ to be considered NOT dry.
CVAX CPU CHIP DESIGN SPECIFICATION Page 23
INSTRUCTION (I) BOX
Condition Delta PC
--------------------------------
IID forks ( spec counter = 0 ):
Exceptions 0
FPD 1
Opc = Branch byte disp. 2
Opc = Branch word disp. 3
Opc = FD (hex) 1
Zero operand opc. 1
First Specifier see note ( + 1 for opcode)
PFQ dry 0
Specifier forks ( spec counter > 0 ):
Specifier Decode see note
Optimize (CTR=2,MODE=5) 1 (to skip over register specifier)
Execute (CTR = 1) 0 NOTE: OPTIMIZE DISPATCH CLEARS SPEC COUNTER
PFQ dry 0
LOAD ID:
DL=0 (BYTE) 1
DL=1 (WORD) 2
DL=2 (LONG) 4
DL=3 (QUAD) 4
PFQ DRY 0
NOTE:
In these cases the amount of data taken out of the Prefetch Stack depends
on the specifier mode.
Spec Mode Spec Code Delta PC
-------------------------------------------
byte disp. A 2
byte disp. deferred B 2
word disp. C 3
word disp. deferred D 3
longword disp. E 5
longword disp. def. F 5
ABSOLUTE 9(F) 5
other 0-9 1
If this is an IID fork, delta PC is increased by 1 to account for the
opcode.
2.4 Miscellaneous Register Descriptions
This section describes some of the registers in the I Box.
CVAX CPU CHIP DESIGN SPECIFICATION Page 24
INSTRUCTION (I) BOX
2.4.1 Current Specifier / Register Number Latch (SPEC.RN) -
The Current Specifier / Register Number Latch holds the address mode and
GPR address of the last specifier decoded. It is also used with the RLOG
facility in the E Box data path section. When RLOG is pushed, RN supplies
four bits of the data that is pushed. The SPEC.RN register can be read
via a mem_req microinstruction; RN can be written via a mem_req
microinstruction, as well.
SPEC.RN is loaded during any DEC.NEXT when the specifier counter is not =
1 with bits <7:0> of the specifier. Note that when the specifier is short
literal (modes 0-3), the SPEC.RN register holds the entire specifier.
Microcode gets the literal by reading it from this register. The RN.OLD
register is also part of the SPEC.RN logic. RN.OLD is updated only when
the specifier being decoded may be a destination address for the
instruction in progress. There is also a microcode command to load RN
with RN.OLD .
2.4.2 FPU Present -
Whenever RESET is asserted, one of the CP_STA lines is pulled down by the
CFPA if it is present. If the CFPA is not present, that CP_STA line will
be pulled up by an external resistor. The status of this pin will be
sensed by the FPA logic on CVAX, which will assert the signal
G_S%FPU_IS_THERE_H if the FPA is present. The I box will set the
FPU_PRESENT bit only if RESET is asserted and G_S%FPU_IS_THERE_H is
asserted. If the FPU_PRESENT bit is set, floating point instructions will
cause a normal GSD dispatch at IID. If this bit is clear and the IID PLA
entry for an instruction specifies F Box execution, an illegal opcode
dispatch occurs.
2.4.3 VAX Trap Request -
This bit can be set or cleared by SPECIAL MISC1 microinstructions. When
set, the I Box's next IID dispatch will be to a trap routine. The VTR bit
must be cleared by the handling routine before normal execution can be
resumed.
2.4.4 Specifier Counter -
This facility indicates which specifier is presently being decoded.
During an IID dispatch (spec counter = 0) where a normal dispatch happens,
the specifier counter is loaded with the number of specifiers for the
instruction as listed in the IPLA. At each specifier dispatch, it is
decremented. When the counter reaches 1, the next dispatch will be to the
execution flow. When the counter reaches 0, the next dispatch will be an
IID. The specifier counter is also used to address the working registers
CVAX CPU CHIP DESIGN SPECIFICATION Page 25
INSTRUCTION (I) BOX
for specifier decode addressing. The specifier counter is not decremented
at index mode dispatches (i.e. dispatches where INDEX_EXPECTED is set).
SPEC.CTR is cleared at execution of any microinstruction which loads VIBA
and PC. It is also cleared whenever a register-mode optimized execute
dispatch is generated.
2.4.5 Data Length And Access Type -
The data length and access type of the specifier presently being worked on
are kept in the AT/DL register.
The codes for the access type are:
0 A Address Source
1 V Field Source
2 R Read Source
3 M Modify Source
The access type portion of the AT/DL register may be written only on
specifier dispatches with a value from the IPLA.
The data length portion of the AT/DL register may be written in the
following ways:
o Automatically with a value from the IPLA on specifier dispatches.
o Forced by the MISC field.
o Forced to byte (00) at execution dispatches for four
instructions: SOBGTR,SOBLEQ,BLBC,BLBS.
The codes for the data lengths are:
0 BYTE
1 WORD
2 LONG
3 QUAD
2.4.6 PSL Bits -
The following PSL bits are shadowed in the I Box:
< 4> T
<27> FPD
<30> TP
These bits are loaded whenever A port address 28 is detected as a
destination.
CVAX CPU CHIP DESIGN SPECIFICATION Page 26
INSTRUCTION (I) BOX
MICROCODE NOTE
IID may not occur during or FOR 2 CYCLES after a
microinstruction in which these bits (T,FPD,TP) are
changed.
2.4.7 Second IID Flag -
This flag is set whenever the I box detects that it is dispatching to
address XFD or IE.IID.STALL . It is cleared during a succesful dispatch.
2.4.8 Index Expected Flag -
This flag is set whenever the I box dispatches to an index mode specifier.
It is cleared at a succesful dispatch.
2.5 I Box Initialization At RESET Signal
The following state bits of the I Box are initialized when RESET is
asserted:
STATE INITIALIZED TO
-----------------------------------------------------+--------------------------
PFQ VALID BITS <2:0> | 0
HARDWARE PREFETCH HALT | 1
DELTA_PC <2:0> | 0
VAX TRAP REQUEST BIT | 0
FD bit | 0
SPECIFIER COUNTER | 0
INDEX EXPECTED | 0
SECOND IID EXPECTED | 0
2.6 I Box Related Microinstructions
In the B field:
Code Operation Comment
-----+-----------------+--------------------------------------------------------
0A B port is ID register (read only when B port is source, not dest)
CVAX CPU CHIP DESIGN SPECIFICATION Page 27
INSTRUCTION (I) BOX
In the MISC field:
Code Operation Comment
-----+-----------------+--------------------------------------------------------
05 RESTART.PREFETCH clear both prefetch disable bits (at phi1)
06 DISABLE.PFQ.PREF set ucode prefetch disable bit ( at phi1)
07 ENABLE.PFQ.PREF clear ucode prefetch disable bit ( at phi1)
08 CLEAR.RN clear RN register (master at phi1, slave at phi3)
09 RN.MINUS.1 decrement RN register (master at phi1, slave at phi3)
0A RN.PLUS.1 increment RN register (master at phi1, slave at phi3)
0B RN.PLUS.DL.Q increment RN if DL=quad (master at phi1, slave at phi3)
0C DL.BYTE DL <-- byte (master at phi1, slave at phi3)
0D DL.WORD DL <-- word (master at phi1, slave at phi3)
0E DL.LONG DL <-- long (master at phi1, slave at phi3)
0F DL.QUAD DL <-- quad (master at phi1, slave at phi1)
17 RN.LOAD.OLD LOAD RN with RN.OLD during PHI3 (slave only)
In the SPECIAL MISC1 field:
MIB<37:33> Operation Comment
----------+-----------------------+--------------------------------------------
1xx1x CLEAR.VAX.TRAP.REQ clear VAX TRAP REQUEST bit
(master at phi1, slave at phi3)
0xx1x SET.VAX.TRAP.REQUEST set VAX TRAP REQUEST bit
(master at phi1, slave at phi3)
In the MEMREQ.REG field:
(NOTE: These registers may be read via the W-spur; only RN may be written via the SPUR)
Code Operation Comment
----+-----------------------+------------------------------------------------------------------
03 OPCODE OPCODE.REG in bits <7:0> (Drive of spur is done by E Box)
04 SPEC.RN SPECIFIER MODE in bits <7:4>, RN in bits <3:0>
In the BR.BCS field (Branch Microinstruction Only)
Code Operation Comment
----+----------------------------------+---------------------------------------------------------
28 DEC.NEXT request for decoder next dispatch
2A DL.BWL.AND.AT.RVM_DEC.NEXT IF DL = B,W, OR L AND AT R, V, OR M DEC.NEXT ELSE GOTO
2B AT.RVM_DEC.NEXT IF AT R, V, OR M DEC.NEXT ELSE GOTO
2C DL.BWL.AND.AT.R_DEC.NEXT IF DL = B,W, OR L AND AT = R DEC.NEXT ELSE GOTO
2D AT.R_DEC.NEXT IF AT = R DEC.NEXT ELSE GOTO
2E AT.AV_DEC.NEXT IF AT = AV THEN DEC.NEXT ELSE GOTO
2F DL.BWL_DEC.NEXT IF DL = B,W, OR L THEN DEC.NEXT ELSE GOTO
3B FPU/DL FPU.PRESENT,DL<1:0> = UTEST<2:0> (drive utest at phi2)
3C I I Box STATUS (FPD.IRQ, RMODE.OLD, RMODE) = UTEST<2:0> (drive utest at phi2)
3D OPCODE2-0 OPCODE<2:0> = UTEST<2:0> (drive utest at phi2) (Drive is done by E Box)
3E LOAD.ID CAUSES LOAD OF ID REGISTER, CASE ON WHETHER OR NOT THERE WAS ENOUGH.
AT<1>,PFQ DRY & HALTED,PFQ DRY (whether halted or not) = UTEST<2:0>
CVAX CPU CHIP DESIGN SPECIFICATION Page 28
INSTRUCTION (I) BOX
2.7 Microcode Restriction Summary
o A recoverable microtrap may not happen in the same cycle as a
CASE.ID.LOAD operation.
o There must be 2 cycles after a change of the PSL before a DECNEXT
operation can be done.
o A load of VIBA and PC must be done after a PC<-BPC operation before any
I Box call.
o The following I Box state bits may be changed by the microcode in the
same cycle as, or immediately before, any I Box dispatch or IDR load
function, but the requested dispatch or load function will be based on the
value of these bits BEFORE the requested change:
FPU Existence bit
Vax Trap Request bit
o A case on PSL bits cannot immediately follow a write to the PSL bits
o Loading of the PC in the same cycle as an I Box dispatch is allowed only
in the case of the conditional branch code to enable a one-cycle
branch-not-taken to be implemented.
o The LOAD.IDR command can only use the DL register. The FORCE.LONG field
is ignored.
o Execution dispatch addresses for opcodes SOBGTR, SOBLEQ, BLBC, BLBS
(addresses SOBX, BLBX) must differ in only one bit position. This is
negotiable if there is STRONG need.
o MXPS0[OPCODE] may be done in the same cycle as DEC.NEXT, but the results
will be unpredictable.
o MISC field operations INCR.RN, DECR.RN, and INCR.RN.IF.DL.Q may not
occur in the same microinstruction as any operation that may cause a
recoverable microtrap.
o Note that SPEC.RN will keep its previous value for 1 microinstruction
after a write.rn is executed.
o Further detail and other restrictions can be found in the following
ECO's:
1. Undefined W-spur bits are not driven and therefore return the
precharged value, 1 (ECO 5JUN01PIR.1).
2. Invert MIB<12> (ECO 5JUL01AO.1).
3. Redefinition of global IID signal (ECO 5AUG01DWA.1).
CVAX CPU CHIP DESIGN SPECIFICATION Page 29
INSTRUCTION (I) BOX
4. The PSL (PSL<dv,fu,iv,cc's) cannot be explicitly written
in the same cycle as DEC.NEXT (RMS 26-Jul-1985 memo).
5. The privileged part of the PSL (PSL<tp,fpd,is,cm,pm>) and psl<t>
cannot be
changed in the same cycle as, or the cycle before,
DEC.NEXT (RMS 26-Jul-1985 memo).
6. The IPL part of the PSL cannot be changed in the same cycle as,
or the cycle before, DEC.NEXT, or the cycle before that
(interrupt) (RMS 26-JUL-1985 memo).
7. MISC.ENABLE.PREFETCH, MISC.DISABLE.PREFETCH, and MISC.RESTART.PREFETCH
must not
happen in the same cycle as or in the cycle before and I Box dispatch
(DEC.NEXT or CASE.ID.LOAD)
2.8 SN Output
The I Box must generate a working register address for use by the E Box.
This value is dependent on the specifier counter, and is updated whenever
an I Box dispatch is done. The following table shows the working register
address as a function of the current specifier number.
Specifier WR Value sent to E Box
Number number as G_S%SN_H<2:0>
----------------------------------------------------
1 0 0
2 2 2
3 4 5
4 7 4
5 3 7
6 1 6
2.9 I Box Testability Hardware
There will be a LFSR attached to the outputs of the IPLA sense amp for
testing the contents of the IPLA ROM. The order of bits in this LFSR will
be the same as the order described above for the IPLA outputs. The
CVAX CPU CHIP DESIGN SPECIFICATION Page 30
INSTRUCTION (I) BOX
feedback taps in the LFSR are located as follows:
PRIMITIVE SEARCH PROGRAM VERSION 1.3 MARCH 9, 1986
DATE = 04-24-86 TIME = 09:14 HRS
No. of Stages in LFSR = 12
No. of XOR Gates used for feedback = 3
Primitive Table:
|==========================================================================|
|| # | POLYNOMIAL * | FEEDBACK TAP POSITIONS ||
|==========================================================================|
|| 1 | 1000001101001 B1 | 12 6 5 3 ||
|| 2 | 1000010011001 B1 | 12 7 4 3 ||
|| 3 | 1110000000101 B1 | 12 11 10 2 ||
|| 4 | 1000110000101 B1 | 12 8 7 2 ||
|| 5 | 1001000001101 B1 | 12 9 3 2 ||
|==========================================================================|
|| 5 primitives found in 40 trials ||
|==========================================================================|
LFSR DESIGN ACCEPTED --
.-.-.-.-.-.-.-.-.-.-.-.-.
<--| | | | | | | | | | | | |<--
`+`-`-`+`-`-`-`-`-`+`+`-`
| | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 31
INSTRUCTION (I) BOX
2.10 I Box Schematics And Their Functions
2.10.1 I_ADDRESS_GENERATOR (IAG) - The address generator creates
addresses on the IMAB (G_S%IMAB_H) based on dispatch information from the
dispatch pla (see I_DISPATCH_PLA) and the IID logic (see I_IID_LOGIC). 10
bits of address are generated, and bit <0> of the IMAB is always 0.
2.10.2 I_AT_DL_REG (IAD) - This schematic contains two 2-bit registers
for storing the access type and data length of the current specifier. It
also includes a multiplexor which chooses one of six possible AT and DL
values from the outputs of the IPLA (see I_IPLA). The multiplexor is
controlled by a value based on the specifier counter and the number of
specifiers the current instruction has.
2.10.3 I_DATAPATH (IDP) - The datapath receives instruction data from the
IDAL bus and stores it in three longword registers. The datapath also
sorts this data and selects the next six bytes of the instruction stream
for processing. Some of this data is loaded into the Instruction Data
Register for use by the E Box. The first two bytes of the instruction
data are decoded by the I Box control hardware to determine the correct I
Box dispatch for the next DEC.NEXT operation.
2.10.4 I_DP_DRIVERS (IDD) - This logic is primarily composed of large
drivers for controlling the datapath. Inputs come mainly from the
prefetch queue controller (see I_PFQ_CONTROL).
2.10.5 I_DISPATCH_PLA (IP1) - The dispatch PLA determines what kind of
dispatch will be done at the next DEC.NEXT operation. It is a self-timed
PLA, needing only one clock to operate. The programming file for the
dispatch PLA is found below in both PLAD and binary format. Note that
some outputs of this PLA are taken directly from product terms, so the
number of true PLA outputs is less than the number indicated in the PLAD
format data.
2.10.5.1 I_DISPATCH_PLA PLAD File -
!
! Description for the address prediction PLA in the I-box
!
CVAX CPU CHIP DESIGN SPECIFICATION Page 32
INSTRUCTION (I) BOX
INPUT
ILLEGAL_OPCODE, ! INDICATES AN ILLEGAL OPCODE CONDITION, I.E. UNDEFINED OPCODES, FP OPS WHEN NO FPA,
! FPD WHEN FPD IS ILLEGAL.
NO_SPECIFIERS, ! INDICATOR FROM IID LOGIC THAT OPCODE HAS NO SPECIFIERS
! NOTE: VALID ONLY IF SPEC_CTR EQ 0
BRANCH_BYTE, ! INDICATOR FROM IID LOGIC THAT OPCODE IS A BRANCH WITH
! BYTE DISPLACEMENT...AGAIN, ONLY VALID IF SPEC_CTR EQ 0
BRANCH_WORD, ! SAME AS ABOVE, FOR BRANCHES W/ WORD DISPLACEMENT
SECOND_IID_EXPECTED, ! FLAG UPDATED ON EVERY DISPATCH, SET IF DISPATCH ADDRESS IS XFD.., CLEARED OTHERWISE
! VALID ONLY IF SPEC_CTR EQ 0
SPEC_CTR_0, ! COUNTER HOLDING NUMBER OF SPECS FOR INSTRUCTION...AT IID, SPEC_CTR GETS SET TO VALUE
! PROVIDED BY IID LOGIC...AT EACH DISPATCH, SPEC_CTR GETS DECREMENTED. WHEN SPEC_CTR
! EQ 2, THE SPECIFIER MODE HAS TO BE CHECKED TO ENABLE OPTIMIZED DISPATCH...WHEN SPEC_CTR
SPEC_CTR_GE_2, ! EQ 1, THE NEXT DISPATCH WILL BE EXECUTE...WHEN SPEC_CTR EQ 0, THE NEXT DISPATCH IS IID
! NOTE: IF AN OPTIMIZED EXE DISPATCH IS TAKEN, SPEC_CTR MUST GET CLEARED.
FPD_DISPATCH, ! SAME AS FPD_BIT
BYTES_REQUIRED<1:0>, ! OUTPUT OF SOME LOGIC THAT LOOKS AT: SPECIFIER MODE, ACCESS TYPE, SPEC_CTR EQ 0, REGISTER EQ PC,
! OUTPUTS NUMBER OF BYTES REQUIRED FOR A SPECIFIER DISPATCH UNDER THOSE CONDITIONS
HAVE0,
HAVEATL1,
HAVEATL2,
HAVEATL3,
HAVEATL4,
HAVEATL5,
HAVEATL6,
I_PSL_TP, ! TRACE PENDING BIT...VALID ONLY WHEN SPEC_CTR EQ 0
INT_PENDING, ! INTERRUPT PENDING BIT...SAME AS ABOVE
VAX_TRAP_REQUEST, ! VAX TRAP REQUEST PENDING BIT...SAME AS ABOVE
INDEX_EXPECTED, ! FLAG SET ON ANY DISPATCH WHICH SENDS THE GSD.INDEX ADDRESS...INDICATES THAT NEXT DECNEXT
! WILL BE A DECNEXT.INDEX
PFQ_HALTED,
SPEC_CTR_1;
OUTPUT
I_S%DISP_ADR_CHOICE<10:0> /DEFAULT=00000000000, ! CHOOSES ADDRESS
IID_THINGS_OK,
I_S%EN_IDR_EFF_DL_H<1:0>,
I_S%EN_NEW_DELTA_PC_H<5:0>,
I_S%EN_ADD_TO_IB_PTR_H /DEFAULT=0, !
I_S%EN_RESET_SPEC_CTR_H /DEFAULT=0,
I_S%EN_DECR_SPEC_CTR_H /DEFAULT=0,
I_S%EN_LOADING_IDR_H /DEFAULT=0;
CONSTANT
BYTES_REQUIRED
(NEED1 = 00,
NEED2 = 01,
NEED3 = 10,
NEED5 = 11);
CONSTANT
I_S%DISP_ADR_CHOICE
(
CVAX CPU CHIP DESIGN SPECIFICATION Page 33
INSTRUCTION (I) BOX
IB_HLT = 00000000001,
VTR_ADR = 10000000000,
INT_ADR = 01000000000,
TBIT_ADR = 00100000000,
XFD_ADR = 00000000000,
FPD_ADR = 00010000000,
ILLEGAL_OPC = 00001000000,
USE_EXE_ADR = 00000100000,
USE_IID_EXE_ADR = 00000010000,
USE_SPEC_ADR = 00000001000,
USE_SPEC_ADR_NDX = 00000000100,
IB_DRY = 00000000010);
CONSTANT
I_S%EN_IDR_EFF_DL_H
(IDR_BYTE = 00,
IDR_WORD = 01,
IDR_LONG = 10);
CONSTANT
I_S%EN_NEW_DELTA_PC_H
(DPC_0 = 000000,
DPC_1 = 001000,
DPC_2 = 001100,
DPC_3 = 001110,
DPC_4 = 001111,
DPC_5 = 100111,
DPC_6 = 110011);
BEGIN
! PROCEED THROUGH VARIOUS VALUES OF SPEC_CTR, GROUPING STATEMENTS FOR EACH VALUE TOGETHER
! FOR SPEC_COUNTER = 0
! THIS MEANS THAT THE IBOX IS READY TO DO AN IID DISPATCH...VALID CASES ARE:
!
! VAX TRAP REQUEST SET
!#0
SPEC_CTR_0,VAX_TRAP_REQUEST,^SECOND_IID_EXPECTED / VTR_ADR;
!#1
SPEC_CTR_0,^VAX_TRAP_REQUEST,INT_PENDING,^SECOND_IID_EXPECTED /INT_ADR;
!#2
! 2/3/86 took ^FPD_DISPATCH out of term # 2 below
SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^HAVE0,^ILLEGAL_OPCODE / IID_THINGS_OK;
!#3
SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,I_PSL_TP,^SECOND_IID_EXPECTED / TBIT_ADR;
!#4
SPEC_CTR_0,HAVE0,SECOND_IID_EXPECTED,PFQ_HALTED / IB_HLT;
!#5
SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^HAVE0,ILLEGAL_OPCODE / ILLEGAL_OPC;
!#6
SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^HAVE0,FPD_DISPATCH,^ILLEGAL_OPCODE / FPD_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_1;
!#7
SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,HAVEATL2,^FPD_DISPATCH,^ILLEGAL_OPCODE,NO_SPECIFIERS,BRANCH_BYTE /
USE_IID_EXE_ADR,IDR_BYTE,I_S%EN_ADD_TO_IB_PTR_H,DPC_2,I_S%EN_LOADING_IDR_H;
!#8
CVAX CPU CHIP DESIGN SPECIFICATION Page 34
INSTRUCTION (I) BOX
SPEC_CTR_0,^HAVEATL2,^FPD_DISPATCH,^ILLEGAL_OPCODE,NO_SPECIFIERS,BRANCH_BYTE,SECOND_IID_EXPECTED,PFQ_HALTED / IB_HLT;
!#9
SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,HAVEATL3,^FPD_DISPATCH,^ILLEGAL_OPCODE,NO_SPECIFIERS,BRANCH_WORD /
USE_IID_EXE_ADR,IDR_WORD,I_S%EN_ADD_TO_IB_PTR_H,DPC_3,I_S%EN_LOADING_IDR_H;
!#10
SPEC_CTR_0,^HAVEATL3,^FPD_DISPATCH,^ILLEGAL_OPCODE,NO_SPECIFIERS,BRANCH_WORD,SECOND_IID_EXPECTED,PFQ_HALTED / IB_HLT;
!#11
SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^HAVE0,^FPD_DISPATCH,^ILLEGAL_OPCODE,NO_SPECIFIERS,^BRANCH_BYTE,^BRANCH_WORD /
USE_IID_EXE_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_1;
!#12
SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^FPD_DISPATCH,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED1,HAVEATL2 / USE_SPEC_ADR,
I_S%EN_ADD_TO_IB_PTR_H,DPC_2,I_S%EN_RESET_SPEC_CTR_H;
!#13
SPEC_CTR_0,^ILLEGAL_OPCODE,^FPD_DISPATCH,^NO_SPECIFIERS,NEED1,^HAVEATL2,SECOND_IID_EXPECTED,PFQ_HALTED / IB_HLT;
!#14
SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^FPD_DISPATCH,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED2,HAVEATL3 / USE_SPEC_ADR,
I_S%EN_ADD_TO_IB_PTR_H,DPC_3,I_S%EN_RESET_SPEC_CTR_H,IDR_BYTE,I_S%EN_LOADING_IDR_H;
!#15
SPEC_CTR_0,^ILLEGAL_OPCODE,^NO_SPECIFIERS,^FPD_DISPATCH,NEED2,^HAVEATL3,SECOND_IID_EXPECTED,PFQ_HALTED /IB_HLT;
!#16
SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^FPD_DISPATCH,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED3,HAVEATL4 / USE_SPEC_ADR,
I_S%EN_ADD_TO_IB_PTR_H,DPC_4,I_S%EN_RESET_SPEC_CTR_H,IDR_WORD,I_S%EN_LOADING_IDR_H;
!#17
SPEC_CTR_0,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED3,^HAVEATL4,^FPD_DISPATCH,SECOND_IID_EXPECTED,PFQ_HALTED / IB_HLT;
!#18
SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^FPD_DISPATCH,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED5,HAVEATL6 / USE_SPEC_ADR,
I_S%EN_RESET_SPEC_CTR_H,I_S%EN_ADD_TO_IB_PTR_H,DPC_6,IDR_LONG,I_S%EN_LOADING_IDR_H;
!#19
SPEC_CTR_0,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED5,^HAVEATL6,^FPD_DISPATCH,SECOND_IID_EXPECTED,PFQ_HALTED /IB_HLT;
!
! FOR SPEC_COUNTER = 1
! IN THIS CASE, THE DISPATCH IS TO EXECUTION FLOWS ONLY...NONE OF THIS SPECIFIER JUNK.
!#20
SPEC_CTR_1 / USE_EXE_ADR,I_S%EN_DECR_SPEC_CTR_H;
!
! FOR SPEC_COUNTER >= 2
! IN THIS CASE,THE DISPATCH WILL BE TO A SPECIFER FLOW IF THERE IS ENOUGH DATA...IF NOT, THE DISPATCH WILL BE TO EITHER:
! IB_HLT, IF THE DISPATCH IS A NORMAL DECNEXT AND THE PFQ IS DRY AND HALTED
! IB_DRY, IF THE DISPATCH IS A NORMAL DECNEXT AND THE PFQ IS DRY BUT NOT HALTED
! REMEMBER TO DECREMENT SPEC COUNTER,LOAD THE SPEC_RN REGISTER,UPDATE AT AND DL, SET IDR_EFF_DL, NEW_DELTA_PC, ENABLE IDR LOAD,
! ENABLE ADDING TO IB_PTR, SET IDR_LOAD_INDEX
!#21
SPEC_CTR_GE_2,^INDEX_EXPECTED,NEED1,HAVEATL1 / USE_SPEC_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_1,I_S%EN_DECR_SPEC_CTR_H;
!#22
SPEC_CTR_GE_2,NEED1,^HAVEATL1,^PFQ_HALTED / IB_DRY;
!#23
SPEC_CTR_GE_2,NEED1,^HAVEATL1,PFQ_HALTED / IB_HLT;
!#24
SPEC_CTR_GE_2,INDEX_EXPECTED,NEED1,HAVEATL1 / USE_SPEC_ADR_NDX,I_S%EN_ADD_TO_IB_PTR_H,DPC_1,I_S%EN_DECR_SPEC_CTR_H;
!#25
SPEC_CTR_GE_2,^INDEX_EXPECTED,NEED2,HAVEATL2 / USE_SPEC_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_2,I_S%EN_DECR_SPEC_CTR_H,
I_S%EN_LOADING_IDR_H,IDR_BYTE;
CVAX CPU CHIP DESIGN SPECIFICATION Page 35
INSTRUCTION (I) BOX
!#26
SPEC_CTR_GE_2,NEED2,^HAVEATL2,^PFQ_HALTED / IB_DRY;
!#27
SPEC_CTR_GE_2,NEED2,^HAVEATL2,PFQ_HALTED / IB_HLT;
!#28
SPEC_CTR_GE_2,INDEX_EXPECTED,NEED2,HAVEATL2 / USE_SPEC_ADR_NDX,I_S%EN_ADD_TO_IB_PTR_H,DPC_2,I_S%EN_LOADING_IDR_H,IDR_BYTE,
I_S%EN_DECR_SPEC_CTR_H;
!#30
SPEC_CTR_GE_2,^INDEX_EXPECTED,NEED3,HAVEATL3 / USE_SPEC_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_3,I_S%EN_DECR_SPEC_CTR_H,
I_S%EN_LOADING_IDR_H,IDR_WORD;
!#31
SPEC_CTR_GE_2,NEED3,^HAVEATL3,^PFQ_HALTED / IB_DRY;
!#32
SPEC_CTR_GE_2,NEED3,^HAVEATL3,PFQ_HALTED / IB_HLT;
!#33
SPEC_CTR_GE_2,INDEX_EXPECTED,NEED3,HAVEATL3 / USE_SPEC_ADR_NDX,I_S%EN_ADD_TO_IB_PTR_H,DPC_3,
I_S%EN_LOADING_IDR_H,IDR_WORD,I_S%EN_DECR_SPEC_CTR_H;
!#34
SPEC_CTR_GE_2,^INDEX_EXPECTED,NEED5,HAVEATL5 / USE_SPEC_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_5,I_S%EN_DECR_SPEC_CTR_H,
I_S%EN_LOADING_IDR_H,IDR_LONG;
!#35
SPEC_CTR_GE_2,NEED5,^HAVEATL5,^PFQ_HALTED / IB_DRY;
!#36
SPEC_CTR_GE_2,NEED5,^HAVEATL5,PFQ_HALTED / IB_HLT;
!#37
SPEC_CTR_GE_2,INDEX_EXPECTED,NEED5,HAVEATL5 / USE_SPEC_ADR_NDX,I_S%EN_ADD_TO_IB_PTR_H,DPC_5,
I_S%EN_LOADING_IDR_H,IDR_LONG,I_S%EN_DECR_SPEC_CTR_H;
END;
2.10.5.2 I_DISPATCH_PLA Binary File... -
i 23
o 18
p 37
x x x x x x 1 x 1 1 x x x x x 1 x x x x 1 x x 0 0 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1
x x x x x x 1 x 1 1 x x x x x 0 x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
x x x x x x 1 x 1 1 x x x x x 0 x x x x x 0 x 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x x x x x x 1 x 1 1 x x x x x 1 x x x x 0 x x 0 1 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1
x x x x x x 1 x 1 0 x x x 1 x x x x x x 1 x x 0 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1
x x x x x x 1 x 1 0 x x x 0 x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
x x x x x x 1 x 1 0 x x x 0 x x x x x x x 0 x 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x x x x x x 1 x 1 0 x x x 1 x x x x x x 0 x x 0 1 0 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1
x x x x x x 1 x 0 1 x x 1 x x x x x x x 1 x x 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1
x x x x x x 1 x 0 1 x x 0 x x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
x x x x x x 1 x 0 1 x x 0 x x x x x x x x 0 x 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x x x x x x 1 x 0 1 x x 1 x x x x x x x 0 x x 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1
x x x x x x 1 x 0 0 x 1 x x x x x x x x 1 x x 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0
x x x x x x 1 x 0 0 x 0 x x x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
CVAX CPU CHIP DESIGN SPECIFICATION Page 36
INSTRUCTION (I) BOX
x x x x x x 1 x 0 0 x 0 x x x x x x x x x 0 x 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x x x x x x 1 x 0 0 x 1 x x x x x x x x 0 x x 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0
x x x x x x x x x x x x x x x x x x x x x x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 -->use_exe output
0 0 x x 1 1 x 0 1 1 x x x x x x 0 x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 x x x 1 x 0 1 1 x x x x x x 1 0 0 0 x x x 0 1 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 1
0 0 x x 1 1 x 0 1 0 x x x x 0 x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 x x x 1 x 0 1 0 x x x x 1 x x 0 0 0 x x x 0 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 1
0 0 x x 1 1 x 0 0 1 x x x 0 x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 x x x 1 x 0 0 1 x x x 1 x x x 0 0 0 x x x 0 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1
0 0 x x 1 1 x 0 0 0 x x 0 x x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 x x x 1 x 0 0 0 x x 1 x x x x 0 0 0 x x x 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0
0 1 0 0 x 1 x 0 x x 0 x x x x x x 0 0 0 x x x 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0
0 1 x 1 1 1 x 0 x x x x x 0 x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 x 1 x 1 x 0 x x x x x 1 x x x 0 0 0 x x x 1 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1
0 1 1 x 1 1 x 0 x x x x 0 x x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 x x 1 x 0 x x x x 1 x x x x 0 0 0 x x x 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1
0 x x x x 1 x 1 x x 0 x x x x x x 0 0 0 x x x 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 --> use_fpd output
1 x x x x 1 x x x x 0 x x x x x x 0 0 0 x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --> use_illeg_opc output
x x x x 1 1 x x x x 1 x x x x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
x x x x 0 1 x x x x x x x x x x x 1 0 0 x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --> use_tbit output
0 x x x x 1 x x x x 0 x x x x x x 0 0 0 x x x 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
x x x x 0 1 x x x x x x x x x x x x 1 0 x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --> use_int output
x x x x 0 1 x x x x x x x x x x x x x 1 x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --> use_vtr output
end
2.10.6 I_FPA_BUFFERS (IFB) - The fpa buffer logic sends opcode class
information to the FPA logic. The FPA present bit also lives here, as
does the logic used to generate the G_S%BRDCST_OK_H signal.
2.10.7 I_IID_LOGIC (IIL) - The IID logic examines the next two bytes of
instruction data. Part of this logic generates an execution address
offset for opcodes with no specifiers. Another part of the logic
generates a specifier dispatch address offset for specifier parsing. The
IID logic examines the opcode to see if it is illegal. Furthermore, it
determines if the opcode is a simple branch or jump, the number of bytes
needed for the next specifier dispatch, and whether or not the opcode is
FD, the first part of a 2-byte opcode.
2.10.8 I_IPLA (IPL) - This logic forms the instruction PLA in the I Box.
It examines the opcode to determine access types, data lengths, number of
specifiers, floating point flags, and partial execution addresses for the
current instruction. The programming of the IPLA is contained in the
following four schematics:
CVAX CPU CHIP DESIGN SPECIFICATION Page 37
INSTRUCTION (I) BOX
o I_IPLA_BANK_0 IB0
o I_IPLA_BANK_1 IB1
o I_IPLA_BANK_2 IB2
o I_IPLA_BANK_3 IB3
2.10.9 I_MIB_DECODE (IMD) - The MIB Decoder decodes part of the
microinstruction, specifically the BCS field and MISC field. In addition,
the logic which controls I Box stalls is contained in this schematic. The
global IID signal is generated here, as is the I Box WRITE clock,
IC%LOADSTATEH.
2.10.10 I_MISC_STATE (IMS) - The misc state logic contains the I Box PSL
bits, the XFD bit, and some additional miscellaneous logic.
2.10.11 I_OP_MUX (IOM) - The operation multiplexor generates control
signals for modifying some I Box state based on the occurence of either
DEC.NEXT or CASE.LD.ID BCS functions. The delta_pc value for ID register
loading is generated here, as are the status bits used on the microtest
bus during a CASE.LD.ID .
2.10.12 I_OTHER_MIB_DECODER (IM2) - This mib decoder decodes the SPECIAL
functions and the MXPS functions for the I Box.
2.10.13 I_PFQ_CONTROL (IQC) - The prefetch queue controller uses
calculated delta_pc values as well as MIB decoder outputs to determine the
correct way to update the prefetch queue registers. It also generates the
global delta_pc value and the state bits which indicate the validity of
longwords in the prefetch queue. Another part of this logic creates a
code which informs the dispatch PLA of the number of bytes available for
the next operation, while yet another part controls the generation of IB
fill requests.
CVAX CPU CHIP DESIGN SPECIFICATION Page 38
INSTRUCTION (I) BOX
2.10.14 I_SECOND_IPLA (I2P) - This PLA augments the IPLA (see I_IPLA) for
determining access types and data lengths for some specifiers. In
particular, this PLA contains the codes for access types and data lengths
for the forth through sixth specifiers of an opcode.
2.10.15 I_SPEC_COUNTER (ISC) - The specifier counter logic keeps track of
the number of specifiers already parsed during instruction decode. The
two primary registers in this schematic contain the current spec counter
and the number of specifiers for the instruction. This schematic also
generates two I Box state bits for use in INDEX specifier decoding. Other
logic on this schematic generates a difference code from the spec counter
and the number of specifiers. This difference code is used to generate an
index for selecting the correct AT and DL code in the I_AT_DL_REG
schematic. The code produced is also used to generate the global SN
register index for the E Box.
2.10.16 I_SPEC_RN_REG (ISR) - The spec.rn register holds the current
specifier. The OLD.RN register is here, as is the RMODE detection logic.
Another part of this schematic holds the second.iid bit.
2.10.17 I_SPUR_UTEST_DRIVE (ISU) - This logic drives the WSPUR and
microtest bus when the spirit moves it.
CVAX CPU CHIP DESIGN SPECIFICATION Page 39
INSTRUCTION (I) BOX
2.11 Tables
2.11.1 Dispatch Types, STALL And UTrap Behavior -
The following table shows, for all I Box requests, the behavior of the
Microaddress Generator:
REQUEST(SPEC.CTR.VAL) PFQ Status DISPATCH
-----------------------+---------------+---------------+
DEC.NEXT (0) OK NORMAL
DRY IE.IID.STALL
DEC.NEXT (<>0) OK NORMAL
DRY, NOT HLT DEC.NEXT.STALL
DRY, HALTED DEC.NEXT.HALTED
LOAD IDR OK CASE ON ID LOAD STATUS
DRY, NOT HLT CASE ON ID LOAD STATUS
DRY, HALTED CASE ON ID LOAD STATUS
2.11.2 NOTE ON UPDATING I BOX STATE - There are two conditions under
which the I Box must freeze most dispatch and state change operations.
These conditions arise as a result of events that interrupt the normal
flow of microcode, namely microtraps and STALLs.
The I Box must retire instruction data used by an I Box dispatch before
the microinstruction containing the dispatch can be stalled or completed.
In the event of a STALL or microtrap, however, the microinstruction may be
retried. In the event of a retry, the I Box must ignore the reissued
microinstruction, since the intended data for the microinstruction has
already been discarded from the instruction stream. The INOP mechanism in
the I Box is used to insure that reissued microinstructions are ignored
correctly.
There are two cases in which a reissued microinstruction must be ignored
by the I Box. The first case occurs when a microtrap is signalled in the
same cycle that a DEC.NEXT microinstruction is executed. In this case,
the I Box must ignore all DEC.NEXT operations until after a DEC.NEXT is
received and STALL is not asserted. In this way, the I Box will resume
operation at the correct point in the microcode flow. The second case
occurs when STALL is asserted. In this case, almost all I Box operations
must be suspended until STALL is deasserted. Both cases are handled by
the INOP logic in the I Box.
The INOP signal inhibits:
o all actions associated with DEC.NEXT or CASE.LD.ID operations
(except drive of case status for the CASE.LD.ID)
CVAX CPU CHIP DESIGN SPECIFICATION Page 40
INSTRUCTION (I) BOX
o all I Box MISC field operations except DISABLE.PFQ
o update of the delta PC value sent to the E Box
o update of: SPEC.RN, OPCODE, VAX.TRAP.REQ, DL, AT, PSL BITS,
IMAB, FD BIT, 2ND IID FLAG, INDEX MODE FLAG, SPEC COUNTER, WSN,
AT_EQ_MOD, IID_LD, COPY_TRACE.
The INOP signal does NOT inhibit:
o MISC operations DISABLE.PFQ,DL.BYTE,DL.WORD,DL.LONG,DL.QUAD, and
LOAD.OLD.RN
o CASE operations (excluding CASE.LD.ID)
o FLUSH of the I Box by LOAD.V&PC
o FLUSH of the I Box by RESET
In summary,
o INOP is set by a microtrap occuring in the same cycle as a
DEC.NEXT . In this case, it is cleared by RESET, LOAD.V&PC, or a
DEC.NEXT while STALL is not asserted.
o INOP is set by assertion of STALL. In this case, it is cleared
by deassertion of STALL, assertion of RESET, or LOAD.V&PC.
CVAX CPU CHIP DESIGN SPECIFICATION Page 41
INSTRUCTION (I) BOX
2.11.3 CVAX IPLA Assignments -
KEY:
OPCODE is listed in the first two to four characters
AN "O" between the opcode and mnemonic indicates an opcode
which is optimized with the help of CFPA
AN "F" between the opcode and mnemonic indicates an opcode
that can only be executed with the CFPA coprocessor
MNEMONIC is next
AT / DL fields for all operands follow the mnemonic
NOTE: Access Types of "w" are treated as "v".
START AUTOMATIC PARSING HERE
1 94 CLRB wb wb CLRX 588
1 D4 CLRL wl wl CLRX 588
1 7C CLRQ wq wq CLRX 588
1 B4 CLRW ww ww CLRX 588
1 97 DECB mb mb DECX 584
1 D7 DECL ml ml DECX 584
1 B7 DECW mw mw DECX 584
1 96 INCB mb mb INCX 580
1 D6 INCL ml ml INCX 580
1 B6 INCW mw mw INCX 580
1 DD PUSHL rl rl PUSHX 444
1 95 TSTB rb rb TSTX 400
1 D5 TSTL rl rl TSTX 400
1 B5 TSTW rw rw TSTX 400
1 9F PUSHAB ab ab PUSHX 444
1 DF PUSHAL al al PUSHX 444
1 7F PUSHAQ aq aq PUSHX 444
1 3F PUSHAW aw aw PUSHX 444
1 E9 BLBC rl rl BLBX 500
1 E8 BLBS rl rl BLBX 500
1 17 JMP ab ab JMP 480
1 16 JSB ab ab JSB 484
1 F4 SOBGEQ ml ml SOBX 504
1 F5 SOBGTR ml ml SOBX 504
1 B9 BICPSW rw rw BISPSW 520
1 B8 BISPSW rw rw BISPSW 520
1 DC MOVPSL wl wl MOVPSL 58C
1 BA POPR rw rw POPR 4A0
1 BB PUSHR rw rw PUSHR 4A4
1 BD CHME rw rw CHME 4BC
1 BC CHMK rw rw CHMK 4B8
1 BE CHMS rw rw CHMS 4C0
1 BF CHMU rw rw CHMU 4C4
1 73 F TSTD rd rd TSTDG 518
1 53 F TSTF rf rf TSTF 528
1 53FD F TSTG rg rg TSTDG 518
2 58 ADAWI rw aw ADAWI 448
;2 ADAWI.RMODE 44A
2 80 ADDB2 rb mb ADDX2 40C
;2 ADDX2.RMODE 40E
2 C0 ADDL2 rl ml ADDX2 40C
CVAX CPU CHIP DESIGN SPECIFICATION Page 42
INSTRUCTION (I) BOX
;2 ADDX2.RMODE 40E
2 A0 ADDW2 rw mw ADDX2 40C
;2 ADDX2.RMODE 40E
2 D8 ADWC rl ml ADWC 420
;2 ADWC.RMODE 422
2 8A BICB2 rb mb BICX2 418
;2 BICX2.RMODE 41A
2 CA BICL2 rl ml BICX2 418
;2 BICX2.RMODE 41A
2 AA BICW2 rw mw BICX2 418
;2 BICX2.RMODE 41A
2 88 BISB2 rb mb BISX2 414
;2 BISX2.RMODE 416
2 C8 BISL2 rl ml BISX2 414
;2 BISX2.RMODE 416
2 A8 BISW2 rw mw BISX2 414
;2 BISX2.RMODE 416
2 93 BITB rb rb BITX 408
;2 BITX.RMODE 40A
2 D3 BITL rl rl BITX 408
;2 BITX.RMODE 40A
2 B3 BITW rw rw BITX 408
;2 BITX.RMODE 40A
2 91 CMPB rb rb CMPX 404
;2 CMPX.RMODE 406
2 D1 CMPL rl rl CMPX 404
;2 CMPX.RMODE 406
2 B1 CMPW rw rw CMPX 404
;2 CMPX.RMODE 406
2 98 CVTBL rb wl CVTBX 44C
;2 CVTBX.RMODE 44E
2 99 CVTBW rb ww CVTBX 44C
;2 CVTBX.RMODE 44E
2 F6 CVTLB rl wb CVTXY 598
;2 CVTXY.RMODE 59A
2 F7 CVTLW rl ww CVTXY 598
;2 CVTXY.RMODE 59A
2 33 CVTWB rw wb CVTXY 598
;2 CVTXY.RMODE 59A
2 32 CVTWL rw wl CVTWL 450
;2 CVTWL.RMODE 452
2 86 DIVB2 rb mb DIVX2 468
;2 DIVX2.RMODE 46A
2 C6 O DIVL2 rl ml DIVX2 468
;2 DIVX2.RMODE 46A
2 A6 DIVW2 rw mw DIVX2 468
;2 DIVX2.RMODE 46A
2 92 MCOMB rb wb MCOMX 428
;2 MCOMX.RMODE 42A
2 D2 MCOML rl wl MCOMX 428
;2 MCOMX.RMODE 42A
2 B2 MCOMW rw ww MCOMX 428
;2 MCOMX.RMODE 42A
2 8E MNEGB rb wb MNEGX 42C
CVAX CPU CHIP DESIGN SPECIFICATION Page 43
INSTRUCTION (I) BOX
;2 MNEGX.RMODE 42E
2 CE MNEGL rl wl MNEGX 42C
;2 MNEGX.RMODE 42E
2 AE MNEGW rw ww MNEGX 42C
;2 MNEGX.RMODE 42E
2 90 MOVB rb wb MOVX 59C
;2 MOVX.RMODE 59E
2 D0 MOVL rl wl MOVX 59C
;2 MOVX.RMODE 59E
2 7D MOVQ rq wq MOVX 59C
;2 MOVX.RMODE 59E
2 B0 MOVW rw ww MOVX 59C
;2 MOVX.RMODE 59E
2 9B MOVZBW rb ww MOVX 59C
;2 MOVX.RMODE 59E
2 9A MOVZBL rb wl MOVX 59C
;2 MOVX.RMODE 59E
2 3C MOVZWL rw wl MOVX 59C
;2 MOVX.RMODE 59E
2 84 MULB2 rb mb MULX2 510
;2 MULX2.RMODE 512
2 C4 O MULL2 rl ml MULX2 510
;2 MULX2.RMODE 512
2 A4 MULW2 rw mw MULX2 510
;2 MULX2.RMODE 512
2 D9 SBWC rl ml SBWC 424
;2 SBWC.RMODE 426
2 82 SUBB2 rb mb SUBX2 410
;2 SUBX2.RMODE 412
2 C2 SUBL2 rl ml SUBX2 410
;2 SUBX2.RMODE 412
2 A2 SUBW2 rw mw SUBX2 410
;2 SUBX2.RMODE 412
2 8C XORB2 rb mb XORX2 41C
;2 XORX2.RMODE 41E
2 CC XORL2 rl ml XORX2 41C
;2 XORX2.RMODE 41E
2 AC XORW2 rw mw XORX2 41C
;2 XORX2.RMODE 41E
2 9E MOVAB ab wl MOVX 59C
;2 MOVX.RMODE 59E
2 DE MOVAL al wl MOVX 59C
;2 MOVX.RMODE 59E
2 7E MOVAQ aq wl MOVX 59C
;2 MOVX.RMODE 59E
2 3E MOVAW aw wl MOVX 59C
;2 MOVX.RMODE 59E
2 F3 AOBLEQ rl ml AOBX 488
;2 AOBX.RMODE 48A
2 F2 AOBLSS rl ml AOBX 488
;2 AOBX.RMODE 48A
2 E1 BBC rl vb BBX 490
;2 BBX.RMODE 492
2 E0 BBS rl vb BBX 490
CVAX CPU CHIP DESIGN SPECIFICATION Page 44
INSTRUCTION (I) BOX
;2 BBX.RMODE 492
2 E5 BBCC rl vb BBX 490
;2 BBX.RMODE 492
2 E3 BBCS rl vb BBX 490
;2 BBX.RMODE 492
2 E4 BBSC rl vb BBX 490
;2 BBX.RMODE 492
2 E2 BBSS rl vb BBX 490
;2 BBX.RMODE 492
2 E7 BBCCI rl vb BBX 490
;2 BBX.RMODE 492
2 E6 BBSSI rl vb BBX 490
;2 BBX.RMODE 492
2 FA CALLG ab ab CALLX 498
;2 CALLX.RMODE 49A
2 FB CALLS rl ab CALLX 498
;2 CALLX.RMODE 49A
2 5C INSQHI ab aq INSQXI 4CC
;2 INSQXI.RMODE 4CE
2 5D INSQTI ab aq INSQXI 4CC
;2 INSQXI.RMODE 4CE
2 0E INSQUE ab ab INSQUE 4A8
;2 INSQUE.RMODE 4AA
2 5E REMQHI aq wl REMQXI 4F8
;2 REMQXI.RMODE 4FA
2 5F REMQTI aq wl REMQXI 4F8
;2 REMQXI.RMODE 4FA
2 0F REMQUE ab wl REMQUE 4AC
;2 REMQUE.RMODE 4AE
2 DB MFPR rl wl MFPR 4B4
;2 MFPR.RMODE 4B6
2 DA MTPR rl rl MTPR 4B0
;2 MTPR.RMODE 4B2
2 60 F ADDD2 rd md ADDDG2 4D4
;2 ADDDG2.RMODE 4D6
2 40 F ADDF2 rf mf ADDF2 4D0
;2 ADDF2.RMODE 4D2
2 40FD F ADDG2 rg mg ADDDG2 4D4
;2 ADDDG2.RMODE 4D6
2 71 F CMPD rd rd CMPDG 4DC
;2 CMPDG.RMODE 4DE
2 51 F CMPF rf rf CMPF 4D8
;2 CMPF.RMODE 4DA
2 51FD F CMPG rg rg CMPDG 4DC
;2 CMPDG.RMODE 4DE
2 6C F CVTBD rb wd ADDDG3 464
;2 ADDDG3.RMODE 466
2 4C F CVTBF rb wf ADDF3 460
;2 ADDF3.RMODE 462
2 4CFD F CVTBG rb wg ADDDG3 464
;2 ADDDG3.RMODE 466
2 68 F CVTDB rd wb ADDF3 460
;2 ADDF3.RMODE 462
2 76 F CVTDF rd wf ADDF3 460
CVAX CPU CHIP DESIGN SPECIFICATION Page 45
INSTRUCTION (I) BOX
;2 ADDF3.RMODE 462
2 6A F CVTDL rd wl ADDF3 460
;2 ADDF3.RMODE 462
2 69 F CVTDW rd ww ADDF3 460
;2 ADDF3.RMODE 462
2 48 F CVTFB rf wb ADDF3 460
;2 ADDF3.RMODE 462
2 56 F CVTFD rf wd ADDDG3 464
;2 ADDDG3.RMODE 466
2 99FD F CVTFG rf wg ADDDG3 464
;2 ADDDG3.RMODE 466
2 4A F CVTFL rf wl ADDF3 460
;2 ADDF3.RMODE 462
2 49 F CVTFW rf ww ADDF3 460
;2 ADDF3.RMODE 462
2 48FD F CVTGB rg wb ADDF3 460
;2 ADDF3.RMODE 462
2 33FD F CVTGF rg wf ADDF3 460
;2 ADDF3.RMODE 462
2 4AFD F CVTGL rg wl ADDF3 460
;2 ADDF3.RMODE 462
2 49FD F CVTGW rg ww ADDF3 460
;2 ADDF3.RMODE 462
2 6E F CVTLD rl wd ADDDG3 464
;2 ADDDG3.RMODE 466
2 4E F CVTLF rl wf ADDF3 460
;2 ADDF3.RMODE 462
2 4EFD F CVTLG rl wg ADDDG3 464
;2 ADDDG3.RMODE 466
2 6D F CVTWD rw wd ADDDG3 464
;2 ADDDG3.RMODE 466
2 4D F CVTWF rw wf ADDF3 460
;2 ADDF3.RMODE 462
2 4DFD F CVTWG rw wg ADDDG3 464
;2 ADDDG3.RMODE 466
2 6B F CVTRDL rd wl ADDF3 460
;2 ADDF3.RMODE 462
2 4B F CVTRFL rf wl ADDF3 460
;2 ADDF3.RMODE 462
2 4BFD F CVTRGL rg wl ADDF3 460
;2 ADDF3.RMODE 462
2 66 F DIVD2 rd md ADDDG2 4D4
;2 ADDDG2.RMODE 4D6
2 46 F DIVF2 rf mf ADDF2 4D0
;2 ADDF2.RMODE 4D2
2 46FD F DIVG2 rg mg ADDDG2 4D4
;2 ADDDG2.RMODE 4D6
2 72 F MNEGD rd wd ADDDG3 464
;2 ADDDG3.RMODE 466
2 52 F MNEGF rf wf ADDF3 460
;2 ADDF3.RMODE 462
2 52FD F MNEGG rg wg ADDDG3 464
;2 ADDDG3.RMODE 466
2 70 F MOVD rd wd MOVDG 594
CVAX CPU CHIP DESIGN SPECIFICATION Page 46
INSTRUCTION (I) BOX
;2 MOVDG.RMODE 596
2 50 F MOVF rf wf MOVF 590
;2 MOVF.RMODE 592
2 50FD F MOVG rg wg MOVDG 594
;2 MOVDG.RMODE 596
2 64 F MULD2 rd md ADDDG2 4D4
;2 ADDDG2.RMODE 4D6
2 44 F MULF2 rf mf ADDF2 4D0
;2 ADDF2.RMODE 4D2
2 44FD F MULG2 rg mg ADDDG2 4D4
;2 ADDDG2.RMODE 4D6
2 62 F SUBD2 rd md ADDDG2 4D4
;2 ADDDG2.RMODE 4D6
2 42 F SUBF2 rf mf ADDF2 4D0
;2 ADDF2.RMODE 4D2
2 42FD F SUBG2 rg mg ADDDG2 4D4
;2 ADDDG2.RMODE 4D6
3 81 ADDB3 rb rb wb ADDX3 430
;3 ADDX3.RMODE 432
3 C1 ADDL3 rl rl wl ADDX3 430
;3 ADDX3.RMODE 432
3 A1 ADDW3 rw rw ww ADDX3 430
;3 ADDX3.RMODE 432
3 78 ASHL rb rl wl ASHX 45C
;3 ASHX.RMODE 45E
3 79 ASHQ rb rq wq ASHX 45C
;3 ASHX.RMODE 45E
3 8B BICB3 rb rb wb BICX3 43C
;3 BICX3.RMODE 43E
3 CB BICL3 rl rl wl BICX3 43C
;3 BICX3.RMODE 43E
3 AB BICW3 rw rw ww BICX3 43C
;3 BICX3.RMODE 43E
3 89 BISB3 rb rb wb BISX3 438
;3 BISX3.RMODE 43A
3 C9 BISL3 rl rl wl BISX3 438
;3 BISX3.RMODE 43A
3 A9 BISW3 rw rw ww BISX3 438
;3 BISX3.RMODE 43A
3 87 DIVB3 rb rb wb DIVX3 46C
;3 DIVX3.RMODE 46E
3 C7 O DIVL3 rl rl wl DIVX3 46C
;3 DIVX3.RMODE 46E
3 A7 DIVW3 rw rw ww DIVX3 46C
;3 DIVX3.RMODE 46E
3 85 MULB3 rb rb wb MULX3 514
;3 MULX3.RMODE 516
3 C5 O MULL3 rl rl wl MULX3 514
;3 MULX3.RMODE 516
3 A5 MULW3 rw rw ww MULX3 514
;3 MULX3.RMODE 516
3 9C ROTL rb rl wl ROTL 458
;3 ROTL.RMODE 45A
3 83 SUBB3 rb rb wb SUBX3 434
CVAX CPU CHIP DESIGN SPECIFICATION Page 47
INSTRUCTION (I) BOX
;3 SUBX3.RMODE 436
3 C3 SUBL3 rl rl wl SUBX3 434
;3 SUBX3.RMODE 436
3 A3 SUBW3 rw rw ww SUBX3 434
;3 SUBX3.RMODE 436
3 8D XORB3 rb rb wb XORX3 440
;3 XORX3.RMODE 442
3 CD XORL3 rl rl wl XORX3 440
;3 XORX3.RMODE 442
3 AD XORW3 rw rw ww XORX3 440
;3 XORX3.RMODE 442
3 9D ACBB rb rb mb ACBX 48C
;3 ACBX.RMODE 48E
3 F1 ACBL rl rl ml ACBX 48C
;3 ACBX.RMODE 48E
3 3D ACBW rw rw mw ACBX 48C
;3 ACBX.RMODE 48E
3 8F CASEB rb rb rb CASEX 494
;3 CASEX.RMODE 496
3 CF CASEL rl rl rl CASEX 494
;3 CASEX.RMODE 496
3 AF CASEW rw rw rw CASEX 494
;3 CASEX.RMODE 496
3 28 MOVC3 rw ab ab MOVCX 524
;3 MOVCX.RMODE 526
3 0C PROBER rb rw ab PROBEX 4C8
;3 PROBEX.RMODE 4CA
3 0D PROBEW rb rw ab PROBEX 4C8
;3 PROBEX.RMODE 4CA
3 6F F ACBD rd rd md ACBDG 4E4
;3 ACBDG.RMODE 4E6
3 4F F ACBF rf rf mf ACBF 4E0
;3 ACBF.RMODE 4E2
3 4FFD F ACBG rg rg mg ACBDG 4E4
;3 ACBDG.RMODE 4E6
3 61 F ADDD3 rd rd wd ADDDG3 464
;3 ADDDG3.RMODE 466
3 41 F ADDF3 rf rf wf ADDF3 460
;3 ADDF3.RMODE 462
3 41FD F ADDG3 rg rg wg ADDDG3 464
;3 ADDDG3.RMODE 466
3 67 F DIVD3 rd rd wd ADDDG3 464
;3 ADDDG3.RMODE 466
3 47 F DIVF3 rf rf wf ADDF3 460
;3 ADDF3.RMODE 462
3 47FD F DIVG3 rg rg wg ADDDG3 464
;3 ADDDG3.RMODE 466
3 65 F MULD3 rd rd wd ADDDG3 464
;3 ADDDG3.RMODE 466
3 45 F MULF3 rf rf wf ADDF3 460
;3 ADDF3.RMODE 462
3 45FD F MULG3 rg rg wg ADDDG3 464
;3 ADDDG3.RMODE 466
3 75 F POLYD rd rw ab POLYDG 4EC
CVAX CPU CHIP DESIGN SPECIFICATION Page 48
INSTRUCTION (I) BOX
;3 POLYDG.RMODE 4EE
3 55 F POLYF rf rw ab POLYF 4E8
;3 POLYF.RMODE 4EA
3 55FD F POLYG rg rw ab POLYDG 4EC
;3 POLYDG.RMODE 4EE
3 63 F SUBD3 rd rd wd ADDDG3 464
;3 ADDDG3.RMODE 466
3 43 F SUBF3 rf rf wf ADDF3 460
;3 ADDF3.RMODE 462
3 43FD F SUBG3 rg rg wg ADDDG3 464
;3 ADDDG3.RMODE 466
3 29 CMPC3 rw ab ab CMPCX 4F0
;3 CMPCX.RMODE 4F2
3 35 CMPP3 rw ab ab EMULATE.A 474
;3 EMULATE.A.RMODE 476
3 F9 CVTLP rl rw ab EMULATE.A 474
;3 EMULATE.A.RMODE 476
3 36 CVTPL rw ab wl EMULATE.3W 478
;3 EMULATE.3W.RMODE 47A
3 3A LOCC rb rw ab LOCC.SKPC 454
;3 LOCC.SKPC.RMODE 456
3 34 MOVP rw ab ab EMULATE.A 474
;3 EMULATE.A.RMODE 476
3 3B SKPC rb rw ab LOCC.SKPC 454
;3 LOCC.SKPC.RMODE 456
4 7B EDIV rl rq wl wl EDIV 51C
;4 EDIV.RMODE 51E
4 7A O EMUL rl rl rl wq MULX3 514
;4 MULX3.RMODE 516
4 EC CMPV rl rb vb rl FIELDX 508
;4 FIELDX.RMODE 50A
4 ED CMPZV rl rb vb rl FIELDX 508
;4 FIELDX.RMODE 50A
4 EE EXTV rl rb vb wl FIELDX 508
;4 FIELDX.RMODE 50A
4 EF EXTZV rl rb vb wl FIELDX 508
;4 FIELDX.RMODE 50A
4 F0 INSV rl rl rb vb INSV 470
;4 INSV.RMODE 472
4 EB FFC rl rb vb wl FIELDX 508
;4 FIELDX.RMODE 50A
4 EA FFS rl rb vb wl FIELDX 508
;4 FIELDX.RMODE 50A
4 20 ADDP4 rw ab rw ab EMULATE.A 474
;4 EMULATE.A.RMODE 476
4 37 CMPP4 rw ab rw ab EMULATE.A 474
;4 EMULATE.A.RMODE 476
4 0B CRC ab rl rw ab EMULATE.A 474
;4 EMULATE.A.RMODE 476
4 08 CVTPS rw ab rw ab EMULATE.A 474
;4 EMULATE.A.RMODE 476
4 09 CVTSP rw ab rw ab EMULATE.A 474
;4 EMULATE.A.RMODE 476
4 38 EDITPC rw ab ab ab EMULATE.A 474
CVAX CPU CHIP DESIGN SPECIFICATION Page 49
INSTRUCTION (I) BOX
;4 EMULATE.A.RMODE 476
4 39 MATCHC rw ab rw ab EMULATE.A 474
;4 EMULATE.A.RMODE 476
4 2A SCANC rw ab ab rb SCANC.SPANC 47C
;4 SCANC.SPANC.RMODE 47E
4 2B SPANC rw ab ab rb SCANC.SPANC 47C
;4 SCANC.SPANC.RMODE 47E
4 22 SUBP4 rw ab rw ab EMULATE.A 474
;4 EMULATE.A.RMODE 476
5 2D CMPC5 rw ab rb rw ab CMPCX 4F0
;5 CMPCX.RMODE 4F2
5 24 CVTPT rw ab ab rw ab EMULATE.A 474
;5 EMULATE.A.RMODE 476
5 26 CVTTP rw ab ab rw ab EMULATE.A 474
;5 EMULATE.A.RMODE 476
5 74 F EMODD rd rb rd wl wd EMODF 4F4
;5 EMODF.RMODE 4F6
5 54 F EMODF rf rb rf wl wf EMODF 4F4
;5 EMODF.RMODE 4F6
5 54FD F EMODG rg rw rg wl wg EMODF 4F4
;5 EMODF.RMODE 4F6
5 2C MOVC5 rw ab rb rw ab MOVCX 524
;5 MOVCX.RMODE 526
6 0A INDEX rl rl rl rl rl wl INDEX 49C
;6 INDEX.RMODE 49E
6 21 ADDP6 rw ab rw ab rw ab EMULATE.A 474
;6 EMULATE.A.RMODE 476
6 F8 ASHP rb rw ab rb rw ab EMULATE.A 474
;6 EMULATE.A.RMODE 476
6 27 DIVP rw ab rw ab rw ab EMULATE.A 474
;6 EMULATE.A.RMODE 476
6 2E MOVTC rw ab rb ab rw ab EMULATE.A 474
;6 EMULATE.A.RMODE 476
6 2F MOVTUC rw ab rb ab rw ab EMULATE.A 474
;6 EMULATE.A.RMODE 476
6 25 MULP rw ab rw ab rw ab EMULATE.A 474
;6 EMULATE.A.RMODE 476
6 23 SUBP6 rw ab rw ab rw ab EMULATE.A 474
;6 EMULATE.A.RMODE 476
STOP AUTOMATIC PARSING HERE
CVAX CPU CHIP DESIGN SPECIFICATION Page 50
INSTRUCTION (I) BOX
2.11.4 Other Opcodes -
The following opcodes have no entry in the IPLA. They are 0-operand
instructions, illegal opcodes, and simple branch instructions. ALL of
these instructions dispatch directly to execution flows at IID time if
there are no exceptions pending:
OPCODE MNEMONIC DISPATCH ADDRESS
--------------------------------------------------------------------
03 BPT BPT 186
1B BLEQU BRCOND 19E
04 RET RET 188
11 BRB BRX 192
19 BLSS BRCOND 19E
05 RSB RSB 18A
31 BRW BRX 192
12 BNEQ BRCOND 19E
07 SVPCTX SVPCTX 18E
1F BCS BRCOND 19E
10 BSBB BSBX 190
FC FC XFC 198
1E BCC BRCOND 19E
30 BSBW BSBX 190
FD FD XFD 19A
13 BEQL BRCOND 19E
1C BVC BRCOND 19E
FE FE RSRV.INST.FLT 282
18 BGEQ BRCOND 19E
1D BVS BRCOND 19E
FF FF RSRV.INST.FLT 282
1E BGEQU BRCOND 19E
00 HALT HALT 180
57 57 RSRV.INST.FLT 282
14 BGTR BRCOND 19E
01 NOP NOP 182
59 59 RSRV.INST.FLT 282
1A BGTRU BRCOND 19E
06 LDPCTX LDPCTX 18C
77 77 RSRV.INST.FLT 282
15 BLEQ BRCOND 19E
02 REI REI 18E
5A 5A RSRV.INST.FLT 282
5B 5B RSRV.INST.FLT 282
CVAX CPU CHIP DESIGN SPECIFICATION Page 51
INSTRUCTION (I) BOX
2.11.5 Internal/External Signal Timing -
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_S%LATE_PHI4_L |_____/~~~~~~~~~~~~~~~~~~~~~~~~~~\______| PRECHARGE CLOCK FOR DATAPATH; TO: IDP |
| | | | | | Node Cap: 14.57PF |
| SPICE REF: i_datapath_sim idp_path1_ss_1 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |PHI4+7 - phi1+5| IDP |phi4+7 - phi1+5 | none | yes | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_2_GETS_IDAL_H |/~~~~~~~\______________________________| LOADS PFQ[2] WITH IDAL; TO: IDP |
| | | | | | Node Cap: 3.79PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+4 -phi1+17| IDP |PHI1+4 - PHI1+17| none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_2_GETS_IDAL_L |\________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| AS ABOVE |
| | | | | | Node Cap: 4.16PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+5 -phi2+1 | IDP |PHI1+5 - PHI2+1 | none | yes | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_1_GETS_IDAL_H |/~~~~~~~\______________________________| LOADS PFQ[1] WITH IDAL; TO: IDP |
| | | | | | Node Cap: 3.83PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+4 -phi1+17| IDP |PHI1+4 - PHI1+17| none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_1_GETS_IDAL_L |\________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| AS ABOVE |
| | | | | | Node Cap: 4.28PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+5 -phi2+1 | IDP |PHI1+5 - PHI2+1 | none | yes | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_0_GETS_IDAL_H |/~~~~~~~\______________________________| LOADS PFQ[0] WITH IDAL; TO: IDP |
| | | | | | Node Cap: 3.83PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+4 -phi1+17| IDP |PHI1+4 - PHI1+17| none | no | yes |
CVAX CPU CHIP DESIGN SPECIFICATION Page 52
INSTRUCTION (I) BOX
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 53
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_0_GETS_IDAL_L |\________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| AS ABOVE |
| | | | | | Node Cap: 4.23PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+5 -phi2+1 | IDP |PHI1+5 - PHI2+1 | none | yes | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_1_GETS_Q2_H |/~~~~~~~\______________________________| LOADS PFQ[1] WITH PFQ[2]; TO: IDP |
| | | | | | Node Cap: 3.80PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+4 -phi1+17| IDP |PHI1+4 - PHI1+17| none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_1_GETS_Q2_L |\________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| AS ABOVE |
| | | | | | Node Cap: 4.26PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+5 -phi2+1 | IDP |PHI1+5 - PHI2+1 | none | yes | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_0_GETS_Q2_H |/~~~~~~~\______________________________| LOADS PFQ[0] WITH PFQ[2]; TO: IDP |
| | | | | | Node Cap: 3.82PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+4 -phi1+17| IDP |PHI1+4 - PHI1+17| none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_0_GETS_Q2_L |\________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| AS ABOVE |
| | | | | | Node Cap: 4.20PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+5 -phi2+1 | IDP |PHI1+5 - PHI2+1 | none | yes | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_0_GETS_Q1_H |/~~~~~~~\______________________________| LOADS PFQ[0] WITH PFQ[1]; TO: IDP |
| | | | | | Node Cap: 3.90PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+4 -phi1+17| IDP |PHI1+4 - PHI1+17| none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 54
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_C%PFQ_0_GETS_Q1_L |\________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| AS ABOVE |
| | | | | | Node Cap: 4.36PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+5 -phi2+1 | IDP |PHI1+5 - PHI2+1 | none | yes | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_CL%IB_PTR_EQ_0_H |_______/~~~~~~~~~~~~~~~~~~~~~~\________| QMUX ORIGIN = PFQ BYTE 0; TO: IDP |
| | | | | | Node Cap: 14.66PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD | phi1+15 - phi4| IDP | PHI1+15 - PHI4 | none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_CL%IB_PTR_EQ_1_H |_______/~~~~~~~~~~~~~~~~~~~~~~\________| QMUX ORIGIN = PFQ BYTE 1; TO: IDP |
| | | | | | Node Cap: 14.61PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD | phi1+15 - phi4| IDP | PHI1+15 - PHI4 | none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_CL%IB_PTR_EQ_2_H |_______/~~~~~~~~~~~~~~~~~~~~~~\________| QMUX ORIGIN = PFQ BYTE 2; TO: IDP |
| | | | | | Node Cap: 14.65PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD | phi1+15 - phi4| IDP | PHI1+15 - PHI4 | none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_CL%IB_PTR_EQ_3_H |_______/~~~~~~~~~~~~~~~~~~~~~~\________| QMUX ORIGIN = PFQ BYTE 3; TO: IDP |
| | | | | | Node Cap: 14.94PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD | phi1+15 - phi4| IDP | PHI1+15 - PHI4 | none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_SL%IDR_POS_EQ_2_H |___________________________/~~~~~~~~~\_| ID DATA ORIGIN = QMUX[2]; TO: IDP |
| | | | | | Node Cap: 2.31PF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi3+15-phi4+20| IDP |phi3+15-phi4+20 | none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 55
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_SL%IDR_POS_EQ_1_H |___________________________/~~~~~~~~~\_| ID DATA ORIGIN = QMUX[1]; TO: IDP |
| | | | | | Node Cap: 1.98PF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi3+15-phi4+20| IDP |phi3+15-phi4+20 | none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_SL%IDR_POS_EQ_0_H |___________________________/~~~~~~~~~\_| ID DATA ORIGIN = QMUX[0]; TO: IDP |
| | | | | | Node Cap: 1.94PF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi3+15-phi4+20| IDP |phi3+15-phi4+20 | none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_SL%IDR_POS_EQ_2_L |~~~~~~~~~~~~~~~~~~~~~~~~~~\__________/~| ID DATA ORIGIN = QMUX[2]; TO: IDP |
| | | | | | Node Cap: 2.55PF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi3+15-phi4+20| IDP |phi3+15-phi4+20 | none | yes | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_SL%IDR_POS_EQ_1_L |~~~~~~~~~~~~~~~~~~~~~~~~~~\__________/~| ID DATA ORIGIN = QMUX[1]; TO: IDP |
| | | | | | Node Cap: 2.35PF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi3+15-phi4+20| IDP |phi3+15-phi4+20 | none | yes | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_SL%IDR_POS_EQ_0_L |~~~~~~~~~~~~~~~~~~~~~~~~~~\__________/~| ID DATA ORIGIN = QMUX[0]; TO: IDP |
| | | | | | Node Cap: 2.42PF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi3+15-phi4+20| IDP |phi3+15-phi4+20 | none | yes | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_CL%READ_IDR_H |//~~~~~~~~~~~\_________________________| B.BUS <-- IDR; TO: IDP |
| | | | | | Node Cap: 7.53PF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi1+6 - phi2+6| IDP |phi1+6 - phi2+6 | none | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 56
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_CL%BYTE_SXT_H |~~~\___________________________/~~~~~~~| SIGN EXTEND IDR, DL = BYTE; TO: IDP |
| | | | | | Node Cap: 2.25PF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi4+10 -phi1+8| IDP |PHI4+ - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_CL%BYTE_SXT_L |___/~~~~~~~~~~~~~~~~~~~~~~~~~~~\_______| SIGN EXTEND IDR, BL = BYTE; TO: IDP |
| | | | | | Node Cap: 2.85PF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi4+10 -phi1+8| IDP |PHI4+ - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_CL%WORD_SXT_H |~~~\___________________________/~~~~~~~| SIGN EXTEND IDR, DL = WORD; TO: IDP |
| | | | | | Node Cap: 2.15PF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi4+10 -phi1+8| IDP |PHI4+ - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_CL%WORD_SXT_L |___/~~~~~~~~~~~~~~~~~~~~~~~~~~~\_______| SIGN EXTEND IDR, BL = WORD; TO: IDP |
| | | | | | Node Cap: 2.79PF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi4+10 -phi1+8| IDP |PHI4+ - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 57
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_S%BUFF_LOW_BYTE_H<7:0> |~~~~~~~~~~~\=================/~~~~~~~~~| LOW BYTE BUFFERED TO I2P |
| INTERCONNECT MAX : 2500um| | | | | Node Cap: 1.30PF |
| SPICE REF: none Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |phi2+10 - phi4 | I2P | PHI2+10 - PHI3 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDP | | | | | |@
| I_SL%PFQ_LOW_BYTE_H<7:0> |~~~~~~~\=====================/~~~~~~~~~| LOW BYTE FROM I-STREAM; |
| INTERCONNECT MAX : 150um | | | | | Node Cap: 4.36PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDP | phi1+17 = phi4| ISR | PHI2 - PHI4 | | | |
| IDP | | IIL | PHI1+17 - PHI4 | | | |
| IDP | | IDD | PHI1+17 - PHI4 | | | |
| IDP | | IPL | PHI1+17 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDP | | | | | |@
| I_SL%PFQ_2ND_BYTE_H<7:0> |~~~~~~\======================/~~~~~~~~~| 2ND BYTE FROM I-STREAM; TO: ISR,IIL |
| MAX INTERCONNECT: 1800um | | | | | Node Cap: 3.15PF |
| SPICE REF: i_datapath_sim idp_path1_ss_4 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDP | phi1+17 = phi4| ISR | PHI2 - PHI4 | | | |
| IDP | | IIL | PHI1+18 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDP | | | | | |@
| G_PH%B_BUS_H<31:0> | SEE GLOBAL SIGNAL TIMING SHEETS | B-BUS; TO: EBOX |
| | | | | | LOAD = 3pF |
| SPICE REF: i_datapath_sim idp_path2_ss_2 Last updated: 4/18/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDP | phi1+18 | EBOX | PHI1+18 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 58
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IPL | | | | | |@
| I_S%NEW_FPO_INSTR_H |XXXXXXXX=======================XXXXXXXX| FP OPTIMIZE FLAG; TO: IFB |
| MAX INTERCONNECT:NO LIMIT| | | | | Node Cap: 1.21PF |
| SPICE REF: IPL_PATH3 Last updated: 5/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IPL | PHI1+12 - LATE| IFB | PHI2 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IPL | | | | | |@
| I_S%NEW_FPA_INSTR_H |XXXXXXXX=======================XXXXXXXX| FP ACCELERATE FLAG; TO: IFB |
| MAX INTERCONNECT:NO LIMIT| | | | | Node Cap: 1.25PF |
| SPICE REF: IPL_PATH3 Last updated: 5/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IPL | PHI1+12 - LATE| IFB | PHI2 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IPL | | | | | |@
| I_S%IPLA_EXE_ADDRESS_H<6:0>|XXXXXXX========================XXXXXXXX| PARTIAL EXEC ADDRESS; |
| MAX INTERCONNECT: NO LIMIT | | | | | Node Cap: 2.02PF |
| SPICE REF: IPL_PATH3 Last updated: 5/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IPL |PHI1+12 - LATE | IAG | PHI4 - PHI2 | | | |
| IPL | | IOM | PHI4 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IPL | | | | | |@
| I_S%IPLA_DL_{2:0}_H<1:0> |XXXXXX=========================XXXXXXXX| OPERAND DL'S FOR OPS 1-3; TO: IAD |
| MAX INTERCONNECT:1200um | | | | | Node Cap: 1.15PF |
| SPICE REF: IPL_PATH3 Last updated: 5/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IPL | PHI1+12 - LATE| IAD | PHI1+12 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IPL | | | | | |@
| I_S%IPLA_AT_{2:0}_H<1:0> |XXXXXXX========================XXXXXXXX| OPERAND AT'S FOR OPS 1-3; TO: IAD |
| MAX INTERCONNECT:1200um | | | | | Node Cap: 957FF |
| SPICE REF: IPL_PATH3 Last updated: 5/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IPL | PHI1+12 - LATE| IAD | PHI1+12 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IPL | | | | | |@
| I_S%IPLA_SPECS_H<2:0> |====================XXXXXXXXXXXXXXXX===| # OF SPECS FOR OPCODE; |
| MAX INTERCONNECT: 1100um | | | | | Node Cap: 1.94PF |
| SPICE REF: IPL_PATH3 Last updated: 5/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IPL | PHI4+14 - PHI3| ISC | PHI4+18 - PHI2 | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 59
INSTRUCTION (I) BOX
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 60
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IM2 | | | | | |@
| I_S%B_GETS_IDR_H |====================/~~~~~~~~~XXXXXXX==| TO: IDD |
| MAX INTERCONNECT: 1500um | | | | | Node Cap: 1.85PF |
| SPICE REF: i_other_mib_decoder_sim im2_path1 Last updated: 4/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IM2 | phi1-7 - phi3 | IDD | PHI1 - PHI2+5 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IM2 | | | | | |@
| I_S%SET_VTR_H |===================/~~~~~~~~~~XXXXXXX==| TO: IMS |
| MAX INTERCONNECT: 2000um | | | | | Node Cap: 1.49PF |
| SPICE REF: i_other_mib_decoder_sim im2_path1 Last updated: 4/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IM2 | phi1-7 - phi3 | IMS | PHI1 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IM2 | | | | | |@
| I_S%CLEAR_VTR_H |===================/~~~~~~~~~~XXXXXXX==| TO: IMS |
| MAX INTERCONNECT: 2000um | | | | | Node Cap: 1.47PF |
| SPICE REF: i_other_mib_decoder_sim im2_path1 Last updated: 4/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IM2 | phi1-7 - phi3 | IMS | PHI1 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IM2 | | | | | |@
| I_S%READ_SPEC_H |XXXXXXXXX==============================| TO: ISU |
| MAX INTERCONNECT:NO LIMIT| | | | | Node Cap: 848.1FF |
| SPICE REF: none Last updated: 4/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IM2 | ~phi2 - ~phi1| ISU | PHI3 - PHI4 | none | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IM2 | | | | | |@
| I_S%WRITE_RN_H |=============================XXXXXXXXX=| TO: ISR |
| MAX INTERCONNECT: 1200um | | | | | Node Cap: 1.11PF |
| SPICE REF: none Last updated: 4/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IM2 | ~phi1 - ~Phi4 | ISR | PHI1+15 - PHI3 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 61
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| G_S%IB_FILL_REQ_H | SEE GLOBAL TIMING SHEETS | TO: MBOX |
| | | | | | LOAD = 3.1pF |
| SPICE REF: IQC_PATH3_SS_2 Last updated: 6/6/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |phi4-1 to phi2 | MBOX | PHI4 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| I_S%PFQ_HALTED_H |XXXXXXXXXXXXXXXXX======================| |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 1.51PF |
| SPICE REF: IQC_PAT3_SS_1 Last updated: 6/6/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |PHI2+15 - PHI1 | IOM | PHI2+15 - PHI4 | | | |
| IQC | | IP1 | PHI2+10 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| I_S%HAVE_ATL_6_BYTES_H |\_______________/======================| TO: IP1 |
| MAX INTERCONNECT: 2400um | | | | | Node Cap: 1.21PF |
| SPICE REF: IQC_PATH5 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |PHI2+18 - PHI1 | IP1 | PHI2+18 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| I_S%HAVE_ATL_5_BYTES_H |\_______________/======================| TO: IP1 |
| MAX INTERCONNECT: 2400um | | | | | Node Cap: 1.39PF |
| SPICE REF: IQC_PATH5 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |PHI2+18 - PHI1 | IP1 | PHI2+18 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| I_S%HAVE_ATL_4_BYTES_H |\_______________/======================| TO: IP1,IOM |
| MAX INTERCONNECT: 2400um | | | | | Node Cap: 1.60pf |
| SPICE REF: IQC_PATH5 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |PHI2+18 - PHI1 | IOM | PHI3 - PHI4 | | | |
| IQC | | IP1 | PHI2+18 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 62
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| I_S%HAVE_ATL_3_BYTES_H |\_______________/======================| TO: IP1 |
| MAX INTERCONNECT: 2400um | | | | | Node Cap: 1.21PF |
| SPICE REF: IQC_PATH5 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |PHI2+18 - PHI1 | IP1 | PHI2+18 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| I_S%HAVE_ATL_2_BYTES_H |\_______________/======================| TO: IP1,IOM |
| MAX INTERCONNECT: 2400um | | | | | Node Cap: 1.38PF |
| SPICE REF: IQC_PATH5 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |PHI2+18 - PHI1 | IOM | PHI3 - PHI4 | | | |
| IQC | | IP1 | PHI2+18 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| I_S%HAVE_ATL_1_BYTE_H |\_______________/======================| TO: IP1,IOM |
| MAX INTERCONNECT: 2400um | | | | | Node Cap: 1.34PF |
| SPICE REF: IQC_PATH5 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |PHI2+18 - PHI1 | IOM | PHI3 - PHI4 | | | |
| IQC | | IP1 | PHI2+18 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| I_S%HAVE_0_BYTES_H |\_______________/======================| |
| MAX INTERCONNECT: 2400um | | | | | Node Cap: 1.96PF |
| SPICE REF: IQC_PATH5 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |PHI2+18 - PHI1 | IOM | PHI3 - PHI4 | | | |
| IQC | | IP1 | PHI2+18 - PHI1 | | | |
| IQC | | ISC | PHI3 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| G_S%ONE_SLOT_FREE_H | SEE GLOBAL TIMING SHEETS | TO: MBOX |
| | | | | | LOAD: 2.7pF |
| SPICE REF: IQC_PATH1_SS_1,SS_2 Last updated: 3/5/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |PHI2+24 - PHI2 | MBOX | PHI3+5 - PHI2| | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 63
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| I_S%IB_PTR_L<3:0> |X============================XXXXXXXXXX| TO: IDD |
| MAX INTERCONNECT: 200um | | | | | Node Cap: 995.5FF |
| SPICE REF: IQC_PATH4 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |PHI4+25 - PHI4 | IDD | PHI1 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| I_S%LD_Q?_FRM_*_L |==========XXXXXXXXXX/~~~~~~~~~~~~~~~\==| TO: IDR |
| MAX INTERCONNECT:400um | | | | | Node Cap: 1.42PF |
| SPICE REF: IQC_PATH1_SS_* Last updated: 6/6/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |PHI4+22 | IDR | PHI4+21 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IQC | | | | | |@
| G_S%DELTA_PC_L<2:0> | SEE GLOBAL TIMING SHEETS | TO: EBOX |
| | | | | | LOAD = 2pF |
| SPICE REF: IQC_PATH2 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IQC |phi1+20 to phi3| EBOX | PHI1+20 - PHI3 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%SWAP_RN_H |===================////~~~~~~~XXXXXXXXX| TO: ISR |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 919.3FF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1 -phi3 | ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%DL_QUAD_H |_____/===\_____________________________| TO: IAD |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 1.76PF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+16-phi2+10| ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%DL_LONG_H |____/====\_____________________________| TO: IAD |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 1.71PF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+16-phi2+10| ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 64
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%DL_WORD_H |_____/===\_____________________________| TO: IAD |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 1.72PF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+16-phi2+10| ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%DL_BYTE_H |_____/===\_____________________________| TO: IAD |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 1.60PF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+16-phi2+10| ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%INCR_RN_IF_DL_Q_H |_____/===\_____________________________| TO: ISR |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 917.5FF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+16-phi2+10| ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%INCR_RN_H |____/====\_____________________________| TO: ISR |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 930.7FF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+16-phi2+10| ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%DECR_RN_H |_____/===\_____________________________| TO: ISR |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 738FF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+16-phi2+10| ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%CLEAR_RN_H |_____/===\_____________________________| TO: ISR |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 836FF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+16-phi2+10| ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 65
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%ENABLE_PFQ_H |_____/===\_____________________________| TO: IQC |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 1.38PF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+16-phi2+10| ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%DISABLE_PFQ_H |_____/===\_____________________________| TO: IQC |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 1.44PF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+16-phi2+10| ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%RESTART_PFQ_H |_____/===\_____________________________| TO: IQC |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 1.52PF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+16-phi2+10| ISR | PHI1+16 - PHI2 | no | no | no |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%CASE_LD_ID_H |============\\\\\\\\_______________/===| TO: IOM,IQC |
| MAX INTERCONNECT: 2000um | | | | | Node Cap: 3.60PF |
| SPICE REF: i_mib_decode_sim imd_path5 Last updated: 3/31/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi4+15-phi2+10| IDD | PHI4+17 - PHI2 | | | |
| IMD | | IOM | PHI4+14 - PHI2 | | | |
| IMD | | IQC | PHI4+14 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%CASE_LD_ID_DRIVE_H |___/=====\_____________________________| TO: ISU |
| MAX INTERCONNECT: 1000um | | | | | Node Cap: 1.43PF |
| SPICE REF: i_mib_decode_sim imd_path1 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+8 - phi2 | ISU | PHI1+8 - PHI2 | no | no | yes |
| IMD | | IQC | phi1+8 - phi2 | no | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 66
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%CASE_INT_RM_DRIVE_H |___/=====\_____________________________| TO: ISU |
| MAX INTERCONNECT: 1000um | | | | | Node Cap: 794FF |
| SPICE REF: i_mib_decode_sim imd_path1 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+8 - phi2 | ISU | PHI1+8 - PHI2 | no | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%CASE_FPA_DL_DRIVE_H |___/=====\_____________________________| TO: ISU |
| MAX INTERCONNECT: 1000um | | | | | Node Cap: 709FF |
| SPICE REF: i_mib_decode_sim imd_path1 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |phi1+8 - phi2 | ISU | PHI1+8 - PHI2 | no | no | yes |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%DECNEXT_H |============\\\\\\\\_______________/===| TO: IMS,ISC,ISR,IAG,IOM,IQC |
| MAX INTERCONNECT: 700um | | | | | Node Cap: 7.86PF |
| SPICE REF: i_mib_decode_sim imd_path6 Last updated: 4/1/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD | phi4+15 - phi2| IAG | PHI4+16 - PHI2 | | | |
| IMD | | IMS | PHI4+16 - PHI2 | | | |
| IMD | | IOM | PHI4+16 - PHI2 | | | |
| IMD | | IQC | PHI4+16 - PHI2 | | | |
| IMD | | ISC | PHI4+16 - PHI2 | | | |
| IMD | | ISR | PHI4+16 - PHI2 | | | |
| IMD | | IDD | PHI4+17 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%DECNEXT_REQ_H |XXXX==========================XXXXXXXXX| TO: ISC,ISR |
| MAX INTERCONNECT: 1500um | | | | | Node Cap: 1.50PF |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD | PHI1 - PHI4 | | PHI1 - PHI2 | | | |
| IMD | | IQC | PHI1 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 67
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| G_S%IID_LD_H | SEE GLOBAL TIMING SHEETS | TO: EBOX,IFB |
| | | | | | LOAD = 4.1pF |
| SPICE REF: i_mib_decode_sim imd_path9 Last updated: 4/1/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD | phi3+17 - phi1| IFB | PHI3+17 - PHI1 | | | |
| IMD | | EBOX | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_S%INOP_H |=========XXXXXXXXXXXXX=================| |
| MAX INTERCONNECT: 1500um | | | | | Node Cap: 3.38PF |
| SPICE REF: i_mib_decode_sim imd_path8, imd_path9 Last updated: 4/1/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD | phi3+13 - phi2| IMD | PHI4 - PHI2 | | | |
| IMD | | IQC | PHI4+5 - PHI2 | | | |
| IMD | | ISR | PHI4 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| I_C%LOAD_STATE_H |____________________/==========\_______| |
| MAX INTERCONNECT: 2000um | | | | | Node Cap: 6.69PF |
| SPICE REF: i_mib_decode_sim imd_path9 Last updated: 4/1/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD | phi3+12-phi4+5| IAD | PHI3+10 | | | |
| IMD | | IDD | "" | | | |
| IMD | | IFB | "" | | | |
| IMD | | IMD | "" | | | |
| IMD | | IOM | "" | | | |
| IMD | | ISC | "" | | | |
| IMD | | ISR | "" | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|I2P | | | | | |@
| I_S%IPLA_DL{5:3}<1:0> |XXXX=========================XXXXXXXXXX| TO: IAD |
| MAX INTERCONNECT:NO LIMIT| | | | | Node Cap: 691.89FF |
| SPICE REF: none Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| I2P | early - late | IAD | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 68
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|I2P | | | | | |@
| I_S%IPLA_AT{5:3}<1:0> |XXXX=========================XXXXXXXXXX| TO: IAD |
| MAX INTERCONNECT:NO LIMIT| | | | | Node Cap: 1.04PF |
| SPICE REF: none Last updated: 4/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| I2P | early - late | IAD | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISU | | | | | |@
| G_PH%UTEST_L<2:0> | SEE GLOBAL TIMING SHEETS | TO: USEQ |
| | | | | | LOAD = 4.5pF |
| SPICE REF: i_mib_decode_sim imd_path3 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISU | phi1+15 | USEQ | phi1+15 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISR | | | | | |
| I_S%I2D_EXP_H |XXXX===================================| TO: IOM,IP1 |
| MAX INTERCONNECT: 1400um | | | | | Node Cap: 2.00PF |
| SPICE REF: Last updated:7/15/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISR | PHI2-3 - PHI1 | IOM | PHI3 - PHI4 | | | |
| ISR | | IP1 | PHI2+10 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISR | | | | | |@
| I_S%SPEC_H<7:4> |===================XXXXXXXXX===========| TO: ISU |
| MAX INTERCONNECT:NO LIMIT| | | | | Node Cap: 1.27PF |
| SPICE REF: I_SPEC_RN_REG_SIM SPEC_RN_REG_CRIT_PATH_SS Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISR |PHI4+6 - PHI3 | ISU | PHI1+10 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISR | | | | | |
| G_S%OPCODE_H<7:0> | SEE GLOBAL TIMING SHEETS | |
| | | | | | LOAD = 1.75pF |
| SPICE REF: I_SPEC_RN_REG_SIM DATA_FLOW Last updated: 7/2/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISR |phi2+10 to phi4| EBOX |PHI2+11 TO PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 69
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|I2P | | | | | |@
| G_S%FPA_OPCODE_H<5:0> | SEE GLOBAL TIMING SHEETS | TO: FPA LOGIC |
| | | | | | LOAD = .9pF |
| SPICE REF: none - hand estimate done Last updated:7/15/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| I2P |phi2+13 to phi1| FPA | PHI2+13 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISR | | | | | |@
| I_S%RMODE_H |===================XXXXXXXXXXXXX=======| TO: ISU |
| MAX INTERCONNECT:NO LIMIT| | | | | Node Cap: 919.7 |
| SPICE REF: I_SPEC_RN_REG_SIM SPEC_RN_REG_CRIT_PATH_SS Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISR |PHI4+6 - PHI3 | ISU | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISR | | | | | |@
| I_S%RMODE_LAST_H |===================XXXXXXXXXXXX========| TO: ISU |
| MAX INTERCONNECT:NO LIMIT| | | | | Node Cap: 821FF |
| SPICE REF: I_S[EC_RN_REG_SIM SPEC_RN_REG_CRIT_PATH_SS Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISR |PHI4+10 - PHI3 | ISU | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISC | | | | | |@
| I_S%INDEX_EXP_H |XXXXXXXX===============================| TO:IP1 |
| MAX INTERCONNECT: 450um | | | | | Node Cap: 726FF |
| SPICE REF: ISC_PATH2 Last updated: 6/25/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISC |PHI2+5 - PHI1 | IP1 | PHI2+15 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISC | | | | | |@
| I_S%FAST_INDEX_EXP_H |XXXXXXX================================| TO: IIL |
| MAX INTERCONNECT: 1000um | | | | | Node Cap: 1.31PF |
| SPICE REF: ISC_PATH2 Last updated: 6/25/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISC |PHI1+18 - PHI1 | IIL | PHI1+18 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 70
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISC | | | | | |@
| I_S%SPEC_CTR_H<2:0> |XXXXXXXXXX=============================| TO: ISR,IP1 |
| MAX INTERCONNECT: 700um | | | | | Node Cap: 1.84PF |
| SPICE REF: ISC_PATH Last updated: 6/27/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISC |PHI2+11 - PHI1 | ISR | PHI2+11 - PHI4 | | | |
| ISC | | IP1 | PHI2+11 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISC | | | | | |@
| I_S%FAST_SPEC_CTR_H<2:0> |XXXXXX=================================| TO: IIL |
| MAX INTERCONNECT:1400um | | | | | Node Cap: 2.00PF |
| SPICE REF: ISC_? Last updated: 6/27/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISC |PHI1 + 17 | IIL | PHI1+19 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISC | | | | | |@
| G_S%SN_H<2:0> | SEE GLOBAL TIMING SHEETS | TO: EBOX |
| | | | | | LOAD = 1.8pF |
| SPICE REF: ISC_PATH1_SS_2 Last updated: 6/25/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISC | phi4 - phi3 | EBOX | PHI4 - PHI3 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISC | | | | | |@
| I_S%AT_DL_INDEX_H<2:0> |=============================XXXXXXXXXX| TO: IAD |
| MAX INTERCONNECT: 400um | | | | | Node Cap: 1.15PF |
| SPICE REF: ISC_PATH1 Last updated: 6/25/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISC |PHI1+1 - PHI4 | IAD | PHI1+3 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISC | | | | | |@
| I_S%SPECIAL_CASE_H |===================XXXXXXXXXX==========| TO: IOM |
| MAX INTERCONNECT: 1500um | | | | | Node Cap: 736FF |
| SPICE REF: ISC_PATH2 Last updated: 6/25/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISC |PHI3+15 - PHI2 | IOM | PHI4 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 71
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IAD | | | | | |@
| I_S%DATA_LENGTH_H<1:0> |===================XXXXXX==============| TO: ISR,ISU,IMD,IOM,IQC |
| MAX INTERCONNECT: 1200um | | | | | Node Cap: 3.21PF |
| SPICE REF: IAD_PATH1 Last updated: 6/6/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IAD | PHI4 - PHI3 | IOM | PHI4+10 - PHI2 | | | |
| IAD | | IMD | PHI4 - PHI2 | | | |
| IAD | | IQC | PHI4 - PHI2 | | | |
| IAD | | ISR | PHI1 - PHI2 | | | |
| IAD | | ISU | PHI4+10 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IAD | | | | | |@
| I_S%LAT_ACCESS_TYPE_H<1> |XXXXXX=================================| |
| MAX INTERCONNECT:NO LIMIT | | | | | Node Cap: 684FF |
| SPICE REF: IAD_PATH1 Last updated: 6/6/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IAD |PHI2+8 - PHI1 | IFB | PHI2+15 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IAD | | | | | |@
| G_S%AT_EQ_MOD_H | SEE GLOBAL TIMING SHEETS | TO: MBOX |
| | | | | | LOAD = 4pF |
| SPICE REF: I_AT_DL_REG_SIM IAD_PATH1 Last updated: 6/6/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IAD | phi4+3 - phi3 | MBOX | PHI4+3 - PHI3| | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IAD | | | | | |@
| G_S%ACCESS_TYPE_H<1:0> | SEE GLOBAL TIMING SHEETS | TO: USEQ |
| | | | | | LOAD = 3pF |
| SPICE REF: i_at_dl_reg_sim ext_sig_1_ss_1 Last updated: 6/6/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IAD | phi4 - phi3 | USEQ | PHI4 - PHI3 | | | |
| IAD | | IMD | PHI4 - PHI2 | | | |
| IAD | | ISU | PHI4+10 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 72
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IAD | | | | | |@
| G_S%DL_H<1:0> | SEE GLOBAL TIMING SHEETS | TO:USEQ,EBOX |
| | | | | | LOAD = 4pF |
| SPICE REF: i_at_dl_reg_sim ext_sig_1_ss_1 Last updated: 6/6/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IAD | phi4+2 - phi3 | USEQ | | | | |
| IAD | | EBOX | PHI4+2 - PHI3 | | | |
| IAD | | MBOX | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 73
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMS | | | | | |@
| G_S%COPY_TRACE_H | SEE GLOBAL TIMING SHEETS | TO: EBOX |
| | | | | | LOAD = 3pF |
| SPICE REF: IMS_PATH1_SS_4 Last updated: 6/23/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMS |phi1+9 -phi2+10| EBOX |PHI1+9 - PHI2+10| | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMS | | | | | |@
| I_S%LAT_XFD_BIT_H |=============================XXXXXXXXXX| TO: IFB,IPL,I2P,IIL |
| MAX INTERCONNECT: 1500um | | | | | Node cap: 2.65PF |
| SPICE REF: IMS_PATH1_SS_4 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMS |PHI1+16 - PHI4 | IFB | PHI3 - PHI4 | | | |
| IMS | | IPL | | | | |
| IMS | | I2P | | | | |
| IMS | | IIL | PHI2 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMS | | | | | |@
| I_S%LAT_VAX_TRAP_REQ_H |XXXX===================================| TO: IOM,IP1 |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.62PF |
| SPICE REF: IMS_PATH1_SS_3 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMS |PHI1+13 - PHI1 | IOM | PHI3 - PHI4 | | | |
| IMS | | IP1 | PHI2+10 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMS | | | | | |@
| I_S%LAT_PSL_TP_H |XXXXXXXXXXXXXXXXXX=====================| TO: IOM,IP1 |
| MAX INTERCONNECT: 1000um | | | | | Node cap: 1.26PF |
| SPICE REF: IMS_PATH1_SS_4 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMS |PHI1+18 - PHI1 | IP1 | PHI2 - PHI1 | | | |
| IMS | | IOM | PHI3 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMS | | | | | |@
| I_S%LAT_PSL_FPD_H |=========XXXXXXXXX=====================| TO: IP1 |
| MAX INTERCONNECT:no limit| | | | | Node cap: 1.11PF |
| SPICE REF: NONE NEEDED Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMS | 1 CYCLE EARLY | IP1 | PHI2 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 74
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IFB | | | | | |@
| G_S%FD_BIT_L | SEE GLOBAL TIMING SHEETS | TO: FPA |
| | | | | | LOAD = 1.25pF |
| SPICE REF: IFB_PATH1_SS_1,2 Last updated: 5/13/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IFB |phi2+10 - phi4 | FPA | PHI2+9 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IFB | | | | | |@
| G_S%FP_INTEGER_L | SEE GLOBAL TIMING SHEETS | TO: FPA |
| | | | | | LOAD = 1.2pF |
| SPICE REF: IFB_PATH1_SS_2,1 Last updated: 5/13/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IFB |phi2+10 - phi4 | FPA | PHI2+9 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IFB | | | | | |@
| G_S%BRDCST_OK_H | SEE GLOBAL TIMING SHEETS | TO: EBOX |
| | | | | | LOAD = 4.2pF |
| SPICE REF: IFB_PATH1_SS_1,2 Last updated: 5/13/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IFB | phi4 to phi3 | EBOX | PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IFB | | | | | |@
| I_S%LAT_FPU_PRESENT_H |=======================================| TO: ISU,IIL |
| MAX INTERCONNECT:no limit| | | | | Node cap: 2.68PF |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IFB | ALWAYS | IIL | PHI1 - PHI4 | | | |
| IFB | | ISU | PHI4+10 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 75
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IAG | | | | | |@
| G_S%IMAB_H<10:0> | SEE GLOBAL TIMING SHEETS | TO: USEQ |
| | | | | | LOAD = .9pF |
| SPICE REF: i_address_generator IAG_PATH1 Last updated: 6/13/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IAG |phi1+9 to phi4 | USEQ | PHI1+9 - PHI3 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IIL | | | | | |@
| I_S%IID_EXE_ADDRESS_H<3:0>|====================XXXXXX=============| TO: IAG |
| MAX INTERCONNECT:no limit | | | | | Node cap: 1.21PF |
| SPICE REF: IIL_PATH2 Last updated: 6/26/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IIL |PHI3+13 - PHI3 | IAG | PHI4 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IIL | | | | | |@
| I_S%BYTES_NEEDED_H<1:0> |\______________/=======================| TO: IP1 |
| MAX INTERCONNECT: 2500um | | | | | Node cap: 1.83PF |
| SPICE REF: IIL_PATH2_SS_1 Last updated: 6/26/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IIL |PHI2+16 - PHI1 | IP1 | PHI2+20 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| I_S%SET_INDEX_EXPECTED_H |====================XXXXXXX============| TO: ISC |@
| MAX INTERCONNECT:no limit| | | | | Node cap: 1.40PF |
| SPICE REF: IIL_PATH2 Last updated: 6/26/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IIL |PHI3+16 - PHI2 | ISC | PHI4 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IIL | | | | | |@
| I_S%SPEC_ADDRESS_OFFSET |====================XXXXXXX============| TO: IAG,ISC |
| _H<3:0> | | | | | |
| MAX INTERCONNECT:no limit| | | | | Node cap: 1.67PF |
| SPICE REF: IIL_PATH2_SS_1 Last updated: 6/26/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IIL |PHI3+16 - PHI2 | IAG | PHI4 - PHI2 | | | |
| IIL | | ISC | PHI4 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IIL | | | | | |@
| I_S%ILLEGAL_OPCODE_H |XXXXXXXXXXXXXXXX=======================| TO: IP1 |
| MAX INTERCONNECT: 2500um | | | | | Node cap: 2.65PF |
| SPICE REF: IIL_PATH2 Last updated: 6/26/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IIL |PHI2+16 - PHI1 | IP1 | PHI2+15 - PHI1 | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 76
INSTRUCTION (I) BOX
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 77
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IIL | | | | | |@
| I_S%SET_XFD_H |==========XXXXXXXXXXXXX================| TO: IMS |
| MAX INTERCONNECT:no limit| | | | | Node cap: 1.36PF |
| SPICE REF: IIL_PATH2 (EXTRAPOLATED) Last updated: 6/27/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IIL |PHI3+16 - PHI2 | IMS | PHI4+10 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IIL | | | | | |@
| I_S%BRANCH_WORD_H |~~~~~~~~~~~~~~~~\======================| |
| MAX INTERCONNECT: 2500um | | | | | Node cap: 1.96PF |
| SPICE REF: IIL_PATH2_SS_1 Last updated: 6/26/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IIL |PHI2+13 - PHI1 | IOM | PHI4 - PHI1 | | | |
| IIL | | IP1 | PHI2+15 - PHI1| | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IIL | | | | | |@
| I_S%BRANCH_BYTE_H |~~~~~~~~~~~~~~~~\======================| |
| MAX INTERCONNECT: 2500um | | | | | Node cap: 1.96PF |
| SPICE REF: ILL_PATH2_SS_1 Last updated: 6/26/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IIL |PHI2+13 - PHI1 | IOM | PHI4 - PHI1 | | | |
| IIL | | IP1 | PHI2+15 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IIL | | | | | |@
| I_S%NO_SPECIFIERS_H |~~~~~~~~~~~~~~~~\======================| TO: IP1 |
| MAX INTERCONNECT: 2500um | | | | | Node cap: 2.06PF |
| SPICE REF: IIL_PATH2_SS_1 Last updated: 6/26/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IIL |PHI2+13 - PHI1 | IP1 | PHI2+15 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IIL | | | | | |@
| I_S%LOW_BYTE_EQ_FD_L |XXXXXXXXXXXX=================XXXXXXXXXX| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.75PF |
| SPICE REF: IIL_PATH2_SS_1 Last updated: 5/8/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IIL |PHI2+6 - PHI4 | IP1 | PHI2+10 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 78
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IPL | | | | | |@
| G_S%I_RED_OUT_H | SEE GLOBAL TIMING SHEETS | TO: USEQ |
| | | | | | |
| SPICE REF: none - don't care Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IPL | | USEQ | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%EN_NEW_DELTA_PC_H<5:0> |=========\___________///////////=======| TO: IQC |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 2.20PF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IQC | PHI4+7 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%EN_IDR_EFF_DL_H<1:0> |=========\___________///////////=======| TO: IOM |
| MAX INTERCONNECT: 1500um | | | | | Node cap: 698FF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IOM | PHI4+7 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%EN_ADD_TO_IB_PTR_H |=========\___________///////////=======| TO: IQC |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 2.08PF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IQC | PHI4+10 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%EN_RESET_SPEC_CTR_H |=========\___________///////////=======| TO: ISC |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.07PF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | ISC | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%EN_DECR_SPEC_CTR_H |=========\___________///////////=======| TO: ISC |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 714FF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | ISC | PHI4+7 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 79
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%IID_THINGS_OK_H |=========\___________///////////=======| TO: IOM |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 928FF |
| SPICE REF: IP1_PATH1 Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IOM | PHI4+7 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
|I_S%IDR_NEW_DELTA_PC_H<2,0> |===================XXXXXXXX============| TO: IQC |
| MAX INTERCONNECT: 1500um | | | | | Node cap: 1.22PF |
| SPICE REF: IOM_PATH2_SS_2 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |PHI3+18 - PHI3 | IQC | PHI3+18 - PHI3 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%IDR_UTRAP_HLT_H |===================XXXXXXXXXX==========| TO: ISU |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.24PF |
| SPICE REF: IOM_PATH2_SS_2 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |PHI4+0 - PHI3 | ISU | PHI4+10 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%IDR_UTRAP_DRY_H |===================XXXXXX==============| TO: ISU |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.12PF |
| SPICE REF: IOM_PATH2_SS_1 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |PHI1-3 - PHI3 | ISU | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%ADD_TO_IB_PTR_H |===================XXXXXX==============| TO: IQC |
| MAX INTERCONNECT:2500um | | | | | Node cap: 1.77PF |
| SPICE REF: IOM_PATH2_SS_1 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |PHI4+14 - PHI3 | IQC | PHI4+16 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 80
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%IDR_EFF_DL_H<1:0> |====================XXXXXXXXX==========| |
| MAX INTERCONNECT: 1000um | | | | | Node cap: 2.19PF |
| SPICE REF: IOM_PATH1_SS_1 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |PHI4-3 - PHI3 | IDD | PHI4 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%IDR_LOAD_INDEX_H<1:0>|=========XXXXXXX=======================| |
| MAX INTERCONNECT: 1000um | | | | | Node cap: 2.09PF |
| SPICE REF: IOM_PATH1_SS_1 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |PHI2+11 - PHI2 | IDD | PHI2+15 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%CATCH_IPLA_H |~~~~~~~~~\__________________________/~~| TO: IPL,I2P |
| MAX INTERCONNECT: 1500um | | | | | Node cap: 3.31PF |
| SPICE REF: IOM_PATH1_SS_1 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |PHI4+22 - PHI2 | IPL | PHI1 - PHI2 | | | |
| IOM | | I2P | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%EN_ASSERT_IID_H |=========XXXXXX========================| TO: IMD,ISR |
| MAX INTERCONNECT: 1200um | | | | | Node cap: 1.24PF |
| SPICE REF: NONE NEEDED Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |PHI3 - PHI2 | IMD | PHI3 - PHI1+5 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 81
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%EN_CLR_XFD_BIT_H |==========\__________________/XXXXXXX==| TO: IMS |
| MAX INTERCONNECT: 500um | | | | | Node cap: 1.03PF |
| SPICE REF: NONE NEEDED Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |PHI1 - PHI2 | IMS | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%TP_GETS_T_H |==========\__________________/XXXXXXX==| TO: IMS |
| MAX INTERCONNECT: 500um | | | | | Node cap: 693FF |
| SPICE REF: IOM_PATH1_SS_1 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |RISES W/PHI1-PHI2| IMS | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%LOAD_AT_DL_REG_H |==========\__________________/XXXXXXX==| TO: IAD |
| MAX INTERCONNECT: 1000um | | | | | Node cap: 949.5FF |
| SPICE REF: IOM_PATH1_SS_1 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |RISES W/PHI1-PHI2| IAD | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%LOADING_OPCODE_H |==========\__________________XXXXXXXX==| TO: ISR |
| MAX INTERCONNECT:1000um | | | | | Node cap: 2.05PF |
| SPICE REF: IOM_PATH1_SS_1 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |RISES W/PHI1-PHI2| ISR | PHI1 - PHI2 | | | |
| IOM | | I2P | PHI1 - PHI2 | | | |
| IOM | | IMS | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| I_S%LOADING_SPEC_RN_REG_H|=========\____________________XXXXXXX==| |
| MAX INTERCONNECT: 1000um | | | | | Node cap: 1.21PF |
| SPICE REF: IOM_PATH1_SS_1 Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |RISES W/PHI1-PHI2| ISR | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 82
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|ISR | | | | | |@
| G_S%RN_H<3:0> | SEE GLOBAL TIMING SHEETS | |
| | | | | | LOAD = 2.3pF |
| SPICE REF: i_spec_rn_reg_sim SPEC_RN_REG_CRIT_PATH_H_SS Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISR | PHI4+1 TO PHI3| ISU | PHI4+2 - PHI3| | | |
| ISR | phi4+1 to phi3| EBOX | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|CHIP | | | | | |@
| G_PH%STALL_L | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| | | IMD |PHI3-1 TO PHI1 | YES | YES | YES |
| | | |PHI3+5 TO PHI4 | NO | YES | YES |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|PADS | | | | | |@
| G_S%RESET_S_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| BIU | | IFB | ANY OLD TIME | | | |
| BIU | | IMD | "" | | | |
| BIU | | IMS | "" | | | |
| BIU | | IQC | "" | | | |
| BIU | | ISC | "" | | | |
| BIU | | IPL | "" | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|EBOX | | | | | |@
| G_S%LD_VIBA_AND_PC_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| EBOX | | IQC | PHI3+7 - PHI4 | NO | | |
| EBOX | | IMD | PHI3+10 - PHI4 | NO | | |
| EBOX | | IMS | PHI4 - PHI1 | NO | | |
| EBOX | | IOM | PHI4 - PHI1 | NO | | |
| EBOX | | ISC | PHI3+10 - PHI4 | NO | | |
| EBOX | | ISR | ANY OLD TIME | NO | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 83
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|EBOX | | | | | |@
| G_PH%W_SPUR_H<7:0> | SEE GLOBAL TIMING SHEETS | |
| | | | | | LOAD = 6.5pF |
| SPICE REF: i_spur_utest_drIVE_sim ISU_PATH1_SS_1 Last updated: 4/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| ISU | phi4-2 | EBOX | | | | |
| | | ISR |PHI2 TO PHI3 | NO | YES | YES |
| | | ISU | X | | | |
| | | IMS | G_S%LOAD_PSL_H | NO | YES | YES |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|EBOX | | | | | |@
| G_S%PSL_T_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| EBOX | | IMS |ON G_S%LOAD_PSL_H| | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|EBOX | | | | | |@
| G_S%LOAD_PSL_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| EBOX | | IMS | PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|INTL | | | | | |@
| G_S%FPD_INT_PENDING_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| INTL | | ISU | phi3+10- phi4+5| | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|BIU | | | | | |@
| G_S%BIU_TRAP_L | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| | | IMD | PHI3 - phi1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 84
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|FPA | | | | | |@
| G_S%FPU_TRAP_L | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| FPA | | IMD | PHI3 -PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|MBOX | | | | | |@
| G_PH%MMGT_TRAP_L | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| | | IMD | PHI3 -PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|EBOX | | | | | |@
| G_S%INT_OVFL_L | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| EBOX | | IMD | PHI3 - PHI1| | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|USEQ | | | | | |@
| G_S%MIB_H,G_S%MIB_L<40:7>| SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| USEQ | | IMD | PHI4-1 - PHI2| | | |
| USEQ | | IM2 | PHI4-1 - PHI2| | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|FPA | | | | | |@
| G_S%FPU_IS_THERE_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| FPA | | IFB | AT POWERUP | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|BIU | | | | | |@
| G_S%IDAL_H<31:0> | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| BIU | | IDP | PHI4+10 - PHI2 | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 85
INSTRUCTION (I) BOX
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 86
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|INTL | | | | | |@
| G_S%IID_IRQ_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| INTL | | IP1 |PHI2+16 - PHI1 | | | |
| INTL | | IOM |PHI3+15 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|EBOX | | | | | |@
| G_S%NEW_IB_PTR_H<1:0> | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| EBOX | | IQC | PHI2+14 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|BIU | | | | | |@
| G_PH%IB_FILL_ERR_L | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| BIU | | IQC | PHI2+21 - PHI1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|BIU | | | | | |@
| G_S%IB_DATA_PRS_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| BIU | | IQC | PHI1+15 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|TEST | | | | | |@
| G_S%LOAD_REDUCERS_L | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| TEST | | IPL | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|TEST | | | | | |@
| G_C%REDUCE_PHI1_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| | | IPL | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 87
INSTRUCTION (I) BOX
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 88
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|TEST | | | | | |@
| G_C%SCAN_PHI1_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| | | IPL | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|CLK | | | | | |@
| G_C%PHI1_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| | | IAG | | | | |@
| | | IAD | | | | |
| | | IDD | | | | |
| | | IIL | | | | |
| | | IPL | | | | |
| | | IMD | | | | |
| | | IMS | | | | |
| | | IOM | | | | |
| | | IM2 | | | | |
| | | IQC | | | | |
| | | I2P | | | | |
| | | IWC | | | | |
| | | ISR | | | | |
| | | ISU | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|CLK | | | | | |
| G_C%PHI2_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| | | IDP | | | | |@
| | | IP1 | | | | |
| | | IDD | | | | |
| | | IIL | | | | |
| | | IPL | | | | |
| | | IMD | | | | |
| | | IOM | | | | |
| | | IQC | | | | |
| | | I2P | | | | |
| | | ISC | | | | |
| | | ISR | | | | |
| | | ISU | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 89
INSTRUCTION (I) BOX
@
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|CLK | | | | | |@
| G_C%PHI3_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| | | IAG | | | | |
| | | IAD | | | | |
| | | IDP | | | | |
| | | IDD | | | | |
| | | IIL | | | | |
| | | IPL | | | | |
| | | IMD | | | | |
| | | IMS | | | | |
| | | IOM | | | | |
| | | IM2 | | | | |
| | | IQC | | | | |
| | | I2P | | | | |
| | | ISC | | | | |
| | | IDR | | | | |
| | | ISU | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|CLK | | | | | |@
| G_C%PHI4_H | SEE GLOBAL TIMING SHEETS | |
| | | | | | |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| | | IAG | | | | |
| | | IAD | | | | |
| | | IDP | | | | |
| | | IPL | | | | |
| | | IMD | | | | |
| | | IMS | | | | |
| | | IOM | | | | |
| | | IM2 | | | | |
| | | IQC | | | | |
| | | I2P | | | | |
| | | ISC | | | | |
| | | ISR | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_IB_HLT_ADDRESS_H |===========\_________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.01PF |
| SPICE REF: IP1_PATH1 Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IAG | PHI4+5 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 90
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_IID_EXE_ADDRESS_H |=========\___________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.55PF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IAG | PHI4+5 - PHI2 | | | |
| IP1 | | ISR | PHI4+10 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_SPEC_ADR_H |=========\___________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.57PF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IAG | PHI4+5 - PHI2 | | | |
| IP1 | | IOM | PHI4+5 - PHI2 | | | |
| IP1 | | ISC | PHI4+5 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_SPEC_ADR_NDX_H |=========\___________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.32PF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IAG | PHI4+5 - PHI2 | | | |
| IP1 | | IOM | PHI4+5 - PHI2 | | | |
| IP1 | | ISC | PHI4+5 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_IB_DRY_ADR_H |=========\___________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 997FF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IAG | PHI4+5 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_VTR_ADR_H |=========\___________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 707FF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IAG | PHI4+5 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 91
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_INT_ADR_H |=========\___________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 697FF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IAG | PHI4+5 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_TBIT_ADR_H |=========\___________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 622FF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IAG | PHI4+5 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_FPD_ADR_H |=========\___________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.54PF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | ISR | PHI4+10 - PHI2 | | | |
| IP1 | | IAG | PHI4+5 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_ILLEG_OPC_ADR_H |=========\___________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 765FF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IAG | PHI4+5 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_EXE_ADR_H |=========\___________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.29PF |
| SPICE REF: IP1_PATH1 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+7 - PHI2 | IOM | PHI4+10 - PHI2 | | | |
| IP1 | | IAG | PHI4+5 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 92
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%USE_XFD_ADR_H |=========\___________////////==========| |
| MAX INTERCONNECT: 2000um | | | | | Node cap: 1.06PF |
| SPICE REF: IP1_PATH2 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+22 - PHI3 | ISR | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IAG | | | | | |@
| I_S%CLR_XFD_H |===================XXXXXXXXXXXXXXXXX===| |
| MAX INTERCONNECT: 350um | | | | | Node cap: 1.29PF |
| SPICE REF: IAG_PATH3 Last updated: 6/13/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IAG |PHI4+14 - PHI2 | IMS | PHI4+16 - PHI2 | | | |
| IAG | | ISR | PHI1 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IAD | | | | | |@
| I_S%LAT_DL_REG_H<1:0> |XXXXXXXXXXXXXXX========================| |
| MAX INTERCONNECT: 1000um | | | | | Node cap: 1.03PF |
| SPICE REF: I_AT_DL_REG_SIM DL4_TO_MLATCH_H_SS Last updated: 6/24/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IAD |PHI2+16 - PHI1 | IOM | PHI2+18 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%SPEC_CTR_GEQ_2_H |XXXXXXXXXXXXXX=========================| |
| MAX INTERCONNECT: 1000um | | | | | Node cap: 1.21PF |
| SPICE REF: IP1_PATH3 Last updated: 6/13/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI2+18 - PHI1 | IOM | PHI2+18 - PHI3 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%SPEC_CTR_ZERO_L |XXXXXXXXXXXXXX=========================| |
| MAX INTERCONNECT: 1000um | | | | | Node cap: 1.88PF |
| SPICE REF: IP1_PATH3 Last updated: 6/13/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI2+18 - PHI1 | IOM | PHI2+18 - PHI3 | | | |
| IP1 | | IFB | PHI2+18 - PHI4 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 93
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IP1 | | | | | |@
| I_S%NOT_XFD_H |====================/~~~~~~~~~~\\\=====| |
| MAX INTERCONNECT: 500um | | | | | Node cap: 1.40PF |
| SPICE REF: IP1_PATH2 Last updated: 6/11/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IP1 |PHI4+16 - PHI3 | IAG | PHI4+16 - PHI2 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IOM | | | | | |@
| G_S%LOAD_MASTER_OPCODE_H |===============================XXXXXXX=| |
| | | | | | LOAD = 2.2pF |
| SPICE REF: I_OP_MUX_IM LOAD_MASTER_1_SS_1 Last updated: 7/10/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IOM |PHI1+12 - PHI4+| EBOX | phi1+12 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| G_S%LOAD_SLAVE_OPCODE_H |_____________________/========\________| |
| | | | | | CAP: 1.20PF |
| SPICE REF: I_MIB_DECODE_SIM IMD_PATH9 Last updated: 4/14/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |PHI3+16-PHI4+10| EBOX | phi3+16 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IM2 | | | | | |@
| G_S%SPUR_GETS_OPCODE_H |XXXXXXXXX==============================| |
| | | | | | |
| SPICE REF: NONE - HAND ESTIMATE DONE Last updated: 7/8/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IM2 | PHI2 - PHI1 | EBOX | phi3 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IMD | | | | | |@
| G_S%UTEST_GETS_OPCODE_H |===================/~~~~~~~~~XXXXXXXXXX| |
| | | | | | CAP: .5PF |
| SPICE REF: I_MIB_DECODE_SIM IMD_PATH2 Last updated: 3/28/86 |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IMD |PHI1 - PHI2+ | EBOX | phi1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_S%LD_ID_MASTER_H |/========\_____________________________| |
| | | | | | Node cap: 3.45PF |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |PHI1 - PHI2+ | IDP | phi1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 94
INSTRUCTION (I) BOX
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |@
V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
|IDD | | | | | |@
| I_S%LD_ID_MASTER_L |\========/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| |
| | | | | | Node cap: 4.08PF |
| SPICE REF: Last updated: |
| Driven by When valid Used by When needed Hidden cap? Pullups? Pulldowns? |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| IDD |PHI1 - PHI2+ | IDP | phi1 | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 95
INSTRUCTION (I) BOX
2.12 Glossary Of Mnemonics
The following is a partial list of mnemonics and their translations or
meanings:
BCS - Branch Condition Select - A field in the microinstruction
BIU - Bus Interface Unit
BPC - Backup PC register
CFPA - CVAX Floating Point Accelerator chip
DL - Data Length
FPA - see CFPA
FPU - see CFPA
GPR - General Purpose Register
IB - Instruction Buffer
IDAL - Internal Data/Address Lines
IDR - Instruction Data Register
IID - Initial Instruction Decode
IPLA - Instruction PLA
MAB - MicroAddress Bus
PFQ - Prefetch Queue (see also IB)
QMUX - Prefetch Queue Output Multiplexor
RLOG - Register Modification Log
RN - Register Number
TB - Translation Buffer
VIBA - Virtual Instruction Buffer Address Register
WR - Working Register
CVAX CPU CHIP DESIGN SPECIFICATION Page 96
INSTRUCTION (I) BOX
2.13 CHANGE REQUESTS THAT HAVE BEEN INCLUDED HERE
The following change requests have been reflected in this rev of the spec:
o 5MAY12DWA.1
o 5JUN01PIR.1
o 5JUL01A0.1
o 5AUG01DWA.1
o 5AUG20DS.1
o 5AUG20DWA.1
o 5AUG30AO.1
o 5SEP25AO.1
o 5SEP25PEG.1
o 5NOV05DWA.1
o 5NOV05DWA.2
o 5DEC05DWA.1
o 5DEC11DWA.1
o 6JAN03DWA.1
o 6JAN08DWA.1
o 6JAN31DWA.1
o 6JAN31DWA.2
o 6JAN31DWA.3
o 6FEB19DWA.1
o 6FEB19DWA.2
2.14 ISSUES
The following issues must be resolved in order to finish this spec. Note
that items followed by a [RESOLVED] have been decided, and the spec
updated to reflect that decision.
CVAX CPU CHIP DESIGN SPECIFICATION Page 97
INSTRUCTION (I) BOX
1. Can the registers addressed in the memreq MXPS operation become A
port addresses 30-3F?
ANS: 6/29/8 D.W.A. - NO, ROUTING PROBLEMS PROHIBIT THIS
2. What must the I Box do about integer overflow? Should this be an
E Box function?
ANS: 6/29/84 D.W.A. - THE I BOX DOES NOTHING ABOUT INTEGER
OVERFLOW ANY MORE. THE E Box CONTROLS THIS FUNCTION.
3. How do you set the FPD bit?
ANS: 6/29/84 D.W.A. - MICROCODE SETS AND CLEARS FPD FOR CERTAIN
INSTRUCTIONS.
4. What is the performance hit if the I Box requires a cycle between
setting AT or DL and doing a dispatch or LOAD ID?
ANS: 6/29/84 D.W.A. - THERE ARE NO AT OR DL DEPENDENT INITIAL
DISPATCHES.
5. Is the ability to load IDR automatically on detection of an
immediate operand helpful? Such operands appear very seldom,
according to Emer and Clark.
ANS: 6/29/84 D.W.A. - USEFUL, BUT ON A VERY SMALL PERCENTAGE OF
INSTRUCTIONS. AUTOMATIC HANDLING OF IMMEDIATE OPERANDS WILL NOT
BE DONE.
6. Should the IPLA be a ROM or a true PLA?
ANS: 7/9/84 D.W.A. - ROM, FOR UCODE FLEXIBILITY AND AREA
CONSIDERATIONS.
7. Can the FPA Instruction flag bit in the IPLA be removed? The
microcode at the FPA execute address could do a case on FPU
present using one of the partially empty branch fields like 1A
(MREF.STATUS) and go to illegal opcode if FPU present is clear.
ANS: 7/16/84 D.W.A. - NO, THE FPA BIT CANNOT BE REMOVED.
8. We must have a way to explicitly clear XFD during error flows;
probably a MISC field. This is for use where some exception
occurs between parsing FD and the opcode byte that follows it.
We must remove the functionality that clears XFD during LOAD VIBA
and PC commands. Alternatively, we might want to make two MISC
fields that load VIBA and PC, and have only one of them do the
CLR XFD function.
ANS: 7/16/84 D.W.A - NO WAY. WE'LL LEAVE THE XFD CONTROL AS IS,
CLEARING IT AT LOAD VIBA AND PC.
CVAX CPU CHIP DESIGN SPECIFICATION Page 98
INSTRUCTION (I) BOX
9. We should grab the new values of PC<1:0> (at branch time) from
the W-bus via the spur instead of loading from dedicated lines
running from the PC to the I Box.
ANS: 7/18/84 D.W.A. - NO. CAN'T LOAD FROM BPC IF WE DO THIS.
10. How does Integer Overflow Trap affect the PSL.T, PSL.TP
functionality? In the case of an integer overflow when PSL.T
should be set at the end of the instruction, we must insure that
the overflow trap routine is executed properly. Check out how
the T and TP bits function in uVAX. The implementation is
correct there.
ANS: 9/1/84 D.W.A. - THE TRACE BIT GETS COPIED AT IID TIME.
MICROCODE CLEARS THE TRACE BIT BEFORE ISSUING THE NEXT IID.
11. We must insure that uTraps issued by memory management take
priority over those issued by the I Box due to prefetching
problems.
ANS: 7/2/84 D.W.A. - yes.
12. How does the FPA get the opcode for FPA instructions? We must
insure that the FPA gets one opcode which is unique per
instruction, i.e., the XFD code MUST NOT be sent to the FPA
before the real opcode. We will need another PLA to determine if
the opcode being decoded is an accelerated integer instruction.
ANS: 3/7/85 D.W.A. - OPCODE<5:0> WILL BE SENT, ALONG WITH THE
CPSTA CODE. OPCODE<7:0> AND FD BIT WILL BE SENT TO FPA LOGIC,
WHICH WILL DO THE ENCODING.
13. What testability functions should we have?
ANS: 2/20/85 D.W.A. - DATA REDUCERS ON OUTPUT OF IPLA, DISPATCH
PLA, AND OPERATION MUX
14. Do we need to break R=PC out of the mode A-F dispatches as
separate addresses?
ANS: 3/1/85 D.W.A. - NO. E BOX CAN HANDLE THE PC REFERENCE
JUST FINE
CVAX CPU CHIP DESIGN SPECIFICATION Page 99
EXECUTION (E) BOX
3 EXECUTION (E) BOX
The E BOX contains the main execution data path and associated control
logic.
It consists of the following major functions:
o Register File
o Program Counter (PC Register)
o Constant Generator
o Shift Counter (SC)
o Shifter
o Arithmetic Logical Unit (ALU)
o Multiplier Quotient Register (Q)
o Processor Status Longword (PSL)
o Condition Code Logic
o Register Logging (RLOG) Stack
o State Logic
o Opcode Register
The E BOX performs most calculations for the micromachine. It receives
memory data from the I BOX. It is controlled by the microinstruction and
a limited amount of internal state.
The key innovative concept in the CVAX E BOX is the pipelining of
operations in the data path. In each cycle, the E BOX reads two operands
out of the register file, performs an operation on them (either in the ALU
or the Shifter), and latches the result. The latched result is written
back to the register file during the very end of the CURRENT cycle and the
first part of the NEXT microcycle. The pipeline timing is shown below:
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |
v------------------------v----------+---------+---------+----------v---------------------------------------------------v
| FUNCTION |0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 0| |
| Name |0-5-0-5-0-5-0-5-0-5-0-5-0-5-0-5-0-5-0-5-0| Comments |
^------------------------^+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+^---------------------------------------------------^
+ + + + +
A & B_BUS SELECT ///~~~~~~~~\\\\_________________________/ Read Selects Driven G_C%PHI1_H
+ + + + +
G_PH%B_BUS_H<31:0> ~~XXXXXXX=====================HHHHHHHHHHH B Bus
+ + + + +
E_PH%A_BUS_H<31:0> ~~XXXXXXX=====================HHHHHHHHHHH A Bus
CVAX CPU CHIP DESIGN SPECIFICATION Page 100
EXECUTION (E) BOX
+ + + + +
ALU OPERATION __________XXXXXXXXXXXXXXXXXXXXXXXXXX_____ Operates from G_C%PHI2_H through the middle of G_C%PHI4_H
+ + + + +
SHIFT OPERATION ____________________XXXXXXXXXXXXXXXX_____ Operates from G_C%PHI3_H through the middle of G_C%PHI4_H
+ + + + +
W_BUS SELECT ~~~~~~~~~~\___________________/~~~~~~~~~~ Select During G_C%PHI4_H and G_C%PHI1_H
+ + + + +
G_S%W_BUS_H<31:0> ==============================XXXXXXXXXX= Write Bus. Guarenteed valid by t0.
+ + + + +
The principal complications caused by this structure are:
1. The W_Bus decode is determined from the previous
microinstruction; i.e., the register file write is pipelined.
2. Since the write is pipelined, the data path must be designed so
that when either (or both) of the A_Bus and B_Bus register
selects match the previous W_Bus select, the new W_Bus data is
used instead of the stale register data.
This is illustrated in the following microcode sequence:
;-------------------------------;
[W0]<--[W0]+[W1] ; B_Bus select = [W1]
; A_Bus select = [W0]
; W_Bus select = [W0]
;-------------------------------;
[SP]<--[SP]-[W0] ; B_Bus select = [W0],
; W_Bus data must appear
; on the B_Bus
; A_Bus select = [SP]
; W_Bus select = [SP]
This is achieved by a fast write back which alters the register cell
before a read occurs.
CVAX CPU CHIP DESIGN SPECIFICATION Page 101
EXECUTION (E) BOX
3.1 Register File
The Register File is logically divided into three sections: The triple
ported W Registers; the dual ported GP Registers; and the dual ported T
Registers. All three sections can be written as longwords. The GP
Registers, with the exception of the PC, can all be written in a
data-length dependent manner.
3.1.1 Triple Ported Registers (W Registers) -
Eight of the locations in the register file are triple ported; that is,
they may be read through the A port and B port, and written through the W
port, simultaneously. These registers are the microcode working
registers, W[0:7].
In some cases, a W Register can be used as the destination register for 3
address arithmetic. A W Register is written (independent of A or B
selects) when the DST=WSN is selected in the microinstruction. W[6] is
reserved for memory management, with W[6]<1:0> being hardwired to 00 to
optimize memory management microcode.
W[7] is the SC register. While SC is useable as a normal working
register, it has other functions as well. For a description of these
functions, see the SC Logic section.
3.1.2 Dual Ported Registers (GP Registers) -
There are fifteen dual ported general purpose registers, GPR[0:14], in the
register file. They may be read through the A port and written through
the W port simultaneously. GPR[0:13] are the user visible registers R0 -
R13. GPR[14] is the user visible SP. GPR[15], the PC, is not located in
register file. The GPR's, with the exception of the PC, can all be
written in a data-length dependent manner.
3.1.2.1 Data-Length Dependent Writes -
Writes to the general purpose registers can be to the low-order byte only,
the low-order word (16-bits) only, or the whole longword.
The BASIC and MEM_REF microwords have a 1-bit L field. If the L-bit = 0,
then the GPR writes are longword. When the L-bit = 1, the length of the
GPR write is dictated by the data-length register in the I BOX,
G_S%DL_H<1:0>, as shown below.
G_S%DL_H<1:0>
-------------
00 = byte
01 = word
CVAX CPU CHIP DESIGN SPECIFICATION Page 102
EXECUTION (E) BOX
10 = longword
11 = quadword
The longword and quadword codes both cause a longword write to the GPR's.
The other 3 microword formats (CONSTANT, SHIFT, and SPECIAL) do not have
an L field. For these microwords, all GPR writes are longword.
The DL value which is used is the DL value that becomes valid at the same
time as the MIBs that specify the write.
3.1.3 Dual Ported Registers (T Registers) -
There are sixteen dual ported temporary registers, T[0:15], in the
register file. They may be read through the A port and written through
the W port simultaneously. T[15] is used to shadow the hardware SISR
registers; bit<31:16,0> are hardwired to 0.
3.1.4 Functional Summary -
This section lists the register file names and addresses and summarizes
the read/write operation of the register file as a function of the
microinstruction.
3.1.4.1 Register File Addressing -
The register file (and other "register-like" functions) are addressed from
the A-field and B-field of the microinstruction; see the "Control Fields
Summary". The register file decoder is set up as follows:
CVAX CPU CHIP DESIGN SPECIFICATION Page 103
EXECUTION (E) BOX
register Name A-decoder B-decoder
-------- ---- ----------------- ---------
GPR[0] 000000 --
GPR[1] 000001 --
GPR[2] 000010 --
GPR[3] 000011 --
GPR[4] 000100 --
GPR[5] 000101 --
GPR[6] 000110 --
GPR[7] 000111 --
GPR[8] 001000 --
GPR[9] 001001 --
GPR[10] 001010 --
GPR[11] 001011 --
GPR[12] AP 001100 --
GPR[13] FP 001101 --
GPR[14] SP 001110 --
GPR[15] PC 001111 --
T[0] KSP 010000 --
T[1] ESP 010001 --
T[2] SSP 010010 --
T[3] USP 010011 --
T[4] IS 010100 --
T[5] SAVEPSL 010101 --
T[6] SAVEPC 010110 --
T[7] AST.TRAP 010111 --
T[8] TXPAGE 011000 --
T[9] TMMGT 011001 --
T[10] SCBB 011010 --
T[11] PCBB 011011 --
T[12] P0BR 011100 --
T[13] P1BR 011101 --
T[14] SBR 011110 --
T[15] SISR 011111 --
W[0] 100000 0000
W[1] 100001 0001
W[2] 100010 0010
W[3] 100011 0011
W[4] 100100 0100
W[5] 100101 0101
W[6] 100110 0110
W[7] 100111 0111
NOTE: The PC is not located in the register file
Note that the remaining register addresses are used to address other logic
in the micromachine:
register A-decoder B-decoder
CVAX CPU CHIP DESIGN SPECIFICATION Page 104
EXECUTION (E) BOX
-------- ---------------- ---------
W[SN] 101000 or 111000 --
W[SN.PLUS.1] 101001 or 111001 --
GPR[RN] 101010 or 111010 --
PSL 101011 --
Q 101100 --
-- 101101 --
K[1] 101110 --
K[SEXT.N] 101111 --
W[SN] -- 1000
W[SN.PLUS.1] -- 1001
MID.BUFF -- 1010
K[DL] -- 1011
VA -- 1100
VA' -- 1101
VIBA -- 1110
-- -- 1111
NOTE: PC and MID.BUFF cannot be written using the DST field in the
microinstruction; PC is written using the MISC field. K[1], K[SEXT.N],
and K[DL] are read only pseudo-registers.
3.1.4.2 Source Control -
When the code for W[SN] or W[SN.PLUS.1] appears in the A-field or B-field,
SN or SN.PLUS.1 should be used to generate the W register address.
Similarly, when GPR[RN] appears in the A-field, RN should be used to
generate the GPR address.
The mapping between the SN codes and the W Registers is given in the table
below:
G_S%SN_H<2:0> W[SN] W[SN.PLUS.1]
============= ===== ============
000 0 1
010 2 3
100 7 0
101 4 5
110 1 2
111 3 4
3.1.4.3 Implementation Notes -
When implementing the A and B select decode logic, it will be necessary to
latch the decoded address as this may be needed on the subsequent write.
It must be possible to write two registers in the register file
simultaneously. This occurs when a write is being done using the DST
field in the microinstruction while the MISC field is WRITE.SC. In this
CVAX CPU CHIP DESIGN SPECIFICATION Page 105
EXECUTION (E) BOX
case, register W[7] is written in parallel with the actual destination
register. When W[7] is updated, the shadow SC is also updated.
3.1.4.4 Destination Control -
During the first part of a microcycle, register file data is placed on the
A_Bus and B_Bus, and the pipelined result from the previous microcyle is
written from the W_Bus. The selection of the destination register is
determined by the DST field in the microword. The write logic will choose
either the A port select, B port select, W[SN], or the bit bucket (ZILCH)
as the destination. In addition, W[7] may be written under the control of
the MISC field.
3.1.4.5 Timing Of Writes And Control Signals From The M BOX -
The M BOX passes two signals to the E BOX to control register file writes:
G_S%WSEL_UPDATE_H
This signal is used during PHI2 to load the write select (WSEL) latch with
the register to be written by the W_BUS. The write length is also latched
by this signal during PHI2.
G_S%REG_WRITE_H
This signal is used during PHI4 and PHI1 to enable the write.
3.1.5 W_Bus -
The W_Bus is the write path for the register file; it is the actual W-bit
lines of the register file. The W_BUS receives data from one of the
following sources: M BOX (via the G_S%MW_BUS_H), W_SPUR, and E BOX (ALU
output and Barrel Shifter output). It also has the capability to drive
data onto the W_SPUR and MW_BUS. It is a single-ended static bus driven
by push-pull drivers. The drivers have a built in latch which is updated
during G_C%PHI4_H. The drivers are located just below the shifter.
The M BOX writes data to the E BOX register file via the MW_BUS; and reads
data from the E BOX via the G_S%W_BUS_H.
3.1.6 Zero Extension -
Zero extension is carried out in the W_BUS drivers. Zero extension of a
byte causes bits G_S%W_BUS_H<31:8> to be cleared. Zero extension of a
word causes bits G_S%W_BUS_H<31:16> to be cleared. Zero extension of a
longword or quadword has no effect.
CVAX CPU CHIP DESIGN SPECIFICATION Page 106
EXECUTION (E) BOX
For the 3 microword formats (CONSTANT, SHIFT, and SPECIAL) which do not
have an L field, no zero extension is performed.
The two other microword formats (BASIC and MEM_REF) have a 1-bit L field.
If this L bit = 1, then zero extension is performed as dictated by the
data-length dependent register in the I BOX G_S%DL_H<1:0>.
G_S%DL_H<1:0>
-------------
00 = byte
01 = word
10 = longword
11 = quadword
The DL value which is used is the DL value that becomes valid at the same
time as the MIBs that specify the zero extention. When the L bit = 0, no
zero extension is carried out.
3.1.7 W_SPUR -
The W_Spur is a single-rail, 8-bit bidirectional bus which connects the
W_Bus to registers not in the data path. It passes through the Interrupt
Controller, I BOX, E BOX, M BOX, and BIU. When the W_Spur is driven by
the W Bus drivers, its data corresponds to the lower byte of the data
path, with one exception: When the PSL is written, various PSL bits are
moved onto the W_Spur. See the section titled PSL Distribution, for
further details. It can be read from, or written to and is accessed using
the MEM_REF microinstruction with FNC/MXPS selected. The MEM_REF.REG
field defines the register number which drives/is written from the W_Spur
in an MXPS internal operation as shown below:
MEM_REF.REG Register Selection Access Section
----------- ------------------ ------ -------
INT.ID highest interrupt in bits<4:0> ro INT_CTL
OPCODE opcode register in bits<7:0> ro IBOX
SPEC.RN specifier in bits<7:4>, RN in <3:0> ro/rw IBOX
ATDL AT in bits<3:2>, DL in <1:0> ro IBOX
HSIR HSIR in bits <7:0> rw IBOX
ICCS ICCS<6> in bit<6> rw IBOX
EBOX.STATE STATE<5:0> in bits<5:0> ro EBOX
EBOX.CCS RESTART, ALU CC's in bits<7,3:0> ro EBOX
RLOG.STACK RLOG[0]<7:0> in bits<7:0> ro EBOX
MAPEN MAPEN in bit<0> rw MBOX
MMGT.STATUS MMGT.STATUS in bits<2:0> wo MBOX
PROBE.MODE alternate probe mode in bits<1:0> wo MBOX
MSER.HIGH memory system error register rw BIU
MSER.LOW MSER low bits rw BIU
CADR cache disable register rw BIU
The Shadow_SC is also attached to the W_Spur. It is written using the
MISC/WRITE.SC function in all microinstructions.
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Spur reads have bits<31:8> = 0, and unused bits on the spur will be read
as 1.
NOTE: Doing a MISC/WRITE.SC in parallel with any MEM_REF.MXPS function
will result in the MXPS data being stored in the Shadow_SC. See the PSL
distribution section for further details on the use of the W_SPUR.
3.1.8 Microcode Restrictions -
1. W_SPUR - A W_SPUR read cannot immediately follow a W_SPUR write.
This restriction applies even when the W_SPUR write is implicit
as when W<7> (SC) is updated. (The shadow SC is written via the
spur.)
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3.2 Program Counter (PC Register)
The PC Logic function consists of the PC register, the PC adder, and the
BPC register.
3.2.1 PC Register -
This longword register is used to hold the Program Counter. It is read as
[PC] (see Register File section for addressing details) and written via
two MISC fields. Whenever it is not addressed as a destination, the PC is
loaded from the PC adder which adds G_S%DELTA_PC_H<2:0>, a value furnished
by the I BOX, to the previous value of the PC.
The PC is readable as [GRN] where RN=15, or as GPR[15]. However, the PC
can only be written under control of the MISC and MISC2 fields as shown
below. An explicit write of PC (i.e, a microcode write to register
GPR[15] or GPR[RN] when RN = 15) is ignored.
MISC Operation
---- ------------------
16 LOAD.V&PC
18 IF.BCOND.LOAD.V&PC.TRAP
19 IF.BCOND.LOAD.V&PC
MISC2 Operation
----- ------------------
0 NOP
1 LOAD.PC.FROM.BPC
The first function, MISC/LOAD.V&PC, unconditionally updates the PC and
VIBA from G_S%W_BUS_H and flushes the instruction pipeline.
MISC/IF.BCOND.LOAD.V&PC and MISC/IF.BCOND.LOAD.V&PC.TRAP conditionally
update the PC and VIBA (and flushes the instruction pipeline) from
G_S%W_BUS_H if the instruction dependent branch condition is met
(EBT_PH%BCOND_MET_L asserted). If the branch condition fails, the PC is
not loaded from the G_S%W_BUS_H. Loading the PC in this manner is enabled
by the signal G_S%LD_VIBA_AND_PC_H. G_S%LD_VIBA_AND_PC_H is derived as
shown below:
G_S%LD_VIBA_AND_PC_H = MISC/LOAD.V&PC OR ((MISC/IF.BCOND.LOAD.V&PC OR
MISC/IF.BCOND.LOAD.V&PC.TRAP) AND NOT EBT_PH%BCOND_MET_L)
The PC can also be loaded from the BPC using the MISC2/LOAD.PC.FROM.BPC
field of the SPECIAL microinstruction as shown above. Note that VIBA is
not changed, and the instruction pipeline is not flushed.
The lower two bits of the PC register, G_S%NEW_IB_PTR_H<1:0>, are sent to
the I BOX to be loaded into the IB-PTR if a conditional or unconditional
LOAD.V&PC is executed.
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3.2.2 PC Adder -
The PC adder is used for incrementing the PC as macroinstructions are
parsed. Its inputs are the 32-bit PC register, and the 3-bit value, delta
PC, which can have the values 0, 1, 2, 3, 4, 5, or 6. G_S%DELTA_PC_H<2:0>
is provided by the I BOX during instruction stream processing. Whenever
there is nothing to add to the PC, G_S%DELTA_PC_H<2:0> is set to zero by
the I BOX.
The PC adder value is loaded into the PC register during PHI4 if
G_PH%STALL_L is not asserted and the PC is not being loaded from the W_Bus
or the BPC during this cycle.
3.2.3 BPC Register -
This longword register is used to snapshot the PC during G_S%IID_LD_H in
case the instruction faults or an interrupt is to be taken. The BPC
register is not loaded during an IID of the second byte of a 2-byte
opcode.
3.2.4 Microcode Restrictions -
1. For PC writes of other than data length LONG, the unwritten
portion of PC is unpredictable.
2. The PC cannot be written via GPR[RN] or GPR[15].
3. The PC cannot be written via A = PC and DST = DST.A.
4. In the SPECIAL microinstruction, the PC cannot be written using
the MISC2 and MISC field simultaneously.
5. The PC cannot be written explicitly in one cycle and then read in
the next cycle.
6. The PC cannot be written during a read from memory.
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3.3 Constant Generator
The Constant Generator is used to create constants, and handle sign
extension on the E_PH%A_BUS_H and the G_PH%B_BUS_H busses.
3.3.1 Constants -
3.3.1.1 KDL Constants -
The Constant Generator can generate constants on the G_PH%B_BUS_H bus
based solely on the value of G_S%DL_H<1:0> when MKDL is selected as the
B_Bus address (B-field = MKDL) as shown below. Forced Long has no effect
on the constants.
G_S%DL_H<1:0> Constant Value
------------- -----------------------
00 = byte G_PH%B_BUS_H<31:0> = 1
01 = word = 2
10 = longword = 4
11 = quadword = 8
3.3.1.2 SHIFT Microinstruction Constants -
Some SHIFT microinstructions require that the A_Bus or B_Bus is set to #0.
This bus zeroing is done in the SHIFTER hardware block. See the section
entitled "Shifter" for more details.
3.3.1.3 CONSTANT Microinstruction Constants -
The constant generator creates a 32-bit B_Bus constant from ten bits in
the microinstruction during all CONSTANT microinstructions. The eight bit
CONSTANT.BYTE field supplies the value of the constant. The two bit
CONSTANT.POS field specifies in which byte the constant is to be placed.
The constant is always zero filled.
G_PH%B_BUS_H<31:0> Value
CONSTANT.POS <31:24> <23:16> <15:8> <7:0>
------------ ------------- ------------- ------------- -------------
00 ZERO ZERO ZERO CONSTANT.BYTE
01 ZERO ZERO CONSTANT.BYTE ZERO
10 ZERO CONSTANT.BYTE ZERO ZERO
11 CONSTANT.BYTE ZERO ZERO ZERO
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3.3.1.4 A_Bus Constants -
Constants which are provided by the KMUX for use on E_PH%A_BUS_H are
defined below.
Reg Addr(Reg) Constant Value
------------- -------------------------------------------------
A = 2E A_Bus = K1 = 1
A = 2F A_Bus = K[SEXT.N] = 0 (00000000#16) if alu.n = 0
-1 (11111111#16) if alu.n = 1
3.3.2 Microcode Restrictions -
No known restrictions.
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3.4 Shift Counter (SC)
The SC is a 32-bit register located in the triple ported register file.
It may be addressed as working register W[7], or via the MISC field in the
microinstruction as the SC. Whenever W[7] is loaded, the lower six bits
are shadowed to the Shadow_SC on the W_SPUR for use in microprogram
branching or controlling of the shifter.
There is a latency associated with the value in the Shadow_SC as follows:
assume VALUE 1 is in SC
;-------------------------------;
[SC]<--[Value 2] ; Case here is on Value 1
;-------------------------------;
[SC]<--[Value 3] ; Case here is on Value 1
;-------------------------------;
[SC]<--[Value 4] ; Case here is on Value 2
;-------------------------------;
... ; Case here is on Value 3
;-------------------------------;
... ; Case here is on Value 4
The SHIFT control operates with the same latency.
3.4.1 Functional Summary -
The SC may be addressed as W[7] and as such may be read/written as a
working register would be. When addressed as W[7], the SC is read onto
the A_Bus or B_Bus, and written from the W_Bus, as required. The SC can
also be written in parallel with other registers through the MISC/WRITE.SC
function. (See Register File Section for addressing details.)
3.4.2 UTest And The SC -
A shadow copy of the lower 6 bits of the SC register, Shadow_SC<5:0>, is
testable via the Microtest Bus, as specified by the BCS field, as follows:
BCS Branch Command
----- --------------
SC2-0 SC<2:0> case
SC5-3 SC<5:3> case
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3.4.3 Microcode Restrictions -
1. Shadow_SC - A W_SPUR read cannot immediately follow a W_SPUR
write.
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3.5 Shifter
The Shifter is a full 64-bit in, 32-bit out shift network. It is used for
shift operations as specified in the macro instruction. It is also used
by microcode for general purpose use, to concatenate data, etc.
Its inputs are the A_Bus and B_Bus, with the A_Bus being more significant.
Its output is the W_Bus. It can do 0 to 32 bit right shifts, where a
zero-bit shift selects the B_Bus. It can also do a pseudo 0 to 31 bit
left shift, where a zero-bit shift selects the A_Bus, by performing a
right shift of 31 to 0 bits, respectively. Note that the explicit shift
values (the SHIFT.VAL field in the microinstruction, or the Shadow_SC
register) are interpreted modulo 32. Therefore, it is impossible to
generate a 32-bit right shift except by the pseudo-left shift mechanism
(32-SV).
The shift operation to be done is specified by the SHIFT microinstruction.
If MISC/SHIFT.DL is asserted, the shifter executes left shifts only, as
shown below:
G_S%DL_H<1:0> Shift Value
------------- -----------
00 (byte) 0 Left
01 (word) 1 Left
10 (longword) 2 Left
11 (quadword) 3 Left
If MISC/SHIFT.DL is not asserted, the shift operation is specified by
either SV or 32-SV, depending on SHIFT.DIR. When SV = 0, however, the low
five bits of the Shadow_SC are used in place of SV.
The shifter can effectively zero out the A_BUS when the shift direction is
right and the DST field is DST.A. The B_BUS is effectively zeroed when
the shift direction is left and the DST field is DST.B.
3.5.1 Functional Summary - See the "Control Fields Summary" section.
Dir Dst A_Bus B_Bus Dest Dir Shift Reg if SV=0
--- ----- ----- ----- ---- ----- ----- -----------
A.B..ZILCH...R(SC) R DST.Z A B none right SV Shadow_SC
A.B..ZILCH...L(SC) L DST.Z A B none left 32-SV Shadow_SC
0.B..A...R(SC) R DST.A #0 B A right SV Shadow_SC
A.B..A...L(SC) L DST.A A B A left 32-SV Shadow_SC
A.B..W0...R(SC) R DST.W[SN] A B W[SN] right SV Shadow_SC
A.B..W0...L(SC) L DST.W[SN] A B W[SN] left 32-SV Shadow_SC
A.B..B...R(SC) R DST.B A B B right SV Shadow_SC
A.0..B...L(SC) L DST.B A #0 B left 32-SV Shadow_SC
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3.5.1.1 Implementation Note -
The shifter doesn't actually zero the E_PH%A_BUS_H or G_PH%B_BUS_H bus but
the output of the shifter is identical to that which would result if the
appropriate input bus had been zeroed.
The shifter has been designed to begin evaluating on G_S%PHI3_H.
3.5.2 Raw SHFT Condition Codes -
In addition to the shifted data generated by the operation specified by
the SHIFT microinstruction, the Shifter also generates a set of condition
codes based on the results of that operation. These condition codes will
be referred to as the RAW_SHFT condition codes to avoid confusion with the
ALU Condition Code bits located in the ALU.CC register. These condition
codes are defined as follows:
1. N bit (SHIFTER) - The sign bit of the result, literally the most
significant bit of the result.
2. Z bit (SHIFTER) - The zero condition bit of the result. This is
true if the result is exactly zero.
The C bit and V bit are the carry and overflow conditions, but they are
always zero for shift operation.
The condition codes are derived as shown below:
N bit (SHIFTER) = E__PH%ALU__SHFT__H<31>
Z bit (SHIFTER) = E__PH%ALU__SHFT__H<31:0> EQL 0
V and C bits (SHIFTER) = 0
These RAW_SHFT condition codes may be loaded into the ALU CC Register.
Refer to the section entitled "Condition Code Logic" for more details.
The E_PH%ALU_SHFT_H<31:0> bus is shared by the SHIFTER and the ALU. Its
operation is described in the ALU Functional Summary Section.
3.5.3 Microcode Restrictions -
1. When MISC/SHIFT.DL is asserted, the SHIFT.DR field must specify a
left shift.
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3.6 Arithmetic Logic Unit (ALU)
The ALU is a general purpose Arithmetic Logic Unit, used for microcode
specified operations. The ALU operates upon the data presented over the
A_Bus and B_Bus and puts its results on the W_Bus, as specified by the
microinstruction.
3.6.1 Functional Summary -
The ALU data path consists of a full 32-bit block capable of addition or
any combination of A, .NOT.A, B, and .NOT.B with the carry input
programmable as well as any logical function of A and B. It also includes
a one bit left/right shifter for multiply and divide operations.
The ALU always generates 32 bits of valid data; the results are not data
length dependent.
The ALU also generates condition codes based on the results of its
operation. These Raw ALU CC's are data length dependent, as specified by
the microinstruction (based on the DL register or forced to LONG as
specified by the L-bit in the microword).
The ALU is controlled by the microinstruction. In the BASIC and CONSTANT
microinstructions, specific fields specify the function the ALU performs.
During MEM_REF write microinstructions, the ALU function is always PASS.A.
When a MEM_REF read of an MXPR register (MEMREF/MXPR/READ) occurs the ALU
should be configured to PASS.B. All other cases are don't cares. The
result of the ALU is driven onto the G_S%W_BUS_H via E_PH%ALU_SHFT_H.
E_PH%ALU_SHFT_H is a result bus shared by the ALU and the SHIFTER.
E_PH%ALU_SHFT_H is driven by the ALU for all microinstructions except
SHIFT; it is driven by the SHIFTER during SHIFT microinstructions. The
G_S%W_BUS_H is driven with the data on E_PH%ALU_SHFT_H during BASIC,
CONSTANT, SHIFT, and MEM_REF write and MXPR read microinstructions.
During execution of a SHIFT microinstruction the G_S%W_BUS_H is driven
with data on E_PH%ALU_SHFT_H from the SHIFTER, not the ALU.
For the following functional description, the notation is as follows:
o ALU_SUM<n> is the nth order bit of the generated ALU result.
o EAD_PH%ALU_CY_L<n> is the nth order carry bit from the ALU data
path. Note that it is the carry bit INTO the nth bit slice.
(This is consistent with the full adder description S(i) =
A(i).XOR.B(i).XOR.C(i) ). Under this convention, the low order
carry input to the ALU would actually be EAD_PH%ALU_CY_L<0> and
the high order carry out of the ALU would be EAD_PH%ALU_CY_L<32>.
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3.6.1.1 ALU Implementation Notes -
The ALU is implemented using a 32-bit carry chain with P & G (Propagate
and Generate) Logic. The carry chain is implemented in negative logic,
that is, it is precharged to a logic high level and then conditionally
discharged according to the P and G terms. The propagate term propagates
the carry from the previous bit of the carry chain while the generate term
generates a carry.
The P and G terms are generated as a function of the data input from
E_PH%A_BUS_H<31:0> and G_PH%B_BUS_H<31:0>, and the decoded micro-opcode as
shown below.
EAD_S%ALU_PROP_H<N> = (E_S%P_FCT_H<3>.AND.E_PH%A_BUS_H<N>.AND.G_PH%B_BUS_H<N>).OR.
(E_S%P_FCT_H<2>.AND.E_PH%A_BUS_H<N>.AND.G_PH%B_BUS_L<N>).OR.
(E_S%P_FCT_H<1>.AND.E_PH%A_BUS_L<N>.AND.G_PH%B_BUS_H<N>).OR.
(E_S%P_FCT_H<0>.AND.E_PH%A_BUS_L<N>.AND.G_PH%B_BUS_L<N>)
EAD_S%ALU_GEN_H<N> = (E_S%P_FCT_H<3>.AND.E_PH%A_BUS_H<N>.AND.G_PH%B_BUS_H<N>).OR.
(E_S%G_FCT_H<2>.AND.E_PH%A_BUS_H<N>.AND.G_PH%B_BUS_L<N>).OR.
(E_S%G_FCT_H<1>.AND.E_PH%A_BUS_L<N>.AND.G_PH%B_BUS_H<N>)
The ALU output is then determined by the equation:
ALU_SUM_H<N> = (EAD_S%ALU_PROP_H<N>).XNOR.(EAD_PH%ALU_CY_L<N>)
Where the terms E_S%P_FCT_H<N>, E_S%G_FCT_H<N>, and the carry in
(E_S%ALU_CIN_H<0>) are derived from the opcode and the ALU operation
specified in the microinstruction as shown in the table below. Note that
E_S%G_FCT_H<0> is always 0 for all implemented ALU functions. The value
of ALU_SUM_H<N> is the output of the ALU before the one-bit shifter.
FOR LOGIC FUNCTIONS:
E_S%P_FCT_H<N> E_S%G_FCT_H<N>
<3> <2> <1> <0> <3> <2> <1> ALU_CY_H<0> ALU_SUM_H<31:0> Description
--- --- --- --- --- --- --- ----------- --------------- -------------------------------------------------
1 0 0 0 0 0 0 0 A.AND.B W<31:0> <-- A<31:0> and B<31:0>
0 1 0 0 0 0 0 0 A.AND.NOT.B W<31:0> <-- A<31:0> and ~B<31:0>
0 1 1 0 0 0 0 0 A.XOR.B W<31:0> <-- A<31:0> xor B<31:0>
1 1 1 0 0 0 0 0 A.OR.B W<31:0> <-- A<31:0> or B<31:0>
0 1 0 1 0 0 0 0 .NOT.B W<31:0> <-- ~B<31:0> (one's complement of B)
1 1 0 0 0 0 0 0 PASS.A W<31:0> <-- A<31:0>
1 0 1 0 0 0 0 0 PASS.B W<31:0> <-- B<31:0>
FOR ARITHMETIC FUNCTIONS:
E_S%P_FCT_H<N> E_S%G_FCT_H<N>
<3> <2> <1> <0> <3> <2> <1> ALU_CY_H<0> ALU_SUM_H<31:0> Description
--- --- --- --- --- --- --- ----------- --------------- -------------------------------------------------
1 1 0 0 0 0 0 1 A.PLUS.1 W<31:0> <-- A<31:0> plus 1
0 0 1 1 1 1 0 0 A.MINUS.1 W<31:0> <-- A<31:0> minus 1
0 1 1 0 1 0 0 1 A.PLUS.B.PLUS.1 W<31:0> <-- A<31:0> plus B<31:0> plus 1
0 1 1 0 1 0 0 0 A.PLUS.B W<31:0> <-- A<31:0> plus B<31:0>
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0 1 1 0 1 0 0 PSL.C A.PLUS.B.PLUS.(PSL.C) W<31:0> <-- A<31:0> plus B<31:0> plus PSL.CC<C>
1 0 0 1 0 1 0 1 A.MINUS.B W<31:0> <-- A<31:0> minus B<31:0>
1 0 0 1 0 1 0 .NOT.PSL.C A.MINUS.B.MINUS.(PSL.C) W<31:0> <-- A<31:0> minus B<31:0> minus PSL.CC<C>
1 0 0 1 0 0 1 1 B.MINUS.A W<31:0> <-- B<31:0> minus A<31:0>
0 1 0 1 0 0 0 1 .NEG.B W<31:0> <-- -B<31:0> (two's complement of B)
When using the CONSTANT microinstruction the constants are placed on the
G_PH%B_BUS_H. Thus, the above table is valid for all ALU operations
resulting from the CONSTANT microinstruction.
3.6.1.1.1 Instruction Decode For The ALU -
Instruction decode is performed by a PLA with 7 output bits. A mux at the
PLA output is controlled by whether an SMUL or UDIV or neither is
occuring. SMUL and UDIV are decoded outside of the PLA so that the mux
can be set up before the PLA output is valid. The control mux is a
two-way 8-bit mux with the 7 PLA output bits and the ALU carry in on one
leg and the code corresponding to A.PLUS.B on the other. The ALU carry in
bit is a function of the ALU operation and the PSL.C bit. This logic
exists outside the PLA as speed is critical.
The multiplexer always passes the PLA output except for SMUL.STEP and
UDIV.STEP. For each of these steps, the multiplexer will pass either the
PLA output or the hardwired A.PLUS.B, depending on the state of the ALU.C
(E_S%UDIV_ALU_C_H for UDIV) or Q_REG<0> (E_S%Q0_BUF_L for SMUL).
3.6.1.2 SMUL Step Definition -
The signed multiplication step is used to implement the sequential
add-shift multiplication algorithm. It allows for multiplication of two
operands of length byte, word, or longword. The smul step utilizes the
ALU, the single-bit left/right shifter located at the bottom of the ALU,
the Q register, and the microcode working registers. The operation and
description of the smul step is given below. Consult the CVAX Microcode
for a more detailed explanation.
Operation: For Ra <- Ra.SMULS.Rb (In the microcode Ra=W[1] and Rb=W[0])
o If Q_Reg<0> = 1 (E_S%Q0_BUF_L = 0)
THEN ALU_OUT<31:0> <-- Ra + Rb (Partial Product + Multiplicand)
ELSE ALU_OUT<31:0> <-- Ra (Partial Product)
o G_S%W_BUS_H<31:0> <-- (P<31>.XOR.ALU_CY<32>)'ALU_OUT<31:1>
o Q_REG<31:0> <-- ALU_OUT<0>'Q_REG<31:1>
NOTE: ALU_OUT is the output of the ALU proper, not of the ALU +
single-bit shifter. ALU
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Description: The lsb of the Q register is tested for a 0 or 1. If
Q_reg<0> = 0, then the partial product is passed through the
ALU unmodified. If Q_reg<0> = 1, then partial product and
the multiplicand are added together. Then the output of the
ALU and the Q register is shifted right one bit. The shift
into the msb of W_BUS (via E_PH%ALU_SHFT_H) is the
exclusive-or of the ALU's output sign and the arithmetic
overflow out of the ALU (arithmetic overflow is the
exclusive-or of the carry-in and carry-out of the msb). The
shift into the msb of Q_REG comes from ALU_OUT<0>.
3.6.1.3 UDIV Step Definition -
The unsigned division step is used to implement the sequential
shift-subtract/add non-restoring division algorithm. Non-restoring
division uses the fact that:
2 * (Partial Remainder - Divisor + Divisor) - Divisor =
2 * (Partial Remainder - Divisor) + Divisor
That is, after a failed attempt at division (- Divisor), instead of
restoring the Partial Remainder by adding the divisor back in (+
Divisior), the non-restored Partial Remainder is rotated and division is
tried again by adding the Divisor.
The udiv step utilizes the ALU, the single-bit left/right shifter located
on the bottom of the ALU, the Q register, and the microcode working
registers. The operation and description of the udiv step is given below.
Consult the CVAX Microcode for a more detailed explanation.
Operation: For Ra <- Ra.UDIV.Rb (In the microcode Ra=W[3] and Rb=W[0])
This operation will result with the Q register containing the quotient and
Ra (W[3]) containing the remainder.
o If ALU.C = 1 (E_S%UDIV_ALU_C_H = 1)
THEN ALU_OUT <-- Ra - Rb (Partial Remainder/Quotient - Divisor)
ELSE ALU_OUT <-- Ra + Rb (Partial Remainder/Quotient + Divisor)
o G_S%W_BUS_H<31:0> <-- ALU_OUT<30:0>'Q_REG<31>
o Q_REG<31:0> <-- Q_REG<30:0>'ALU_OUT_L<31>
o ALU.C <-- ALU_CY_OUT<31>, as in normal instruction
NOTE: ALU_OUT is the output of the ALU proper, not of the ALU +
single-bit shifter.
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Description: ALU.N is tested for a 0 or 1. If ALU.N = 0, then Rb is
subtracted from Ra. If ALU.N = 1, then the Ra and Rb are
added together. The output of the ALU is then rotated to the
left one-bit and driven onto the W_BUS via G_PH%ALU_SHFT_H,
with W_BUS<0> being driven by Q_REG<31>. Additionally, the
Q_Register is rotated left one-bit with the complement of the
bit shifted out of the ALU result becoming Q_REG<0>. The bit
shifted out of the ALU result also becomes the new ALU.N
condition flag.
3.6.1.3.1 UDIV Step Issues -
The unsigned divide algorithm in microcode requires that the remainder be
shifted one bit to the right after the final UDIV.STEP. This final step
is done by the microcode and no additional hardware assist is needed.
3.6.1.4 Raw ALU Condition Codes -
In addition to the results generated by the operation specified by the
microinstruction, the ALU also generates a set of condition codes based on
the results of that operation. These condition codes will be referred to
as the RAW_ALU condition codes to avoid confusion with the ALU Condition
Code bits located in the ALU.CC register. These condition codes are
defined as follows:
1. N bit (ALU) - The sign bit of the result, literally the most
significant bit of the result.
2. Z bit (ALU) - The zero condition bit of the result. This is true
if the result is exactly zero.
3. C bit (ALU) - The carry-out of the operation. This only has
meaning during ADD and SUBTRACT operations. It is exactly zero
for PASS and all logical functions.
4. V bit (ALU) - The integer overflow bit. This bit indicates an
integer overflow of the operation, including two's complement
operations. It is defined as the exclusive-OR of the carry-in to
the last stage and the carry-out of the last stage.
These conditions are dependent on the microinstruction data length, as
follows (where CY = carry in):
o Length = USE.DL, DL = BYTE:
N bit (ALU) = E_PH%ALU_SHFT_H<7>
Z bit (ALU) = E_PH%ALU_SHFT_H<7:0> EQL 0
V bit (ALU) = (ALU_CY<7>).XOR.(ALU_CY<8>)
C bit (ALU) = ALU_CY<8>
CVAX CPU CHIP DESIGN SPECIFICATION Page 121
EXECUTION (E) BOX
o Length = USE.DL, DL = WORD:
N bit (ALU) = E_PH%ALU_SHFT_H<15>
Z bit (ALU) = E_PH%ALU_SHFT_H<15:0> EQL 0
V bit (ALU) = (ALU_CY<15>).XOR.(ALU_CY<16>)
C bit (ALU) = ALU_CY<16>
o Length = USE.DL, DL = LONG or QUAD; or Length = FORCED.LONG
N bit (ALU) = E_PH%ALU_SHFT_H<31>
Z bit (ALU) = E_PH%ALU_SHFT_H<31:0> EQL 0
V bit (ALU) = (ALU_CY<31>).XOR.(ALU_CY<32>)
C bit (ALU) = ALU_CY<32>
Note: For all logical and PASS operations, the C and V bits for the ALU
will always be zero.
These RAW_ALU condition codes may be loaded into the ALU CC Register.
Refer to the section entitled "Condition Code Logic" for more details.
3.6.2 Microcode Restrictions -
No known restrictions.
CVAX CPU CHIP DESIGN SPECIFICATION Page 122
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3.7 Multiplier Quotient Register
The multiplier quotient (Q) register is a 32-bit left/right shift register
which is used in combination with the ALU shifter to implement efficient
multiply and divide operations. The Q register can be read onto the A_Bus
and written from the W_Bus as register [Q].
3.7.1 Functional Summary -
The Q register is used as a shift register only during multiply and divide
operations via the BASIC.FNC field in the microword.
For a detailed description of the Q register operation during
muliplication and division refer to the sections on the UDIV and SMUL
step.
BASIC.FNC Q-Register Operation
-------------- --------------------------------------
SMUL.STEP = 0D Q_Reg<30:0> <-- Q_Reg<31:1>
Q_Reg<31> <-- E_S%ALU_SUM_H<0>
UDIV.STEP = 06 Q_Reg<31:1> <-- Q_Reg<30:0>
Q_Reg<0> <-- .NOT.E_S%ALU_SUM_H<31>
3.7.2 Microcode Restrictions -
1. The Q Register cannot be read in the cycle immediately following
a Q Register write.
2. The Q Register cannot be read in the cycle immediately following
an SMUL or UDIV operation.
3. An SMUL operation cannot immediately follow a Q Register write.
(Note: No such restriction applies to UDIV.)
4. The Q Register cannot be written during a read from memory.
CVAX CPU CHIP DESIGN SPECIFICATION Page 123
EXECUTION (E) BOX
3.8 PSL Logic
The user visible PSL is maintained in the E BOX data path. It is a 32-bit
register which can be read onto the A_Bus using the A field in the
microword, or written via the DST.A when A = 2B (PSL). Additionally,
PSL<30,3:0> may be selectively modified.
Shown below is the layout of the user visible PSL. Note that PSL<3:0> are
the PSL Condition Code bits which are generated in the CC Logic. Refer to
the section called "Condition Code Logic" in this spec for further details
on the PSL CC Bits.
3 3 2 2 2 2 2 2 2 2 2 2 1 1
1 0 9 8 7 6 5 4 3 2 1 0 6 5 8 7 6 5 4 3 2 1 0
+-+-+---+-+-+---+---+-+---------+---------------+-+-+-+-+-+-+-+-+
| | | |F| | | |M| | | | | | | | | | |
|C|T| |P|I|CUR|PRV|B| | |D|F|I| | | | | | :PSL
|M|P|MBZ|D|S|MOD|MOD|Z| IPL | MBZ |V|U|V|T|N|Z|V|C|
+-+-+---+-+-+---+---+-+---------+---------------+-+-+-+-+-+-+-+-+
3.8.1 I BOX Usage Of The PSL And Trace Logic -
The TP (Trace Pending, PSL<30>) and T (Trace, PSL<4>) bits are copied to
the I BOX when the PSL is written from the W_BUS. In addition, the I BOX
sometimes transfers its copy of the T bit into its copy of the TP bit.
When this occurs, the I BOX asserts a signal (G_S%COPY_TRACE_H), which
causes the T bit to be written into the TP bit of the user visible PSL.
Additionally, the I BOX uses the FPD bit in the PSL, PSL<27>. This bit is
not modified in the I BOX.
3.8.2 M BOX, INT_CTRL And BIU Usage Of PSL -
The M BOX keeps a local copy of PSL<26:24>. This copy is updated from
G_S%W_BUS_H<26:24> when the PSL is written from the W_BUS. The E BOX
signals a load of the PSL from the W_BUS by asserting a signal,
G_S%LOAD_PSL_H.
Similarly, the Interrupt Controller uses PSL<20:16> and the BIU uses
PSL<6> (FU bit), and neither modifies them.
3.8.3 PSL Distribution -
PSL<30,6,27,20:16> are all available on the W_SPUR<7:0> when the signal
G_S%LOAD_PSL_H is asserted. PSL<4>, used by the IBOX, is buffered from
G_S%W_BUS_H<4> and sent to the IBOX via a dedicated line -
G_S%PSL_T_BIT_H.
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3.8.4 PSL<3:0> - Condition Code Bits -
See section "Condition Code Logic."
3.8.5 Microcode Restrictions -
1. The PSL cannot be written (A field = PSL, DST field = DST.A) at
the same time the PSL condition code bits are being updated
(LOAD.PSL.CC or LOAD.ALU.CC&PSL.CC).
2. A write to PSL is not allowed during IID (TP load conflict).
3. The PSL cannot be written during a read from memory.
4. The PSL cannot be read immediately following a PSL write.
CVAX CPU CHIP DESIGN SPECIFICATION Page 125
EXECUTION (E) BOX
3.9 Condition Code Logic
On each data path operation, new condition codes, RAW_ALU CC's or RAW_SHFT
CC's, are generated within the E BOX. These raw condition codes are
generated from the result of the ALU or the SHIFTER depending upon the
type of microinstruction being executed. In addition, condition codes are
sent from the Floating Point Chip (FPU), FPU.NZV0, which are used during
MEMREF FPA Data transfers.
The RAW_CVAX condition codes are generated from the RAW_ALU CC's, the
RAW_SHFT CC's, and the FPU CC's based on the microinstruction type and the
data length (G_S%DL_H<1:0>) as follows:
o SHIFT DECODE: MIB<40:38> = 010
(SHIFT instruction)
RAW_CVAX.NZVC <- RAW_SHFT.NZ00
--------------------------------------------
RAW_CVAX.N <- E_PH%ALU_SHFT_H<31>
RAW_CVAX.Z <- E_PH%ALU_SHFT_H<31:0> EQL 0
RAW_CVAX.V <- 0
RAW_CVAX.C <- 0
o MEM_REF.FPA.DATA DECODE: MIB<40:38> = 001 AND MIB<37:33> = 11000
(MEM_REF instruction) (FPA.DATA function)
RAW_CVAX.NZVC <- FPU.NZV0
------------------------------
RAW_CVAX.N <- G_S%FPU_CCN_H
RAW_CVAX.Z <- G_S%FPU_CCZ_H
RAW_CVAX.V <- G_S%FPU_CCV_H
RAW_CVAX.C <- 0
For all instruction types other than SHIFT and MEM_REF.FPA.DATA, the
RAW_CVAX Condition Codes are selected as BYTE, WORD, or LONGWORD as shown
below:
o SPECIAL DECODE: MIB<40:38> = 000
CONSTANT DECODE: MIB<40:38> = 1XX
BASIC (L=FORCED_LONG)
BASIC (L=USE_DL, DL=LONG or QUAD)
MEM_REF (not FPA.DATA and L=FORCED_LONG)
MEM_REF (not FPA.DATA and L=USE_DL, DL=LONG or QUAD)
RAW_CVAX.NZVC <- CVAX_ALU.NZVC (LONGWORD)
-------------------------------------------
RAW_CVAX.N <- E_S%ALU_SHFT_H<31>
RAW_CVAX.Z <- E_S%ALU_SHFT_H<31:0> EQL 0
RAW_CVAX.V <- E_S%ALU_LONG_V_H
RAW_CVAX.C <- E_S%ALU_LONG_C_H
o BASIC (L=USE_DL, DL=WORD)
MEM_REF (not FPA.DATA and L=USE_DL, DL=WORD)
CVAX CPU CHIP DESIGN SPECIFICATION Page 126
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RAW_CVAX.NZVC <- CVAX_ALU.NZVC (WORD)
-------------------------------------------
RAW_CVAX.N <- E_S%ALU_SHFT_H<15>
RAW_CVAX.Z <- E_S%ALU_SHFT_H<15:0> EQL 0
RAW_CVAX.V <- E_S%ALU_WORD_V_H
RAW_CVAX.C <- E_S%ALU_WORD_C_H
o BASIC (L=USE_DL, DL=BYTE)
MEM_REF (not FPA.DATA and L=USE_DL, DL=BYTE)
RAW_CVAX.NZVC <- CVAX_ALU.NZVC (BYTE)
-------------------------------------------
RAW_CVAX.N <- E_S%ALU_SHFT_H<7>
RAW_CVAX.Z <- E_S%ALU_SHFT_H<7:0> EQL 0
RAW_CVAX.V <- E_S%ALU_BYTE_V_H
RAW_CVAX.C <- E_S%ALU_BYTE_C_H
These RAW_CVAX condition codes can be loaded into the ALU CC Register or
into the PSL CC Register via the Condition Code Map.
3.9.1 PSL CC Register, PSL<3:0> -
This four bit register latches the architecturally-specified condition
codes for use on subsequent cycles. The PSL CC Register can be loaded
from one of two sources, depending on the microword. It can be loaded
with RAW_CVAX.NZVC via the condition code map, or with G_S%W_BUS_H<3:0>
when the PSL is written from the W_BUS.
3.9.1.1 Loading Of The PSL CC Register -
The PSL CC register is loaded under the control of the CC field in the
microinstruction.
CC Function
-- ----------------------------------------------
00 NOP
01 NOP
10 Load PSL CCs from RAW_CVAX.NZVC via the CC Map
11 Load PSL CCs from RAW_CVAX.NZVC via the CC Map
The operation of the Z bit is changed when MISC = OLD.Z. In this case,
the new Z bit is SET only if the current Z data being supplied and the old
Z bit are both SET.
If G_PH%STALL_L is asserted, the load will be inhibited.
The PSL.C bit is buffered (E_S%PSL_C_H) and sent to the ALU Control PLA.
It is used as the ALU carry in on certain operations. Additionally, the
PSL condition code bits are used by the Branch Test Logic.
CVAX CPU CHIP DESIGN SPECIFICATION Page 127
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The PSL CC register can be read onto bits<3:0> of the A_Bus as [PSL].
3.9.1.2 PSL Condition Code Map -
The map logic takes the RAW_CVAX.NZVC, the C bit of the PSL, G_S%IID_LD_H
from the I BOX, and the MISC field as input and generates the PSL CC's as
output.
There are four different mapping functions called iiip, jizj, iiii, and
iiij. Each of these mapping functions (called MAP_CODEs) is defined in
the following table.
MAP_CODE Map Function
---------------- ---------------------------------------------
MISC = 1E (iiii) PSL.NZVC <-- RAW_CVAX.NZVC
MISC = 1F (iiij) PSL.NZV <-- RAW_CVAX.NZV,
PSL.C <-- .NOT.RAW_CVAX.C
DEFAULT (iiip) PSL.NZV <-- RAW_CVAX.NZV,
PSL.C <-- PSL.C
MISC = 1D (jizj) PSL.N <-- RAW_CVAX.N .XOR. RAW_CVAX.V,
PSL.Z <-- RAW_CVAX.Z
PSL.V <-- 0,
PSL.C <-- .NOT.RAW_CVAX.C
The MAP_CODEs are set up as follows: When G_S%IID_LD_H is asserted, the
MAP_CODE is set to iiip during the following G_C%PHI2_H. When
G_S%IID_LD_H is not asserted, the MAP_CODE takes on the mapping specified
by the MISC field.
The MAP_CODE changes only when the MISC field has a valid mapping or when
G_S%IID_LD_H is asserted and the MISC field is not selecting a MAP_CODE.
Otherwise the previous MAP_CODE is retained. If G_S%IID_LD_H is asserted,
and the MISC field has a valid MAP_CODE, then the map is set as specified
by the MISC field.
MICROCODE NOTE: After a RESET, the condition code map is in an
unpredictable state until the next IID, or until a valid map setting
appears on the MISC field.
3.9.2 ALU CC Register -
This four bit register latches the RAW_CVAX condition codes for use on
subsequent cycles. It is loaded under the control of the CC field of all
microinstructions:
CVAX CPU CHIP DESIGN SPECIFICATION Page 128
EXECUTION (E) BOX
CC Function
-- -----------------------------------
00 NOP
01 Load ALU CCs from RAW_CVAX.NZVC
10 NOP
11 Load ALU CCs from RAW_CVAX.NZVC
The operation of the Z bit is changed when MISC = OLD.Z. In this case,
the new Z bit is SET only if the current Z data being supplied and the old
Z bit are both SET.
If G_PH%STALL_L is asserted, the load will be inhibited.
The ALU.C bit is buffered (E_S%UDIV_ALU_C_H) and sent to the ALU Control
PLA. It is used to control the UDIV step. Additionally, the ALU
condition code bits are used by the Branch Test Logic.
The ALU CC register can be read onto bits<3:0> of the W_Bus via the W_Spur
as MXPS[EBOX.CCS]. It cannot be written as an MXPS. The ALU CC register
can effect conditional branches under control of the microinstruction BCS
field via the microtest bus as shown below.
BCS Branch Condition
------------ ----------------
10 = ALU.NZV ALU.NZV case
11 = ALU.NZC ALU.NZC case
3.9.3 VAX Restart Flag -
The VAX Restart Flag is a one-bit register which helps the system evaluate
instruction restartability following a memory error. It is cleared by
G_S%IID_LD_H. (Implementation Note: G_S%IID_LD_H is asserted only on
FIRST_IID.) It is set by:
1. Any write to memory that was not aborted by memory management.
2. Any write to a GPR register that did not invoke RLOG.
The first condition, writing to memory, is detected in the M BOX.
If the condition occurs, the M BOX will assert a signal
G_S%SET_RESTART_H to indicate to the E BOX that the restart flag
should be set.
Note: The other VAX-visible resources are some of the internal registers
and the PSL. Any changes to these will be tracked explicitly by the
microcode. Copying a GPR register to itself will set VAX restart.
This flag can be read onto bit<7> of the W_Bus via the W_Spur as
MXPS[EBOX.CCS]. It cannot be written via this MXPS.
CVAX CPU CHIP DESIGN SPECIFICATION Page 129
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3.9.4 Integer Overflow Logic -
This logic network examines the PSL.V bit, the PSL.IV bit and the MAP_CODE
from the previous macroinstruction at IID. If the IV bit in the PSL is
set and PSL.V is 1, and MAP_CODE is iiii or iiij then an optimized integer
overflow has been detected. A trap line, G_S%INT_OVFL_L, is asserted on
PHI2 the cycle after G_S%IID_LD_H is detected by the EBOX. The stall line
is also asserted; this is the only time that the EBOX will assert stall.
The trap dispatches to IE.INTOV in the microcode at an address of 110.
The EBOX does not process the trap.
The signal G_S%IID_LD_H is asserted during G_C%PHI3_H. At this time, the
PSL.IV bit and the map is checked. If PSL.IV is asserted and the map is
set to iiii or iiij, then E_S%EN_INT_OVFL_H is asserted. During the
following G_C%PHI2_H, if PSL.V is set and E_S%EN_INT_OVFL_H is asserted
then an integer overflow has occurred and G_S%INT_OVFL_L is asserted.
3.9.5 Branch Test Logic -
The branch test logic network examines the current PSL CC Register, the
current ALU CC Register, the macro opcode (G_S%OPCODE_H<7:0> from the I
BOX), and the current microinstruction. It generates two signals:
EBT_PH%BCOND_MET_L and G_S%BRANCH_TAKEN_TRAP_L. EBT_PH%BCOND_MET_L is
asserted if a conditional branch has been met. This signal is then used
to determine if G_S%LD_VIBA_AND_PC_H is asserted. G_S%LD_VIBA_AND_PC_H is
asserted when a conditional load of V&PC is called for by the
microinstruction and the branch condition is met, or if and unconditional
load of V&PC is called for by the microinstruction.
EBT_PH%BCOND_MET_L is generated based on the condition codes and macro
opcode as shown in the table below. It is asserted when the branch
condition is met.
Branch Condition Macro Opcode
-----------------------------------------------------
PSL.N BLSS 19 *
PSL.Z BEQL,BEQLU 13 *
PSL.V BVS 1D *
ACBF 4F
ACBD 6F
ACBG 4F
PSL.C BCS,BLSSU 1F *
.NOT.(PSL.N) BGEQ 18 *
SOBGEQ F4
.NOT.(PSL.Z) BNEQ,BNEQU 12 *
.NOT.(PSL.V) BVC 1C *
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.NOT.(PSL.C) BCC,BGEQU 1E *
(PSL.C).OR.(PSL.Z) BLEQU 1B *
(PSL.N).OR.(PSL.Z) BLEQ 15 *
.NOT.((PSL.C).OR.(PSL.Z)) BGTRU 1A *
.NOT.((PSL.N).OR.(PSL.Z)) BGTR 14 *
SOBGTR F5
ALU.Z BBC E1
BBCS E3
BBCC E5
BBCCI E7
BLBC E9
.NOT.(ALU.Z) BBS E0
BBSS E2
BBSC E4
BBSSI E6
BLBS E8
(ALU.N).XOR.(ALU.V) AOBLSS F2
((ALU.N).XOR.(ALU.V)).OR.(ALU.Z) AOBLEQ F3
ACBB 9D
ACBW 3D
ACBL F1
* - Indicates a "simple" branch (branch taken in next cycle).
Additionally, if the branch condition is met and a conditional load of
V&PC.TRAP is called for by the microinstruction (indicated by the
assertion of E_S%BCOND_LD_PC_TRAP_L), the trap line
G_S%BRANCH_TAKEN_TRAP_H is asserted; the stall line is not asserted.
The trap dispatches to IE.COND.BRANCH in the microcode at an address of
100. The EBOX does not process the trap.
3.9.6 Microcode Restrictions -
1. The PSL cannot be written (A field = PSL, DST field = DST.A) at
the same time the PSL condition code bits are being updated
(LOAD.PSL.CC or LOAD.ALU.CC&PSL.CC).
CVAX CPU CHIP DESIGN SPECIFICATION Page 131
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3.10 RLOG
This is a six entry LIFO stack onto which a GPR's address and the amount
it is being changed are pushed. It is used to restore GPR contents under
certain exception conditions. It is used primarily with
auto-increment/decrement mode instructions, and when addressing GPR[RN]:
RLOG<3:0> <- RN<3:0>
RLOG<5:4> <- encoded incr/decr amount (contents of the DL reg if
K(DL) is selected to B_Bus, otherwise #2)
RLOG<6> <- 1 for add, 0 for subtract
The stack is pushed when executing a microinstruction in which the misc
function is MISC/RLOG. The stack is cleared by IID. It is popped when
read via its MXPS address. The RLOG is implemented as a 7-bit register
stack with a single one-bit register being used as RLOG<7>. When popped,
RLOG<7> will be SET if the stack is empty and CLEAR if the stack is not
empty.
3.10.1 Implementation Notes -
RLOG<5:4> and RLOG<6> are implemented as follows:
RLOG<5:4> <-- encoded incr/decr amount (contents of DL
register) if BASIC; else #2.
RLOG<6> <-- 1 for [BASIC.(A.PLUS.B) + CONST.(A.PLUS.CONST)];
else 0.
The empty bit is sticky in both directions. RLOG correctly pushes data
when it is not full; all attempts to push when full are ignored and no
corruption occurs. Push and pop both cause state changes and consequently
are inhibited when G_PH%STALL_L is asserted.
3.10.2 Microcode Restrictions -
1. Push/pop of RLOG is not allowed during IID.
2. Push and pop are mutually exclusive.
3. See Implementation Notes above.
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3.11 State Logic
STATE<5:0> is a general purpose state register whose bits can be set or
cleared in a variety of ways.
STATE<5:0> may be read onto G_S%W_BUS_H<5:0> via G_P%W_SPUR_H<5:0> as
MXPS[EBOX.STATE]. The STATE register may not be written via the W_SPUR.
STATE<3:0> may be cleared using the MISC field in all microinstructions
and STATE<5:4> may be cleared using the MISC3 field of the SPECIAL
microinstruction. Additionally STATE bits <2:0> can be individually set
using the MISC field and STATE bits <5:3> can be individually set using
the MISC3 field. This is shown below.
MISC3 MISC
----------------- ------------------
1 = CLR.STATE.5-4 10 = CLR.STATE.3-0
2 = SET.STATE.3 11 = SET.STATE.0
4 = SET.STATE.4 12 = SET.STATE.1
8 = SET.STATE.5 13 = SET.STATE.2
During Initial Instruction Decode (IID), STATE<3:0> are CLEARED.
In addition to being readable on the G_S%W_BUS_H, STATE bits are testable
on the Microtest Bus (G_P%UTEST_L<2:0>), via the BCS field, as follows:
BCS Branch Condition
------------- ------------------
16 = STATE2-0 STATE <2:0> Case
17 = STATE5-3 STATE <5:3> Case
There is a latency associated with the value of the STATE Register when
read onto the uTEST Bus as follows:
assume VALUE 1 is in STATE
;-------------------------------;
[State]<--[Value 2] ; Case here is on Value 1
;-------------------------------;
[State]<--[Value 3] ; Case here is on Value 2
;-------------------------------;
... ; Case here is on Value 3
;-------------------------------;
... ; Case here is on Value 3
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3.11.1 Microcode Restrictions -
1. An MXPS.STATE must not occur during the same instruction as any
clear or set of the STATE bits. This will result in
unpredictable data on the W_SPUR.
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3.12 Opcode Register
The opcode register is an 8-bit, 3-stage master-slave register which holds
the current VAX opcode byte. It is written from the prefetch queue at IID
time, and may be read by MXPS0[OPCODE] to the W-spur, G_PH%W_SPUR_H<7:0>
or by CASE[OPCODE2-0] to the microtest bus, G_PH%UTEST_L<2:0>.
The first stage of the opcode register is always loaded on phase 2. The
second stage is loaded on phase 1 when the signal G_S%LOAD_MASTER_OPCODE_H
is asserted by the I Box. The third stage is loaded when the signal
G_S%LOAD_SLAVE_OPCODE_H is asserted (this occurs during Phi3). The source
lines for driving the opcode to the w-spur and utest lines are the outputs
of the third stage of the register. Likewise, the lines used in the
branch logic are also the outputs of the third stage. Outputs of the
other two stages are used ONLY as inputs to the next register stage.
All eight opcode bits are driven onto the w-spur during phase 3 when the
signal G_S%SPUR_GETS_OPCODE_H is asserted by the I Box. The lower three
bits, opcode<2:0>, are inverted and driven to the utest bus during phase 1
when the signal G_S%UTEST_GETS_OPCODE_H is asserted by the I Box.
3.12.1 Microcode Restrictions -
1. An MXPS0[OPCODE] may not be done in the same cycle as DEC.NEXT.
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3.13 Summary Of E BOX Microcode Restrictions
3.13.1 Register File -
1. W_SPUR - A W_SPUR read cannot immediately follow a W_SPUR write.
3.13.2 Program Counter (PC Register) -
1. For PC writes of other than data length LONG, the unwritten
portion of PC is unpredictable.
2. The PC cannot be written via GPR[RN] or GPR[15].
3. The PC cannot be written via A = PC and DST = DST.A.
4. In the SPECIAL microinstruction, the PC cannot be written using
the MISC2 and MISC field simultaneously.
5. The PC cannot be written explicitly in one cycle and then read in
the next cycle.
6. The PC cannot be written during a read from memory.
3.13.3 Constant Generator -
No known restrictions.
3.13.4 SC Logic -
1. Shadow_SC - A W_SPUR read cannot immediately follow a W_SPUR
write.
3.13.5 Shifter -
1. When MISC/SHIFT.DL is asserted, the SHIFT.DIR field must specify
a left shift.
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3.13.6 ALU -
No known restrictions.
3.13.7 Q Register -
1. The Q Register cannot be read in the cycle immediately following
a Q Register write.
2. The Q Register cannot be read in the cycle immediately following
a SMUL or UDIV operation.
3. An SMUL operation cannot immediately follow a Q Register write.
(Note: No such restriction applies to UDIV.)
4. The Q Register cannot be written during a read from memory.
3.13.8 PSL Logic -
1. The PSL cannot be written (A field = PSL, DST field = DST.A) at
the same time the PSL condition code bits are being updated
(LOAD.PSL.CC or LOAD.ALU.CC&PSL.CC).
2. A write to PSL is not allowed during IID (TP load conflict).
3. The PSL cannot be written during a read from memory.
4. The PSL cannot be read immediately following a PSL write.
3.13.9 CC Logic -
1. The PSL cannot be written (A field = PSL, DST field = DST.A) at
the same time the PSL condition code bits are being updated
(LOAD.PSL.CC or LOAD.ALU.CC&PSL.CC).
3.13.10 RLOG -
1. Push/pop of RLOG is not allowed during IID.
2. Push and pop are mutually exclusive.
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3.13.11 STATE -
1. An MXPS.STATE must not occur during the same instruction as any
clear or set of the STATE bits. This will result in
unpredictable data on the W_SPUR.
3.13.12 OPCODE REGISTER -
1. An MXPS0[OPCODE] may not be done in the same cycle as DEC.NEXT.
CVAX CPU CHIP DESIGN SPECIFICATION Page 138
EXECUTION (E) BOX
3.14 E BOX Microcode Visible State
The table below shows all the microcode visible storage registers located
in the E Box and how they are modified or changed.
Name Size Alteration Conditions
-------------------------------+------+-------------------------------------------------------------------------------------------
W[0:7] 32 DST field = DST.A, and A field = W[n]; Write to W[n]
MicroCode Working Registers DST field = DST.B, and B field = W[n]; Write to W[n]
DST field = DST.W[SN]; Write to W[SN]
MISC field = WRITE.SC; Write to register W[7]
-------------------------------+------+-------------------------------------------------------------------------------------------
GPR[0:15] 32 DST field = DST.A, and A field = GPR[n]; Write to GPR[n]
General Purpose Registers 16,8 DST field = DST.A, A field = GRN, with RN being specified by SPEC.RN<3:0> from the I BOX
-------------------------------+------+-------------------------------------------------------------------------------------------
T[0:15] 32 DST field = DST.A, and A field = T[n]; write to T[n]
MicroCode Temporary Registers
-------------------------------+------+-------------------------------------------------------------------------------------------
Shadow_SC 8 DST field = DST.A, and A field = W[7]
DST field = DST.W[SN] and SN = 7
MISC field = WRITE.SC; Writes SC(W[7]) as well as the Shadow_SC
-------------------------------+------+-------------------------------------------------------------------------------------------
PSL 32 DST field = A, and A field = PSL
Processor Status Longword
-------------------------------+------+-------------------------------------------------------------------------------------------
Q-Register 32 DST field = A, and A field = Q
Multiplier Quotient Register BASIC.FNC = SMUL.STEP or UDIV.STEP (activates single-bit shifting)
-------------------------------+------+-------------------------------------------------------------------------------------------
ALU.CC 4 CC field = LOAD.ALU.CC
ALU Condition Codes CC field = LOAD.ALU.CC&PSL.CC
-------------------------------+------+-------------------------------------------------------------------------------------------
PSL.CC 4 CC field = LOAD.PSL.CC
PSL Condition Codes CC field = LOAD.ALU.CC&PSL.CC
-------------------------------+------+-------------------------------------------------------------------------------------------
STATE 6 MISC field = CLR.STATE.3-0; Clear State<3:0>
MISC field = SET.STATE.0; Set State<0>
MISC field = SET.STATE.1; Set State<1>
MISC field = SET.STATE.2; Set State<2>
MISC3 field = CLR.STATE.5-4; Clear State<5:4>
MISC3 field = SET.STATE.3; Set State<3>
MISC3 field = SET.STATE.4; Set State<4>
MISC3 field = SET.STATE.5; Set State<5>
IID Clears State<3:0>
-------------------------------+------+-------------------------------------------------------------------------------------------
PC 32 MISC field = LOAD.V&PC; Unconditionally load PC
Program Counter MISC field = IF.BCOND.LOAD.V&PC; if EBT_S%BCOND_MET_L is asserted, then load PC
MISC field = IF.BCOND.LOAD.V&PC.TRAP; if EBT_S%BCOND_MET_L is asserted, then load PC
MISC2 field = LOAD.PC.FROM.BPC
-------------------------------+------+-------------------------------------------------------------------------------------------
PSL Map 4 MISC field = MAP.JIZJ; set map to jizj
MISC field = MAP.IIII; set map to iiii
MISC field = MAP.IIIJ; set map to iiij
IID; set map to default of iiip
-------------------------------+------+-------------------------------------------------------------------------------------------
CVAX CPU CHIP DESIGN SPECIFICATION Page 139
EXECUTION (E) BOX
3.15 E BOX Schematic Inventory
The following table lists all of the schematics in the E BOX, with the
corresponding schematic ID and a brief description of the contents of each
schematic.
Schematic Name Schematic ID Contents
============== ============ ======================================================================================
E_ALU_CON EAC SMUL, UDIV mux and its control logic.
E_ALU_CON_MIB EACM ALU decode PLA. Carry in, SMUL, and UDIV logic.
E_ALU_DP EAD Contains the ALU Datapath Logic
E_ALU_DRIVERS EAR Contains the Control line drivers for the ALU Datapath as well as the
associated control logic.
E_BARREL_DEC EBDEC This circuit drives the 33 Shifter control lines. It decodes the shift
value and direction.
E_BARREL_DEC_CON EBDECC Slave latches for SHFTVAL, SHIFT_DIR, ZERO_A, and ZERO_B.
E_BARREL_DEC_CON_MIB EBDECM Shadow SC, muxing SC to UTEST, generation of SHFTVAL to control the shifter.
Generation of the signals to activate the shifter, shift direction,
and shift zeroing.
E_BARREL_LATCH EBL Shifter latch. Latches A and B Busses and performs Shifter zeroing.
E_BARREL_LATCH_CON EBC This controls the precharging, enabling, and zeroing of the shifter latch.
E_BARREL_SFT EBS Shifter with N bit detect on byte, word and long word.
E_BT_LOGIC EBT Opcode Decode, Branch Test Logic, Branch Taken Trap, Load VIBA&PC,
Integer Overflow.
E_BUS_DRIVERS EBD W Bus, M Bus, and W SPUR Drivers. Zero extention. Three way mux to select
SPUR, ALU_SHFT, or MW. Muxes PSL bits to Spur. Zero detection on each byte.
E_BUS_DRIVERS_CON EBDC Bus Driver Control circuit.
E_BUS_DRIVERS_CON_MIB EBDCM MIB decode for the Bus Driver Control circuit.
E_CC_DECODE ECD MIB decodes for the Condition Code Logic Block. Early portion of Integer
Overflow Logic
E_CC_LOGIC ECL Condition Code Logic: Raw CC select logic, ALU CC's, PSL CC's, PSL Map,
SPUR and uTest Drive Logic.
E_KMUX_CTRL EKC Control and MIB decodes for the KMUX. Two random decodes for EMC.
E_MISC_CTRL EMC Contains the datapath drivers and control (excluding MIB decodes) for
the following sections: KMUX (additional loaction for KMUX control is
in EKC), PSL, Q Register, and PC.
CVAX CPU CHIP DESIGN SPECIFICATION Page 140
EXECUTION (E) BOX
E_MISC_DP EMD Contains the following Datapath logic: KMUX, PSL, and Q Register.
E_OPCODE_REG EOR Contains the Opcode Register. Three deep by 8 wide.
E_PC_DP EPC Contains the Entire PC Datapath. Includes PC, Backup PC, and PC incrementer.
E_RF ERF Register File: T, GP, and W registers. Sense amps.
E_RF_B_FIELD_DEC EBF B field decode array.
E_RF_DEC_DST_CON ERD MIB decode. Detects whether the B field address is direct, SN, or SN+1. Also
controls the DST selection. Vax Restart Flag and associated logic.
E_RF_TG_DEC EDTG A field decode, RN decode, select line generation for T and GP registers; DL
logic for writes.
E_RF_W_DEC EDW A field decode, SN and SN+1 decode, select line generation for W registers;
misc A field decodes and select line control logic.
E_RLOG ERL Contains R Log and its control. Also has some control for the Vax Restart Flag.
U Test and Spur drivers for E_OPCODE_REG.
E_STATE_LOGIC ESL EBOX State Registers: Includes uTest and Spur drive logic.
E_ZERO_DET_CTRL EZD Generates Zero Detection (Byte, Word, and Long) from the byte wide zero detection
in the datapath.
CVAX CPU CHIP DESIGN SPECIFICATION Page 141
EXECUTION (E) BOX
3.16 E BOX Global Signal Timing
The diagram below gives a list of global signals used or generared in the
E BOX. The cycle shown here is 100nS long. But all the Spice timing
results are for an 92nS cycle with clock skews of 2nS between adjacent
clock phases.
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%B_BUS_H<31:0> |~~xxxxxx======================HHHHHHHHH| B_BUS C Load = 3pF |
| | | | | | * Simulated with 4pF (erf), 3.2pF (emd) |
| * Valid PHI1 + (17nS - emd), (20nS - erf) |
| Source - EBOX (emd,erf),MBOX,IBOX Destination - EBOX (ead,ebl) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%BRANCH_TAKEN_TRAP_L |xxxxxxxxxxxxxxxxx======================| BRANCH TAKEN TRAP LINE C Load = 2.5pF |
| | | | | | * Simulated with 3.0pF |
| * Valid 7nS before PHI3 to PHI1 |
| Source - EBOX (ebt) Destination - USEQ |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%COPY_TRACE_H |___/=====\_____________________________| COPY TRACE BITS FLAG C Load = 3pF |
| | | | | | * Conditioned with STALL in the IBOX |
| * Asserted PHI1 + 9nS to PHI2 |
| Source - IBOX Destination - EBOX (emd) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%DELTA_PC_L<2:0> |xxxxx==============xxxxxxxxxxxxxxxxxxxx| NUMBER BYTES RETIRED BY IBOX CLoad = 2pF |
| | | | | | * Valid PHI1 + 20nS to End of PHI2 |
| |
| Source - IBOX Destination - EBOX (epc) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%DL_H<1:0> |=====================xxxxxxxxx=========| DATA LENGTH REGISTER C Load = 5.4pF |
| | | | | | * Valid PHI4 + 2nS to PHI3 |
| | | | | | |
| |
| Source - IBOX Destination - MBOX,USEQ,EBOX (ekc, ecd, ebdc , ebdecm , erl , edtg ) |
| late 4, early 4, early 4, late 4) |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 142
EXECUTION (E) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%FPU_CCZ_H |xxxxxxxx===============================| CONDITION CODES FROM FPU C Load = 2.9pF |
| G_S%FPU_CCV_H | | | | | * Valid PHI1 + 20nS |
| G_S%FPU_CCN_H | | | | | |
| | | | | | |
| |
| Source - FPA LOGIC Destination - EBOX (ecl) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%IID_LD_H |__________________________/============| IID SIGNAL TO CHIP C Load = 4.1pF |
| | | | | | * Valid PHI3 + 17 to PHI1 |
| |
| Source - IBOX Destination - MBOX,EBOX (emc, ecd, esl, erl , erd ) |
| not time crit, latched in 3 ) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%INT_OVFL_L |HHHHHHHHHH~~xxxx=======================| INTEGER OVERFLOW LINE C Load = 2.1pF |
| | | | | | * Simulated with 3.5pF |
| * Driven High PHI1; valid PHI3 - 9nS |
| Source - EBOX (ebt) Destination - IBOX,USEQ |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%LD_VIBA_AND_PC_H |==========xxxxxxxxxxxxxxx==============| GOING TO LOAD VIBA and PC C Load = 9.6pF |
| | | | | | * Not conditioned with Stall |
| * Simulated with 10pF |
| * Valid PHI3 - 2nS through PHI1 |
| Source - EBOX (ebt) Destination - IBOX,MBOX,BIU,EBOX (emc) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%LOAD_MASTER_OPCODE_H |____/=====\____________________________| LOADING OPCODE IN MASTER C Load = 2.2pF |
| | | | | | * Valid PHI1 + 12ns to PHI2 |
| |
| Source - IBOX Destination - EBOX (eor) |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 143
EXECUTION (E) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%LOAD_PSL_H |_____________/=======\_________________| LOADING PSL ENABLE C Load = 5.6pF |
| | | | | | * Conditioned with Stall |
| * Simulated with 6.0pF |
| * Valid PHI2 + 12nS, Trails PHI2 by 6nS |
| Source - EBOX (emc) Destination - MBOX,IBOX,INT LOGIC,BIU |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%LOAD_SLAVE_OPCODE_H |__________________________/======\_____| LOAD SLAVE OF OPCODE REG C Load = 1.2pF |
| | | | | | * Valid PHI3 + 16nS through PHI4 + 10nS |
| |
| Source - IBOX Destination - EBOX (eor) |
| |
+------------+---------------+--------------+----------------+---------------+-------------+-----------------------+
| | | | | | |
| G_S%MIB_H<40:0> |===================xxxxxxxxx===========| MICRO-INSTRUCTION BUS C Load = ~5pF |
| G_S%MIB_L<40:7> | | | | | * Valid low 1nS before rising edge of PHI4 |
| | | | | | |
| |
| Source - CONTROL STORE Destination - GLOBAL |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%MW_BUS_H<31:0> |=========HHHHHHHHHHH~~~~~~~~~XXXXX=====| THE BIDIRECTIONAL BUS BETWEEN THE IDAL |
| | | | | | AND THE WBUS THAT IS AN INPUT TO THE |
| | | | | | WBUS DRIVER C Load = 1.3pF (MW_BUS) + |
| 3.1pF (LMW_BUS) |
| * Valid PHI4 + 8nS (need by 10) on READ MW_BUS Valid PHI1 + 18nS on WRITE |
| Source - MBOX,EBOX (ebd) Destination - MBOX, EBOX (ebd) LMW_BUS Valid PHI1 + 21nS on WRITE |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%MW_DRIVE_H |===================xxxxxx/=============| WHEN ASSERTED ENABLES THE EBOX TO DRIVE |
| | | | | | THE MW_BUS C Load = x.xpF |
| * Valid PHI3 + 12ns |
| Source - MBOX Destination - EBOX (ebdc) Must embrace PHI1 |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 144
EXECUTION (E) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%MW_TO_W_H |=========xxxxxxxxxxx/==================| WHEN ASSERTED SELECTS THE MW_BUS AS THE |
| | | | | | DATA SOURCE FOR DRIVING THE W_BUS |
| * Valid PHI3 + 1nS C Load 1.9pF |
| Source - MBOX Destination - EBOX (ebdc) Must embrace PHI4 |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%NEW_IB_PTR_H<1:0> |=========xxxxxx========================| LOW TWO BITS OF PC REGISTER CLoad = 1.9pF |
| | | | | | * Simulated with 2.0pF |
| * Valid PHI2 + 14nS until next PHI2 |
| Source - EBOX (emc) Destination - IBOX |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%OPCODE_H<7:0> |~~~~~~\\\\\\\===================/~~~~~~| EIGHT BITS TO OPCODE REGISTER CLoad = 1.8pF |
| | | | | | Note: Valid PHI2 + 11 to PHI4 |
| Source - IBOX Destination - EBOX (ebt,eor) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_C%PHI1_H |/~~~~~~~\\\____________________________| PHASE 1 CLOCK C Load = 140pF |
| | | | | | |
| G_C%PHI2_H |_________/~~~~~~~~\\\__________________| PHASE 2 CLOCK C Load = 114pF |
| | | | | | |
| G_C%PHI3_H |___________________/~~~~~~~~\\\________| PHASE 3 CLOCK C Load = 117pF |
| | | | | | |
| G_C%PHI4_H |\\___________________________/~~~~~~~~~| PHASE 4 CLOCK C Load = 133pF |
| | | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%PSL_T_H |< buffered W_BUS waveform >| PSL Trace bit C Load = 2.4pF |
| | | | | | * Buffered W_BUS |
| * Valid while LOAD_PSL is asserted |
| Source - EBOX (emd) Destination - IBOX * NOT SIMULATED |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 145
EXECUTION (E) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%REG_WRITE_H |==================xxxxx================| WRITE REGISTER ENABLED IN C Load = 4.2pF |
| | | | | | THE EBOX |
| * Valid PHI3 + 11nS |
| Source - MBOX Destination - EBOX (erd , edtg) |
| (embrace PHI4, same but setup time reqd.) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%RN_H<3:0> |====================xxxxxxxxxxx========| RN PART OF SPECIFIER BYTE C Load = 2.7pF |
| | | | | | * Valid PHI4 + 2nS to PHI3 |
| |
| Source - IBOX Destination - EBOX (edtg) |
| (required inverter delay before end of PHI3) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%SET_RESTART_H |===================xxxxxx==============| NO MMGT_ERROR ON WRITE C Load = 4.2pF |
| | | | | | * Valid PHI3 + 12nS |
| * EBOX strobes SET_RESTART with PHI4 |
| Source - MBOX Destination - EBOX (erd ) |
| (Must embrace PHI4) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%SN_H<2:0> |===================xxxxxxxxxx==========| WORKING REGISTER NUMBER C Load = 1.8pF |
| | | | | | * Valid PHI4 - 1nS to PHI3 |
| |
| Source - IBOX Destination - EBOX (edw, edtg) |
| (required inverter delay before end of PHI3) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%SPUR_GETS_OPCODE_H |XXXXXXXXX==============================| DRIVE SPUR WITH OPCODE C Load = 1.1pF |
| | | | | | * Valid LE PHI2 through PHI4 |
| |
| Source - IBOX Destination - EBOX (erl) |
| (embrace PHI3 ) |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 146
EXECUTION (E) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%STALL_L |HHHHHHHHHH~~xxxxxxx====================| CHIP-WIDE STALL SIGNAL C Load = 12pF |
| | | | | | * Must be Valid PHI2 + 21nS |
| * Valid (ebt) PHI2 + 18nS with 11.5pF |
| Source - MBOX,BIU,IBOX,uSEQ,EBOX (ebt) Destination - GLOBAL,EBOX (emc,ecd,esl, erl ) |
| , Prech only) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%UTEST_GETS_OPCODE_H |===================/~~~~~~~~~XXXXXXXXXX| Drive uTEST with OPCODE C Load = 0.5pF |
| | | | | | * Valid PHI1 through PHI2 |
| |
| Source - IBOX Destination - EBOX (erl ) |
| (embrace PHI1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%UTEST_L<2:0> |~xxxx===============HHHHHHHHHH~~~~~~~~~| MICRO-TEST BUS C Load = 4.5pF |
| | | | | | * Must be Valid 15nS after LE of PHI1 |
| * Valid (ecl) PHI1 + 15nS with 5.0pF |
| * Valid (esl) PHI1 + 17nS with 5.0pF |
| * Valid (ebdecm) PHI1 + 15nS with 5.0pF |
| * Valid (erl) Not simmed. Same as above |
| Source - GLOBAL,EBOX (ecl,esl,ebdecm) Destination - USEQ |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%W_BUS_H<31:0> |=============================xxxxxxxxx=| W-BUS C Load = 4.4 pF |
| | | | | | * Simulated with 4.4pF (ebd) |
| * Valid 2ns before 1 thru start of PHI4 |
| Source - EBOX (ebd) Destination - MBOX,EBOX (epc,emd,erf) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%W_SPUR_H<7:0> | | | | | W-BUS SPUR C Load = 6.5 pF |
| WRITE |~xxxxxxxx=====================HHHHHHHHH| * Must be Valid before PHI2 |
| | | | | | |
| READ |==========HHHHHHHHHH~xxxxxxxxxxxxx=====| * Speced at 10 nS into PHI4, spice below: |
| | | | | | * Valid (ebd) PHI1 + 18nS with 6.6pF |
| * Valid (ecl) PHI3 + 20nS with 6.6pF |
| * Valid (erd) PHI4 - 5nS with 6.6pF |
| * Valid (erl) PHI4 - 4nS with 6.6pF |
| * Valid (esl) PHI1 + 18nS with 5.0pF |
| |
| Source - GLOBAL, EBOX (ecl,esl,ebd,erl,erd) Destination - GLOBAL, EBOX (ebdecm) |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 147
EXECUTION (E) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%WSEL_UPDATE_H |xxxxxxxxx==============================| UPDATE WSEL LATCHES IN EBOX C Load = 2.7pF |
| | | | | | * Valid PHI1 + 21nS |
| |
| Source - MBOX Destination - EBOX (ebdc , edw ) |
| (embrace PHI3, same) |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 148
EXECUTION (E) BOX
3.17 E BOX Internal Signal Timing
The diagram below lists all the internal E BOX signals that cross
schematic boundaries. The cycle shown here is 100nS long. But all the
Spice timing results are for an 92nS cycle with clock skews of 2nS between
adjacent clock phases.
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------^
| | | | | | |
| E_PH%A_BUS_H<31:0> |~~XXXXXXX====================HHHHHHHHHH| A Bus Precharged high |
| | | | | | |
| Spice Ref (Block/Text): E_RF_SIM, E_PC_SIM (Valid PHI1 + 17nS), E_MISC_CTRL_SIM Last Updated: 9/09/86 |
| (Valid PHI1 + 20, 1.35pF), E_QREG_SIM (Valid PHI1 + 17nS, 1.35pF), Cl = 1.25 pF |
| E_PSL_SIM (Valid PHI1 + 16nS, 1.35pF) |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| erf, epc, emd LE PHI2 ead 2 gate delays before LE PHI2 Yes |
| ebl latched in PHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_PH%ALU_SHFT_H<31:0> |=========HHHHHHHHHH~~XXXXXXXXXXXX======| When driven by the SHIFTER |
| | | | | | |
| |===================XXXXXXXXXXXXXX======| When driven by the ALU |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_SIM (Valid PHI1 - 24nS, 2.5pF) Last Updated: 9/09/86 Cl = 2.3pF |
| E_BARREL_SFT_SIM (Valid PHI1 - 17nS, 2.4pF) This speed is for EBD_S%ALU_SHFT_H, ie |
| two inverters later. Otherwise the slope is too shallow to spec. |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ead,ebs See above ebd PHI1 - 10.5ns Latch in ebd No |
| ebl Prech Only |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_PH%LA_BUS_H<31:0> Timing not speced - Spice simulation crosses schematic boundary |
| E_PH%LB_BUS_H<31:0> |
| |
| Driven by: ebl Used by: ebs |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ALU_BYTE_C_H |==XXXXXXXXXXXXXXXXXXXXXXXX=============| BYTE Carry From ALU |
| E_S%ALU_BYTE_V_H | | | | | BYTE oVerflow From ALU |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_SIM Last Updated: 9/04/86 |
| Cl = 1.1 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ead PHI3 + 15nS ecl LE PHI4 mux in ecl No |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 149
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ALU_CIN_H<0> |XXXXXXXX=====================XXXXXXXXXX| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/09/86 |
| Cl = 0.5 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| eac PHI2 - 4ns (0.48pF) ead LE PHI2 |
| until end of PHI3 ENTIRE PHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ALU_LONG_C_H |==XXXXXXXXXXXXXXXXXXXXXXX==============| LONGWORD Carry From ALU |
| E_S%ALU_LONG_V_H | | | | | LONGWORD oVerflow From ALU |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_SIM Last Updated: 9/04/86 |
| Cl = 1.7 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ead PHI3 + 15nS ecl LE PHI4 mux in ecl No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ALU_N_XOR_V_H |XXXXXX========================XXXXXXXXX| ALU.N XOR ALU.V for Branch Test |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.29pF) Last Updated: 9/04/86 |
| Cl = 0.27 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI1 + 17nS ebt LE PHI2 No No |
| entire PHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ALU_N_XOR_V_OR_Z_H |XXXXXX========================XXXXXXXXX| (ALU.N XOR ALU.V) OR ALU.Z for Branch Test |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.33pF) Last Updated: 9/04/86 |
| Cl = 0.33 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI1 + 17nS ebt LE PHI2 No No |
| entire PHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ALU_PCH1_L |\_________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~| PHI1 precharge signal for ALU |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_SIM Last Updated: 2/18/86 |
| Cl = 14.3 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ear EARLY PHI1 ead PHI1 preharge No Yes |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 150
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%ALU_SHFT_TO_W_H Timing not speced - Spice simulation crosses schematic boundary |
| E_S%ALU_SHFT_TO_W_L |
| |
| Driven by: ebdc Used by: ebdc, ebd |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ALU_SUM_H<0> |===================XXXXXXXXXXXX========| ALU sum bit <0>, used with QREG in |
| | | | | | SMUL step |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_SIM Last Updated: 9/04/86 |
| Cl = 1.4 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ead PHI4 + 2nS emd PHI1 mux in emd No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ALU_SUM_L<31> |===================XXXXXXXXXXXXXXXXXXX=| ALU sum bit <31>, used with QREG in |
| | | | | | UDIV step |
| Spice Ref (Block/Text): E_ALU_SIM Last Updated: 9/04/86 |
| Cl = 1.4 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ead PHI4 + 21nS emd PHI1 mux in emd No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ALU_WORD_C_H |==XXXXXXXXXXXXXXXXXXXXXXXX=============| WORD Carry From ALU |
| E_S%ALU_WORD_V_H | | | | | WORD oVerflow Carry From ALU |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_SIM Last Updated: 9/04/86 |
| Cl = 1.3 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ead PHI3 + 15nS ecl LE PHI4 mux in ecl No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ALU_Z_H |XXXXXXXX===============================| ALU.Z for uTest and Branch Test |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.76pF) Last Updated: 9/04/86 |
| Cl = 0.76 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI1 + 18nS ebt LE PHI2 No Yes |
| entire PHI2 |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 151
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%ASEL_H<GP14:0> Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: edtg Used by: erf |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%ASEL_H<T15:0> Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: edtg Used by: erf |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%ASEL_H<W7:0> Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: edw Used by: erf |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%B7_L thru Timing not speced - Spice simulation crosses schematic boundary |
| E_S%B0_L |
| |
| Driven by: ebf Used by: edw |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%B_READ_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: erd Used by: edw |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%BCOND_LD_PC_L |XXXXXXX================================| BCOND.LD.V&PC |
| E_S%BCOND_LD_PC_TRAP_L | | | | | BCOND.LD.V&PC.TRAP |
| | | | | | |
| Spice Ref (Block/Text): E_CC_DECODE_SIM (sim with 1.1pF) Last Updated: 9/04/86 |
| Cl = 1.1 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecd PHI1 + 18nS ebt PHI2 thru No No |
| EARLY PHI4 |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 152
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%BCS_ALU_NZC_H |///=========\__________________________| Drive ALU.NZC onto uTest |
| E_S%BCS_ALU_NZV_H | | | | | Drive ALU.NZV onto uTest |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.8pF) Last Updated: 9/04/86 |
| Cl = 0.78 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecd PHI1 delayed by ecl PHI1 ctrl No Yes |
| 5nS when asserted |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| |
| E_S%BSEL_H<W7:0> Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: edw Used by: erf |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%CIN_IS_1_L Timing not speced - Spice simulation crosses schematic boundary |
| E_S%CIN_IS_PSL_L |
| E_S%CIN_IS_PSLBAR_L |
| |
| Driven by: eacm Used by: eac |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%DEC_ALU_DR_L |XXXXXXXXXXXX===========================| Instruction is ~SHIFT. ALU result to be |
| | | | | | driven onto ALU_SHFT. |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/09/86 |
| Spiced but not recorded - lots of margin Cl = 1.15 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| eacm Late 1 or early 2 ear PHI3 thru PHI4 lat in ear No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%DEC_ALU_SHL_H |XXXXXXXXXXXX===========================| |
| E_S%DEC_ALU_SHR_H | | | | | |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/09/86 |
| Spiced (1.12pF) but not recorded - lots of margin Cl = 1.1 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| eac Late 1 or early 2 ear,emc PHI3 No No |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 153
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%DEC_BACKUP_PC_H |===================XXXXXXXXXXXXXX =| Decode PC -> Backup PC |
| | | | | | |
| Spice Ref (Block/Text): E_KMUX_SIM (sim with 1.21pF) Last Updated: 9/04/86 |
| Cl = 1.22 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ekc PHI4 + 11nS emc PHI1 lat in emc No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%DEC_DST_A_H |===================XXXXXXXXXXXXXXXX====| Decode DST = DST.A |
| | | | | | |
| Spice Ref (Block/Text): E_KMUX_SIM (sim with 1.07pF) Last Updated: 9/04/86 |
| Cl = 1.1 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ekc PHI4 + 12nS emc PHI1 No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%DEC_K1_H |====================XXXXXXXXXXXXXXXXX==| Decode A = K1 |
| E_S%DEC_KSEXT_H | | | | | Decode A = K.SEXT |
| |
| Spice Ref (Block/Text): Last Updated: 9/09/86 |
| Simmed with extracted cap Cl = 0.57 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| edw PHI4 + 16ns emc PHI1 No Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%DEC_PC_ASEL_H |====================XXXXXXXXXXXXXXXXX==| Decode A = PC |
| E_S%DEC_PSL_ASEL_H | | | | | Decode A = PSL |
| E_S%DEC_Q_ASEL_H | | | | | Decode A = Q |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/09/86 |
| Simmed with extracted cap Cl = 0.81 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| edw PHI4 + 16ns emc PHI1 No No |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 154
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%DR_ALU_H |\\_________________//==================| Drive ALU result onto ALUSHFT |
| | | | | | |
| E_S%DR_ALU_L | | | | | |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_SIM Last Updated: 2/18/86 |
| Cl = 6.3/13.3 pF (H/L) |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ear PHI3 + PHI4 ead PHI3 thru PHI4 No No |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%DRIVE_MW_H Timing not speced - Spice simulation crosses schematic boundary |
| Valid from PHI1 + 9nS to PHI2 + 11.5nS |
| Driven by: ebdc Used by: ebd |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%DRIVE_SPUR_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: ebdc Used by: ebd |
| Valid from PHI1 + 7nS to PHI2 + 5.5nS |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%DST_A_H Timing not speced - Spice simulation crosses schematic boundary |
| E_S%DST_A_L |
| |
| Driven by: erd Used by: edw, edtg |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%DST_B_H Timing not speced - Spice simulation crosses schematic boundary |
| E_S%DST_B_L |
| |
| Driven by: erd Used by: edw |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%DST_WSN_H Timing not speced - Spice simulation crosses schematic boundary |
| E_S%DST_WSN_L |
| |
| Driven by: erd Used by: edw |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 155
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%DST_ZILCH_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: erd Used by: edw |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%EBD_PHI4_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: ebdc Used by: ebd |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%EN_INT_OVF_H |=============================XXXXXX====| PSL.V set, Overflow Map set, IID previous |
| | | | | | phase 3. Condition with PSL.IV. |
| | | | | | |
| Spice Ref (Block/Text): E_BT_LOGIC_SIM (sim with 0.45pF) Last Updated: 9/04/86 |
| Cl = 0.4 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecd PHI4 + 13nS ebt ENTIRE PHI2 No Yes |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%ENABLE_LA_LB_BUS_H Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: ebc Used by: ebl |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%ERF_PHI4_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: edw Used by: erf |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%ERF_PHI3_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: edw Used by: erf |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%G_FCT_DP_L<3:0> |~~~~~~~~~\\\========//////~~~~~~~~~~~~~| G Function in ALU DataPath |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_SIM (See simulation for simulation loading) Last Updated: 9/03/86 |
| Cl = 2.54 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ear If asserted, ead ENTIRE PHI2 Yes No |
| Low PHI1 + 10nS |
CVAX CPU CHIP DESIGN SPECIFICATION Page 156
EXECUTION (E) BOX
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 157
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%G_FCT_H<3:1> |XXXXXXXXX===========XXXXXXXXXXXXXXXXXXX| |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_CON_SIM (simmed with 0.41pF) Last Updated: 9/09/86 |
| Cl = 0.43 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| eac At 3.6v by PHI2 ear ENTIRE PHI2 No No |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%G_H<3:1> Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: eacm Used by: eac |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%GA_RN_H Timing not speced - Spice simulation crosses schematic boundary |
| E_S%GA_RN_L |
| |
| Driven by: edw Used by: edw, edtg |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%KMUX_ALU_N_L |===========XXXXXXXXXXXXXXXXXXXXXXXXXXXX| Buffered version of ALU.N, used by K.SEXT |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.89pF) Last Updated: 9/04/86 |
| Cl = 0.91 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI1 - 1nS emc LE PHI1 for No Yes |
| ENTIRE PHI1 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%LAT_PK_H |_________//=========\\_________________| Latch Prop and Kill for PC adder |
| | | | | | |
| Spice Ref (Block/Text): E_PC_SIM Last Updated: 2/19/86 |
| Cl = 2.9 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI2 epc PHI2 ctrl No No |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 158
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%LATCH_AND_PRECH_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: ebc Used by: ebl |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%LATCH_H Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: ebc Used by: ebl |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%LD_BPC_H |___________________//========\\________| Load PC into Backup PC |
| | | | | | |
| Spice Ref (Block/Text): E_PC_SIM Last Updated: 2/19/86 |
| Cl = 2.8 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI3 epc PHI3 ctrl No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%LD_PSLDP_CC_H |___________________//========\\________| Load New PSL CCs into datapath register |
| | | | | | |
| Spice Ref (Block/Text): E_PSL_SIM Last Updated: 2/19/86 |
| Cl = 0.7 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI3 emd PHI3 ctrl No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%LD_Q_SLAVE_H |___________________//========\\________| Load Q(master) into Q(slave) |
| E_S%LD_Q_SLAVE_L | | | | | |
| | | | | | |
| Spice Ref (Block/Text): E_QREG_SIM Last Updated: 2/19/86 |
| Cl = 1.81/2.42 pF (H/L) |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI3 emd PHI3 ctrl No No |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 159
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%MAP_IIII_H |==========XXXXXXXX=====================| CC Map set to IIII |
| E_S%MAP_IIIJ_H | | | | | CC Map set to IIIJ |
| E_S%MAP_IIIP_H | | | | | CC Map set to IIIP |
| E_S%MAP_JIZJ_H | | | | | CC Map set to JIZJ |
| | | | | | |
| Spice Ref (Block/Text): E_CC_DECODE_SIM (sim with 0.45pF) Last Updated: 2/18/86 |
| Cl = 0.67 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecd PHI2 + 18nS ecl PHI3 thru PHI1 No No |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%MW_TO_W_H Timing not speced - Spice simulation crosses schematic boundary |
| E_S%MW_TO_W_L |
| Driven by: ebdc Used by: ebd |
| Valid PHI4 + 9ns to PHI1 + 11ns |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%MXPS_RD_CCS_H |XXXXXXXX===============================| Read ALU.CCs and VaxRestart to W_SPUR |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 2/14/86 |
| Cl = 1.26 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| erl Late 1 ecl,erd Entire PHI3 No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| E_S%N_B_H | | | | | |
| E_S%N_LW_H |=========XXXXXXXXXXXXXXXXXXXXXXXXXXXXX=| Raw Negative Detect signals |
| E_S%N_W_H | | | | | |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM Last Updated: 9/04/86 |
| Cl = 1.1 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ebs PHI1 - 10nS (1.0pF) ecl PHI1 - 7nS mux in ecl No |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 160
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%NEW_ALU_CC_H |==========XXXXXXXX=====================| Load New ALU CCs into ALU.CC Register |
| E_S%NEW_PSL_CC_H | | | | | Load New PSL CCs into PSL.CC Register |
| | | | | | |
| Spice Ref (Block/Text): E_CC_DECODE_SIM (sim with 1.3pF) Last Updated: 9/04/86 |
| Cl = 1.35 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecd PHI2 + 21nS ecl PHI4 thru PHI1 No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%NOT_ALU_Z_H |XXXXXXX================================| NOT ALU.Z for Branch Test |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.76pF) Last Updated: 9/04/86 |
| Cl = 0.75 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI1 + 17nS ebt LE PHI2 No Yes |
| entire PHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%NOT_PSL_C_H |=============================XXXXXXXXXX| NOT PSL.C for Branch Test |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.36pF) Last Updated: 9/04/86 |
| Cl = 0.35 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI4 + 24nS ebt LE PHI2 No Yes |
| entire PHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%NOT_PSL_C_OR_Z_H |XXXXXX=======================XXXXXXXXXX| NOT (PSL.C OR PSL.Z) for Branch Test |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (same as E_S%NOT_PSL_N_OR_Z) Last Updated: 9/04/86 |
| Cl = 0.34 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI1 + 17nS ebt LE PHI2 No Yes |
| entire PHI2 |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 161
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%NOT_PSL_N_H |XXXXXXX================================| NOT PSL.N for Branch Test |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.44pF) Last Updated: 9/04/86 |
| Cl = 0.42 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI1 + 17nS ebt LE PHI2 No Yes |
| entire PHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%NOT_PSL_N_OR_Z_H |XXXXXX=================================| NOT (PSL.N OR PSL.Z) for Branch Test |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.3pF) Last Updated: 9/04/86 |
| Cl = 0.34 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI1 + 14nS ebt LE PHI2 No Yes |
| entire PHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%NOT_PSL_V_H |=============================XXXXXXXXX=| PSL.V for Integer Overflow Logic |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.2pF) Last Updated: 2/19/86 |
| Cl = 0.2 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI4 + 21nS ebt LE PHI2 No Yes |
| entire PHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%NOT_PSL_Z_H |XXXXXXX================================| NOT PSL.Z for Branch Test |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.83pF) Last Updated: 9/04/86 |
| Cl = 0.83 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI1 + 17nS ebt LE PHI2 No Yes |
| entire PHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%OPCODE_H<7:0> |===================xxxxxxxxxxxxxx======| EIGHT BITS OF OPCODE REGISTER |
| | | | | | |
| |
| Spice Ref (Block/Text): E_OPCODE_REG_SIM ( C = 1.52 pF ) Last Updated: 9/09/86 |
| Cl = 1.52 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| eor PHI4 + 6nS ebt Setup time before falling PHI4 ? Yes |
| erl By PHI3 ( 1 cycle after loading ) |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 162
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%P_FCT_DP_L<3:0> |~~~~~~~~~\\\========//////~~~~~~~~~~~~~| P Function in ALU DataPath |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_SIM (See simulation for simulation loading) Last Updated: 9/03/86 |
| Cl = 2.52 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ear If asserted, ead ENTIRE PHI2 Yes No |
| Low PHI1 + 10nS |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%P_FCT_H<3:0> |XXXXXXXXX===========XXXXXXXXXXXXXXXXXXX| |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_CON_SIM (0.41pF) Last Updated: 9/09/86 |
| Cl = 0.41 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| eac 3.6v by PHI2 ear ENTIRE PHI2 No No |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%P_H<3:0> Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: eacm Used by: eac, eacm |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PASS_ALU_H |___________________//=========\\_______| Use ALU result as is (no SHL or SHR) |
| E_S%PASS_ALU_L | | | | | |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_SIM Last Updated: 2/18/86 |
| Cl = 2.31/2.78 pF (H/L) |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ear PHI3 ead PHI3 No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PC_ADDSEL_H |\____________________________//========| Load PC from PC Adder (PC <-- PC + DPC) |
| | | | | | |
| Spice Ref (Block/Text): E_PC_SIM Last Updated: 2/19/86 |
| Cl = 2.57 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI4 epc PHI4 ctrl No No |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 163
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PC_ASEL_H |//========\____________________________| Read PC onto A_BUS |
| | | | | | |
| Spice Ref (Block/Text): E_PC_SIM Last Updated: 2/19/86 |
| Cl = 3.25 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI1 epc PHI1 ctrl No Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PC_BPCSEL_H |//========\____________________________| Load PC from BPC |
| | | | | | |
| Spice Ref (Block/Text): E_PC_SIM Last Updated: 2/19/86 |
| Cl = 2.36 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI1 epc PHI1 ctrl No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PC_DP_H<1:0> |==============================XXXXXXXXX| When PC loaded from PC incrementer |
| |XXXXXXXXX==============================| When PC loaded from BPC or W_BUS |
| | | | | | |
| | | | | | Low two-bits of PC. Buffered into |
| | | | | | NEW_IB_PTR and sent to IBOX. |
| | | | | | |
| Spice Ref (Block/Text): E_PC_SIM Last Updated: 9/03/86 |
| Cl = 0.45 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| epc PHI4 (PHI1) emc PHI2 lat in emc No |
| + 24nS |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PC_PCH_L |\\________//~~~~~~~~~~~~~~~~~~~~~~~~~~~| Precharge PC Adder Logic |
| | | | | | |
| Spice Ref (Block/Text): E_PC_SIM Last Updated: 2/19/86 |
| Cl = 5.71 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI1 epc PHI1 precharge No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PC_WSEL_H |//========\____________________________| Load PC from W_BUS |
| | | | | | |
| Spice Ref (Block/Text): E_PC_SIM Last Updated: 2/19/86 |
| Cl = 2.77 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI1 epc PHI1 ctrl No No |
| |
CVAX CPU CHIP DESIGN SPECIFICATION Page 164
EXECUTION (E) BOX
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 165
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%PHI1_EDTG0_L Timing not speced - Spice simulation crosses schematic boundary |
| E_S%PHI3_EDTG1_L |
| E_S%PHI3_EDTG2_L |
| |
| Driven by: edw Used by: edtg |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%PREC_MW_L PHI3 + 9nS to PHI4 + 10nS Timing not speced - Spice simulation crosses schematic boundary |
| E_S%PREC_SPUR_L PHI2 + 8nS to PHI3 + 9.5nS or |
| PHI4 + 8nS to PHI1 + 9.5nS |
| Driven by: ebdc Used by: ebd |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PSL_ASEL_H |///=========\____________________________| Read PSL onto A_BUS |
| | | | | | |
| Spice Ref (Block/Text): E_PSL_SIM Last Updated: 9/03/86 |
| Cl = 3.49 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc PHI1 emd PHI1 ctrl No Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PSL_C_H |=============================XXXXXXX===| PSL.C for ALU Carry In |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.35pF) Last Updated: 9/03/86 |
| Cl = 0.29 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI4 + 17nS eac Ideally LE PHI1 No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PSL_C_OR_Z_H |XXXXXXXXX====================XXXXXXXXXX| PSL.C OR PSL.Z for Branch Test |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (NOT SIMULATED) Last Updated: 9/03/86 |
| Cl = 0.27 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl LE PHI2 ebt LE PHI2 No Yes |
| entire PHI2 |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 166
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PSL_IV_H |XXXXXXXXX==============================| PSL.IV for Integer Overflow Logic |
| | | | | | |
| Spice Ref (Block/Text): E_PSL_SIM (sim with 1.35pF) Last Updated: 9/03/86 |
| Cl = 1.35 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emd PHI1 + 23nS ecd ENTIRE PHI2 No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PSL_N_OR_Z_H |XXXXXXX================================| PSL.N OR PSL.Z for Branch Test |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.35pF) Last Updated: 9/03/86 |
| Cl = 0.29 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI1 + 17nS ebt LE PHI2 No Yes |
| entire PHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PSL_SPUR_H |===================XXXXXXXX============| Inform SPUR to drive PSL |
| | | | | | |
| Spice Ref (Block/Text): E_MISC_CTRL_SIM Last Updated: 9/03/86 |
| Cl = 1.23 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc PHI3 + 16nS ebdc PHI4 No No |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| Timing not speced - Spice simulation crosses schematic boundary |
| E_S%PSL_TO_SPUR_H PHI4 + 11.5nS, cleared by rising PHI2 |
| E_S%PSL_TO_SPUR_L PHI4 + 10 nS, cleared by rising PHI2 |
| |
| Driven by: ebdc Used by: ebd |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PSL_WSEL_H |/=========\____________________________| Load PSL Register from W_BUS |
| | | | | | |
| Spice Ref (Block/Text): E_PSL_SIM Last Updated: 9/03/86 |
| Cl = 2.14 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI1 emd PHI1 ctrl No No |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 167
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PSLIN_C_H |==============================XXXXXXXXX| PSL.C and PSL.V for Branch Test and to |
| E_S%PSLIN_V_H | | | | | put CCs into Datapath register. |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 1.05pF) Last Updated: 9/03/86 |
| Cl = 1.05 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI4 + 21nS emd, ebt ebt - PHI2 No Yes |
| emd - PHI3 pass in emd No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PSLIN_N_H |XXXXXXX================================| PSL.N and PSL.Z for Branch Test and to |
| E_S%PSLIN_Z_H | | | | | put CCs into Datapath register. |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (Sim with 1.1/0.8pF Z/N) Last Updated: 9/03/86 |
| Cl = 1.1/0.78 pF (Z/N) |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI1 + 15nS (N) emd, ebt ebt - PHI2 No Yes |
| PHI1 + 18nS (Z) emd - PHI3 pass in emd No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%PSLOUT_C_H | | | | | Buffered version of PSL CC bits. |
| E_S%PSLOUT_N_H | | | | | |
| E_S%PSLOUT_V_H |XXXXXXXXX==============================| Load from W_BUS. |
| E_S%PSLOUT_Z_H |====================XXXXXXXXX==========| Load from CC Logic. |
| | | | | | |
| Spice Ref (Block/Text): E_PSL_SIM (sim with 0.9pF) Last Updated: 9/03/86 |
| Cl = 0.89 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emd 24nS after ecl PHI4 mux in ecl No |
| Load Phase |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 168
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%Q0_BUF_L |=============================XXXXXXXXXX| Buffered version of Q(slave)<0> - Controls |
| | | | | | SMUL step. Waveform for SHR operation of |
| | | | | | Q Register. |
| Spice Ref (Block/Text): E_QREG_SIM (sim with 0.625pF) Last Updated: 9/03/86 |
| Cl = 0.63 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emd PHI4 + 24nS eac EARLY PHI1 ? ? |
| (when used with SHR) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%Q0_SHR_LD_H |\____________________________//========| Early SHR mechanism for Q0. Q0 is need |
| E_S%Q0_SHR_LD_L | | | | | earlier then E_S%Q_SHR_H allows - to |
| | | | | | control the SMUL step. |
| | | | | | |
| Spice Ref (Block/Text): E_QREG_SIM Last Updated: 2/19/86 |
| Cl = 0.21/0.28 pF (H/L) |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI4 emd PHI4 ctrl No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%Q_SHL_H |/=========\____________________________| Load Q(master) from SHL Q(slave) |
| E_S%Q_SHL_L | | | | | |
| E_S%Q_SHR_H | | | | | Load Q(master) from SHR Q(slave) |
| E_S%Q_SHR_L | | | | | |
| | | | | | |
| Spice Ref (Block/Text): E_QREG_SIM Last Updated: 9/03/86 |
| Cl = 1.88 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI1 emd PHI1 ctrl No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%QM_WSEL_H |/=========\____________________________| Load Q(master) from W_BUS |
| E_S%QM_WSEL_L | | | | | |
| | | | | | |
| Spice Ref (Block/Text): E_QREG_SIM Last Updated: 9/03/86 |
| Cl = 1.85 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc EARLY PHI1 emd PHI1 ctrl No No |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 169
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%QR31_BUF_H |XXXXXXXXXXX============================| Q(slave) bit 31, sent to ALU during UDIV |
| | | | | | Waveform for SHL operation of Q Register. |
| | | | | | |
| Spice Ref (Block/Text): E_QREG_SIM (sim with extracted cap) Last Updated: 9/03/86 |
| Cl = 1.42 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emd PHI1 + 27nS ead PHI3 mux in ead No |
| (when used with SHL) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%QR_ASEL_H |__/=========\__________________________| Read Q(slave) onto A_BUS |
| | | | | | |
| Spice Ref (Block/Text): E_QREG_SIM (sim with extracted cap) Last Updated: 9/03/86 |
| Cl = 3.15 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc Trail PHI1 by 5nS emd Early PHI1 No Yes |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%R_SHFT_H<32:0> Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: ebdec Used by: ebs |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%RAW_RN15_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: edtg Used by: edw |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%RN_H<3:0> |===================XXXXXXXXXXX=========| Buffered version of g_s%rn_h<3:0> |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 2/14/86 |
| Cl = 0.72 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| edtg BUFFERED erl Phi1 Drives reg cell No |
| G_S%RN_H Timing not crit |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 170
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%SEL_BYTE_CC_H |==========XXXXXXX======================| Select BYTE condition codes |
| E_S%SEL_FPA_CC_H | | | | | Select FPA condition codes |
| E_S%SEL_LONG_CC_H | | | | | Select LONG condition codes |
| E_S%SEL_SHFT_CC_H | | | | | Select SHIFTER condition codes |
| E_S%SEL_WORD_CC_H | | | | | Select WORD condition codes |
| | | | | | |
| Spice Ref (Block/Text): E_CC_DECODE_SIM (sim with 0.7pF) Last Updated: 9/03/86 |
| Cl = 0.73 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecd PHI2 + 19nS ecl PHI3 thru PHI1 No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| |
| E_S%SELECT_ALU_SHFT_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: ebdecm Used by: ebdc |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| |
| E_S%SELECT_SPUR_H Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: ebdecm Used by: ebdc |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| |
| E_S%SET_RESTART_H Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: erl Used by: erd |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 171
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%SH_DIR_H |===================XXXXXXXXXXXXX=======| |
| | | | | | |
| Spice Ref (Block/Text): E_BARREL_DEC_CON_MIB_SIM (0.85pF) Last Updated: 9/10/86 |
| Cl = 0.87 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ebdecm PHI4 + 3nS ebdecc By rising PHI1 Latch |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%SHFTVAL_H<4:0> |===================XXXXXXXXXXXXXXXXXXXX| |
| | | | | | |
| Spice Ref (Block/Text): E_BARREL_DEC_CON_MIB_SIM (0.58pF) Last Updated: 9/10/86 |
| Cl = 0.64 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ebdecm By PHI1 ebdecc By PHI1 Latch |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| |
| E_S%SHIFT_H Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: ebdecm Used by: ebdec, ebc |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| |
| E_S%SHIFT_DIR_H Timing not speced - Spice simulation crosses schematic boundary |
| E_S%SHIFT_DIR_L |
| |
| Driven by: ebdecc Used by: ebdec |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 172
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%SHL_ALU_H |___________________//=========\\_______| SHL ALU output (used in UDIV) |
| E_S%SHL_ALU_L | | | | | |
| | | | | | |
| E_S%SHR_ALU_H | | | | | SHR ALU output (used in SMUL) |
| E_S%SHR_ALU_L | | | | | |
| | | | | | |
| Spice Ref (Block/Text): E_ALU_SIM (look at sim for exact speed of signal) Last Updated: 9/03/86 |
| Cl = 2.2/2.6 pF (H/L) |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ear PHI3 ead PHI3 ctrl No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| |
| E_S%SMUL_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: eacm Used by: eac |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%SN_L<2:0> Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: edtg Used by: edw |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%SPUR_TO_W_H Timing not speced - Spice simulation crosses schematic boundary |
| E_S%SPUR_TO_W_L |
| Valid from PHI4 + 9nS to PHI1 + 11nS |
| Driven by: ebdc Used by: ebd |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%SV_H<4:0> Timing not speced - Spice simulation crosses schematic boundary |
| E_S%SV_L<4:0> |
| |
| Driven by: ebdecc Used by: ebdec |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 173
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%UDIV_ALU_C_H |=============================XXXXXXXXX=| ALU Carry bit used in UDIV Step |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM (sim with 0.27pF) Last Updated: 9/03/86 |
| Cl = 0.27 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecl PHI4 + 20nS eac Ideally LE PHI1 ? ? |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| |
| E_S%UDIV_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: eacm Used by: eac |
| |
^------------------------------------------------------------------------------------------------------------------+
| | | | | | |
| E_S%UNCOND_LD_PC_L |XXXXXXX================================| Unconditional Load of V&PC |
| | | | | | |
| Spice Ref (Block/Text): E_CC_DECODE_SIM (sim with 1.1pF) Last Updated: 9/03/86 |
| Cl = 0.75 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecd PHI1 + 18nS ebt PHI2 thru PHI3 No No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%UPD_PSLDP_CC_H |XXXXXXXX===============================| Datapath copy of PSL.CCs should be updated |
| | | | | | |
| Spice Ref (Block/Text): NOT SIMULATED Last Updated: 9/03/86 |
| Cl = 0.83 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecd LATE PHI1 emc PHI3 No No |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 174
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%UPDATE_SHADOW_SC_H |__________//XXXXXXXX\\_________________| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 2/14/86 |
| Cl = 1.93 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| edw Delayed ~1 & 2 & ~3 ebdecm Valid after 1 and low No No |
| Else must be low be 4 |
| Note For further details see Spice Schematic. Not speced since Spice Sims cross schematic boundary. |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%UPDATE_WSEL_H Timing not speced - Spice simulation crosses schematic boundary |
| E_S%UPDATE_WSEL_L |
| |
| Driven by: edw Used by: edw, edtg |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| |
| E_S%USE_DL_ZEXT_H Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: ebdcm Used by: ebdc |
| |
^------------------------------------------------------------------------------------------------------------------+
| | | | | | |
| E_S%USE_OLD_Z_H |==========XXXXXXX======================| Use Old Z function |
| | | | | | |
| Spice Ref (Block/Text): E_CC_DECODE_SIM (sim with 0.7pF) Last Updated: 9/03/86 |
| Cl = 0.68 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ecd PHI2 + 19nS ecl ENTIRE PHI1 No No |
| and PHI2+ |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 175
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%WB_PURE_H Timing not speced - Spice simulation crosses schematic boundary |
| E_S%WB_PURE_L |
| E_S%WB_SN_H |
| E_S%WB_SN_L |
| E_S%WB_SNP1_H |
| E_S%WB_SNP1_L |
| |
| Driven by: erd Used by: edw |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%WRITE_REG_H Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: edtg Used by: edw, edtg |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%WRITE_SC_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: erd Used by: edw |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%WSEL_15_8_HPG<14:0> Timing not speced - Spice simulation crosses schematic boundary |
| E_S%WSEL_31_16_HPG<14:0> |
| E_S%WSEL_7_0_HPG<14:0> |
| E_S%WSEL_HT<15:0> |
| |
| Driven by: edtg Used by: erf |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%WSEL_HW<7:0> Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: edw Used by: erf, <7> edw |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 176
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| E_S%Z_B_H | | | | | |
| E_S%Z_LW_H |=========XXXXXXXXXXXXXXXXXXXXXXXXXXXXX=| |
| E_S%Z_W_H | | | | | |
| | | | | | |
| Spice Ref (Block/Text): E_CC_LOGIC_SIM, E_ZERO_DET_SIM Last Updated: 9/03/86 |
| Cl = 0.91 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ezd PHI1 - 5nS (1.2pF) ecl LATE PHI4 mux in ecl No |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%ZD_15_8_L Timing not speced - Spice simulation crosses schematic boundary |
| E_S%ZD_23_16_L |
| E_S%ZD_31_24_L |
| E_S%ZD_7_0_L |
| |
| Driven by: ebd Used by: ezd |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%ZD_PHI4_L Timing not speced - Spice simulation crosses schematic boundary |
| |
| Driven by: ezd Used by: ebd |
| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%ZERO_15_8_L Timing not speced - Spice simulation crosses schematic boundary |
| E_S%ZERO_31_16_L |
| |
| Driven by: ebdc Used by: ebd |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ZERO_A0_H |////=========\_________________________| Zero A_BUS<0> for K.SEXT |
| E_S%ZERO_A1_TO_A31_H | | | | | Zero A_BUS<31:1> for K.SEXT and K1 |
| | | | | | |
| Spice Ref (Block/Text): E_MISC_CTRL_SIM (sim with extracted caps) Last Updated: 9/03/86 |
| Cl = 0.44/3.2 pF (A0/A1..) |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| emc PHI1 + 11/12nS emd PHI1 ctrl No Yes |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 177
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ZERO_A_H |XXXXXXXXXXXXXXX========================| |
| E_S%ZERO_B_H | | | | | |
| | | | | | |
| Spice Ref (Block/Text): E_BARREL_DEC_CON_SIM (0.43pF) Last Updated: 10/09/86 |
| Cl = 0.44 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ebdecc PHI1 + 11nS ebc Two gate delays No No |
| before 3 thru 3 |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| |
| E_S%ZERO_A_L Timing not speced - Spice simulation crosses schematic boundary |
| E_S%ZERO_B_L |
| |
| Driven by: ebdecm Used by: ebdecc |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ZERO_BYTEx_H |/////=========\________________________| Zero bytes on B_BUS (KMUX) |
| x is 0 through 3 | | | | | |
| | | | | | |
| Spice Ref (Block/Text): E_KMUX_SIM (sim with 3.0pF) Last Updated: 9/03/86 |
| Cl = 2.93 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ekc PHI1 + 13ns emd PHI1 ctrl No Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| E_S%ZERO_CONST_BITx_H |/////=========\________________________| Drive constants onto B_BUS (KMUX) |
| x is 0 through 7 | | | | | |
| | | | | | |
| Spice Ref (Block/Text): E_KMUX_SIM (sim with 3.0pF) Last Updated: 9/03/86 |
| Cl = 2.48 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| ekc PHI1 + 13ns emd PHI1 ctrl No Yes |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 178
EXECUTION (E) BOX
+----------+---------+---------+----------+
EBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^------------------------------------------------------------------------------------------------------------------+
| |
| E_S%ZERO_LA_H Timing not speced - Spice simulation crosses schematic boundary |
| E_S%ZERO_LB_H |
| |
| Driven by: ebc Used by: ebl |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 179
EXECUTION (E) BOX
3.18 Change Requests (ECO)
The following change requests have been reflected in this revision of the
spec:
o 5MAY06PIR.1
o 5JUN01PIR.1
o 5JUN11PEG.1
o 5JUL01AO.1
o 5JUL15PIR.1
o 5JUL18PIR.1
o 5JUL18PIR.2
o 5AUG20DS.1
o 5SEP19A0.2
o 5SEP19FF.1
o 5SEP25PEG.1
o 5OCT02PEG.1
o 5DEC20TFF.1
o 5DEC27DWA.1
o 6FEB19DWA.1
o 6FEB21DWA.1
o 6FEB21PEG.1
CVAX CPU CHIP DESIGN SPECIFICATION Page 180
EXECUTION (E) BOX
3.19 ISSUES
The following items are unresolved issues about the E BOX design. Note
that items followed by a [RESOLVED] have been decided, and are reflected
in the spec.
1. Should the VAX Restart Flag Bit be set if the PSL is modified?
Currently it is not.
ANS: 1-2-85 P.E.G. - ANSWER: NO.
CVAX CPU CHIP DESIGN SPECIFICATION Page 181
MEMORY (M) BOX
4 MEMORY (M) BOX
The Memory (M) Box is responsible for memory management in the CVAX. The
M Box description is divided into two sections: an M Box overview and a
detailed M Box functional description.
4.1 M Box Overview
The M Box Overview provides a general discussion of the operation of the M
Box. It describes the individual microinstructions which directly control
the M Box. A flow chart of the various events that can occur during an
address translation is presented. Also included is a chart of all the M
Box registers.
4.1.1 Introduction -
The M Box is responsible for memory management. Its primary function is
to translate virtual addresses into physical addresses and determine if
the process is allowed immediate access to memory. In determining access
the M Box checks to see if the process has the required privilege to
reference the requested page, if the page is swapped out, if a page is
being modified for the first time, if there is a length violation, and if
the reference crosses page boundaries. The M Box informs the microcode of
various exceptions by generating a microtrap and driving specified bits on
the Microtest bus.
The microcode can never request more than one longword per
microinstruction, and since a longword reference can be unaligned, the M
Box must determine if the memory reference requires more than one IDAL
transaction. On unaligned accesses the M Box will use VAP for addressing
the second longword of data, but VAP is not incremented when used for
unaligned accesses. When this occurs a single MEMORY REQUEST (MEM REQ)
microinstruction causes two bus cycles to occur. The M Box also contains
a byte rotator which can rotate the position of data bytes transferred
between the W Bus and the IDAL during unaligned accesses.
4.1.2 Microinstruction Control Of The M Box -
There are many types of microinstructions that control the M Box. The
microinstruction type that generates the most control of the M Box is the
MEMORY REQUEST (MEM REQ) type of microinstruction which causes memory
requests to occur. Other types of microinstructions, such as BASIC and
SPECIAL, also control the M Box and are used for reading and writing
registers in the M Box and for controlling the Microtest bus.
CVAX CPU CHIP DESIGN SPECIFICATION Page 182
MEMORY (M) BOX
4.1.2.1 Memory Requests -
The MEMORY REQUEST (MEM REQ) microinstructions cause various functions to
be executed in the M Box. The MEM FUNC (Memory Function) MIB<37:33> field
of the MEM REQ microinstruction specifies the type of function to be
performed. The table below lists all the memory request functions. The
privilege check and access mode for a virtual memory reference are
determined by the MREQ.ACC field MIB<30:28>. MREQ.ACC specifies if the
privilege check is read, write, AT=M, or none, and whether the access mode
is the current mode (in the partial PSL) or a mode stored in the MODE
register. If the access requested by the virtual memory reference
(privilege check/access mode) is not allowed by the protection code
associated with the page, then an access control violation will occur.
This will cause a microtrap if it is not a probe and traps are not
disabled.
MEMORY REQUEST FUNCTION FIELD DEFINITION
Reference Address VAP after
MIB<37:33> Function Type Source Reference
---------- --------- --------- ------- ---------
00 MREQ.VIRT.VA Virtual VA VA +4
04 MREQ.VIRT.VAP Virtual VAP VAP+4
08 MREQ.PHYS.VA Physical VA VA +4
0C MREQ.PHYS.VAP Physical VAP VAP+4
10 PROBE.VIRT.VA Virtual VA unchanged
14 PROBE.VIRT.VAP Virtual VAP unchanged
05 MREQ.VIRT.VAP.PTE Virtual VAP VAP+4
0D MREQ.PHYS.VAP.PTE Physical VAP VAP+4
0B MREQ.PHYS.VA.IPR Physical VA VA +4
0F MREQ.PHYS.VAP.INTVEC Physical VAP VAP+4
02 MREQ.VIRT.VA.LOCK Virtual VA VA +4
18 FPA - - unchanged
1D MXPR (Proc. Reg. Trans.) - - unchanged
1E MXPS0 (Spur Trans. 0) - - unchanged
1F MXPS1 (Spur Trans. 1) - - unchanged
All virtual references use the MREQ.ACC field to determine the privilege
and access modes to be checked against the value stored in the Protection
field of the TB entry.
MIB<30:28> Privilege Check Access Mode
---------- --------------- -----------
0 none current (PSL) <-- Arbitrary since no check is performed
2 read current (PSL)
3 read mode (MODE)
4 write current (PSL)
5 write mode (MODE)
6 AT=m current (PSL)
note: AT=m (Access-type = modify) means that the privilege check is write if AT=m,
otherwise check for read; the I BOX sends a signal (G_S%AT_EQ_MOD_H) to the
M Box indicating that AT=m.
CVAX CPU CHIP DESIGN SPECIFICATION Page 183
MEMORY (M) BOX
The DST field determines the destination control for that instruction.
MIB<27:26> Destination
---------- -----------
00 destination is bit bucket
01 destination is A-port select
10 destination is W[SN]
11 destination is B-port select
The RW field determines whether a READ or WRITE is performed for that MEM
REQ.
MIB<31> Read/Write
------- ----------
0 Read
1 Write
4.1.2.1.1 Microcode Restrictions -
The following is a list of microcode restrictions and general facts
concerning the use of the M Box.
1. All D-stream TB misses load the tag pointed to by the NLU and
clear the TB.V bit. The microcode must guarantee that after a
D-stream TB miss, if the PTE associated with the just loaded TAG
is to be brought into the TB, a READ PTE must occur before any
memory translations occur that could miss the TB (and load a
different TAG in the NLU).
2. A memory cycle immediately following a READ MREQ.PTE must use the
same PTE that was just written, as this is the only PTE that will
translate correctly in the very next cycle. If an MEM REQ
microinstruction does not follow a READ MREQ.PTE, then
prefetching must be disabled during the microcycle following a
READ MREQ.PTE to avoid an attempt to access a PTE other than the
one just written.
3. A BCS = MMGT.STATUS or BCS = MREF.STATUS during an MEM REQ that
loads the MMGT.STATUS register will use the value of MMGT.STATUS
from the previous microcycle for the BRANCH.
4. An instruction that cases on Status bits must not be capable of
trapping on a fault and modifying the Status bits being cased.
5. A WRITE changing the PSL current mode bits or a MXPS
WRITE[MODE<1:0>] can not be followed in the next cycle by a MREQ.
A prefetch can not occur in the cycle following a WRITE changing
the PSL current mode bits.
CVAX CPU CHIP DESIGN SPECIFICATION Page 184
MEMORY (M) BOX
6. ZAP.TB.IF.HIT or ZAP.TB can only be selected in the SPECIAL
microinstruction if prefetching is disabled.
4.1.2.1.2 Virtual -
Execute a READ (or WRITE) function. Use VA (or VAP) as address.
Translate using TB. Cross Page checking only occurs on VA references.
Check for none, READ, WRITE, or AT privilege. Note that on virtual
references with no privilege checking, the TB.V tag, and the PTE.V bit are
still examined. The PTE.M is checked during write access check. Data
length is given by the microinstruction and is either DL or LONG. DL is
the data length received from the I Box.
4.1.2.1.3 Virtual Lock -
Same as virtual but the BIU issues a READ LOCK (or WRITE UNLOCK) CYCLE
STATUS CODE on the CS pins.
4.1.2.1.4 Physical -
Execute a READ (or WRITE) function. Use VA (or VAP) as address. Do not
translate or update MEMORY MANAGEMENT STATUS REGISTERS; bypass TB. Data
length is either DL or LONG.
4.1.2.1.5 Probe References -
Probe references are used to determine if a memory data transfer will be
successful, ie, whether memory management will allow it. No data
transfers are done under any circumstances. The probes test reads and
writes of bytes using the Current (PSL) or the MODE bits as the mode for
access checking. VAP is unchanged. Probes can only take TB miss
microtraps. Probes do not take ACV/TNV microtraps because this would
result in an exception, and a probe is only a test of the success of a
memory reference. Cross Page and M=0 traps are disabled on probes.
MMGT.STATUS and MBOX.STATUS are loaded during probe microinstructions;
this allows the microcode to test whether there has been an access
violation, or a translation not valid.
4.1.2.1.6 Virtual PTE Reference -
Do a virtual access of memory for Read PPTE. Put the modified data into
the not last used entry (NLU) of the TB and set TB.V. VAP is incremented
by 4. The NLU pointer indicates the entry was not the last one to be used
CVAX CPU CHIP DESIGN SPECIFICATION Page 185
MEMORY (M) BOX
of the entries in the TB. The TAG will be overwritten on a READ PPTE with
a miss. Cross Page traps do not occur because microcode guarantees an
aligned reference always takes place.
4.1.2.1.7 Physical PTE Reference -
Do a physical access of memory for Read SPTE. Put the modified data into
the not last used entry (NLU) of the TB and set TB.V.
4.1.2.1.8 Read Interrupt Vector -
Execute an interrupt identify sequence. The decoded level is passed to
the bus via VAP. The TB is bypassed as in physical reads. In response to
this command, the memory system responds with the interrupt vector
received from the interrupting device. Microcode guarantees an aligned
reference always takes place. Force data length to word.
4.1.2.1.9 Internal Processor Register -
MREQ.PHYS.VA.IPR is the same as Physical but send out a IPR type in the CS
code and force a Cache Miss if a READ. Data Length is LONG. Microcode
guarantees that an aligned reference always takes place.
4.1.2.1.10 MXPS Transfer -
The MXPS Transfer is used for reading and writing the MAPEN register, and
writing MODE and MMGT.STATUS in the M Box via the W bus Spur.
4.1.2.1.11 MXPR Transfer -
The MXPR Transfer is used for reading and writing the SLR, P0LR, P1LR
registers in the M Box. When the register is the source the register
contents are read onto the B-bus. When the register is the destination
the register is written to from the W-bus.
4.1.2.1.12 FPA Transfer -
The FPA Transfer is used to Latch data off the IDAL and drive it onto the
W_Bus.
CVAX CPU CHIP DESIGN SPECIFICATION Page 186
MEMORY (M) BOX
4.1.2.2 Non Memory Request Microinstructions -
Besides the Memory Request type of microinstruction, a number of other
types of microinstructions and fields of microinstructions control the M
Box.
4.1.2.2.1 BCS Field -
The BCS field of the microinstruction is used to control writing to the
Microtest bus. Registers in the M Box selected by the BCS field are
PSL<26:24>, MBOX.STATUS, MMGT.STATUS, and MREF.STATUS.
4.1.2.2.2 B Field -
The B field of the SHIFT and BASIC microinstructions is used to read and
write VA, VAP, or VIBA.
4.1.2.2.3 MISC Field -
The MISC field is used to clear MMGT_TD (Trap Disable), set MMGT_REXE, or
write VA, VAP, or VIBA (in parallel with another operation), or
conditionally load VIBA based on the state of the BRANCH CONDITION signal
(G_S%BCOND_TRUE_H) from the E Box.
4.1.2.2.4 SPECIAL -
The MISC1 field of the SPECIAL microinstruction is used to invalidate all
TB entries (and clear REPROBE and MMGT_REXE), invalidate a TB entry if Hit
by the address in VA, or set MMGT.TD. Microcode will guarantee that
prefetching is disabled before any ZAP.TB or ZAP.TB.IF.HIT is executed.
4.1.2.2.5 BROADCAST -
If G_S%BRDCST_WBUS_H is asserted, then the M Box will latch the contents
of the WBUS during PH1 of the next cycle, and drive the latched data on
the IDAL during PH2 and PH3.
4.1.3 Translation Buffer Description -
The Translation Buffer provides virtual to physical address translations.
TB Hit - There is a TB hit if bits <31:9> of the virtual address
CVAX CPU CHIP DESIGN SPECIFICATION Page 187
MEMORY (M) BOX
undergoing translation match one of the tags in the TB and the TB.V stored
in the corresponding PTE is SET. When there is a TB hit, TB_MISS remains
de-asserted. The TB drives the physical address out onto the IDALs.
TB Miss - There is a TB miss if the REPROBE flag is not set and bits
<31:9> of the virtual address undergoing translation do not match any tag,
or they do match a tag and the TB.V bit stored in the corresponding PTE is
CLEARed. If there is a miss during a D stream translation, The TAG
pointed to by the NLU circuit is written, its TB.V bit is cleared, and a
TB miss microtrap is taken if the MMGT_TD (trap disable flag) is not set.
If there is a miss during an I stream prefetch, then no microtrap is
taken, the TAG is NOT written, VIBA is not incremented, and IB_FILL_ERR is
asserted.
4.1.4 Microcode Flows -
The following tables present an overview of various memory reference
sequences. The first table presents longword references, the second
presents references that use DL.
The microcode flows are presented in tabular form. Each line in the table
represents one machine cycle. First the MEM REQ microinstruction mnemonic
is given. If there is "----" in the microinstruction entry then that
indicates that the previous microinstruction is still being executed (as
would be the case if STALL was asserted before T50 of the previous cycle),
"xxxx" signifies that the next microinstruction is executing. Then the
source and destination fields are given. The following tables assume that
all READ cycles complete in one microcycle (which is the fastest allowed
by CVAX with a cache hit) and all WRITE cycles require three microcycles.
The term REGn indicates any register allowed in the source destination
field. 2ND_REF (internal to the M Box) and BM are the state of these
signals for that given cycle. The entries under the VA and VAP columns
are defined as the state of these registers at the beginning of the cycle.
STALL is the state of that signal at T50 for that cycle.
The term ROT refers to a byte rotator and RL is the rotator latch used
during unaligned references that cross longword boundaries. BM refers to
the byte mask; the four bits refer to byte3, byte2, byte1, byte0. The
term 'xxxx' indicates a don't care. Note that VA<7:0> and VAP<7:0> are
given in hex.
CVAX CPU CHIP DESIGN SPECIFICATION Page 188
MEMORY (M) BOX
4.1.4.1 Longword References -
microinstruction VA VAP
mnemonic S/D 2ND_REF STALL BM <7:0> <7:0> comments
ALIGNED LONGWORD READ
READ REG1 0 0 1111 10 xx DAL<--BIU addr latch<--PA[VA]; W-bus<--cache data;
xxxx xxxx x 0 xxxx 10 14 REG1<--W-bus;
ALIGNED LONGWORD WRITE
WRITE REG1 0 0 1111 10 xx DAL<--BIU addr latch<--PA[VA]; W-bus<--REG1;
(b) xxxx xxxx x 0 1111 10 14 DAL<--BIU data latch<--M Box latch<--W-bus;
(a) xxxx xxxx x 0 1111 xx xx DAL<--BIU data latch; ---> RDY
UNALIGNED LONGWORD READ
READ REG1 1 1 1100 12 xx DAL<--BIU addr latch<--PA[VA]; RL<-- ROT(cache data);
---- ---- 1 0 0011 12 16 DAL<--BIU addr latch<--PA[VAP]; W-bus<-- RL+ROT(cache data);
xxxx xxxx x x xxxx 12 16 REG1<-W-bus;
UNALIGNED LONGWORD WRITE
WRITE REG1 1 1 1100 12 xx DAL<--BIU addr latch<--PA[VA]; W-bus<-REG1;
---- ---- 1 1 1100 12 16 DAL<--BIU data latch<--M Box latch<--ROT(W-bus);
---- ---- 1 1 1100 12 16 DAL<--BIU data latch; --->RDY
---- ---- 1 0 0011 12 16 DAL<--BIU addr latch; BIU addr latch<--PA[VAP];
(b) xxxx xxxx x x 0011 xx xx DAL<--BIU data latch;
(a) xxxx xxxx x x 0011 xx xx DAL<--BIU data latch; ---> RDY
ALIGNED LONGWORD READ(WRITE) WITH TB_MISS
READ(WRITE) REG1 0 0 1111 10 xx DAL<--BIU addr latch<--xxxx; microtrap is forced; Uinstr. is aborted;
UNALIGNED LONGWORD READ(WRITE) WITH TB_MISS
READ(WRITE) REG1 1 1 0011 12 xx DAL<--BIU addr latch<--xxxx; microtrap is forced; Uinstr. is aborted;
notes: (a) during this cycle the DAL is busy (no instruction which uses the DAL can execute during this cycle)
(b) during this cycle the DAL and IDAL are busy (no instruction which uses the IDAL or DAL can execute during this cycle)
CVAX CPU CHIP DESIGN SPECIFICATION Page 189
MEMORY (M) BOX
4.1.4.2 Memory References That Use DL -
All of the above examples assumed that the data length was equal to LONG.
The following cases show what happens when DL is equal to a WORD and when
DL is equal to a QUADWORD. Note that when a byte or word is read from
memory, the upper bytes are zero extended by the E Box before the
destination register is loaded. When a QUADWORD transaction takes place,
it is convenient to use a MREQ using VA for the first reference and a MREQ
using VAP for the second reference.
microinstruction VA VAP
mnemonic S/D 2ND_REF STALL BM <7:0> <7:0> comments
ALIGNED READ, DL = WORD
READ REG1 0 0 0011 10 xx DAL<--BIU addr latch<--PA[VA]; W-bus<--cache data;
xxxx xxxx x x xxxx 10 14 REG1<-- 00+W-bus;
ALIGNED WRITE, DL = WORD
WRITE REG1 0 0 0011 10 xx DAL<--BIU addr latch<--PA[VA]; W-bus<-REG1;
(b) xxxx xxxx x x 0011 10 14 DAL<--BIU data latch<--M Box latch<--W-bus;
(a) xxxx xxxx x x 0011 xx xx DAL<--BIU data latch; ---> RDY
UNALIGNED READ, DL = WORD *
READ REG1 0 0 1100 12 xx DAL<--BIU addr latch<--PA[VA]; W-bus<--ROT(cache data);
xxxx xxxx x x xxxx 12 16 REG1<-- 00+W-bus;
UNALIGNED WRITE, DL = WORD *
WRITE REG1 0 0 1100 12 xx DAL<--BIU addr latch<--PA[VA]; W-bus<-REG1;
(b) xxxx xxxx x x 1100 12 16 DAL<--BIU data latch<--M Box latch<--ROT(W-bus);
(a) xxxx xxxx x x 1100 xx xx DAL<--BIU data latch; ---> RDY
ALIGNED READ USING DL WHERE DL = QUADWORD
READ REG1 0 0 1111 10 xx DAL<--BIU addr latch<--PA[VA]; W-bus<-- cache data;
READ REG2 0 0 1111 10 14 DAL<--BIU addr latch<--PA[VAP]; REG1<--W-bus; W-bus<-- cache data;
xxxx xxxx x x xxxx 10 14 REG2<--W-bus;
UNALIGNED READ USING DL WHERE DL = QUADWORD
READ REG1 1 1 1100 12 xx DAL<--BIU addr latch<--PA[VA]; RL<--ROT(cache data);
---- ---- 1 0 0011 12 16 DAL<--BIU addr latch<--PA[VAP]; W-bus<--RL+ROT(cache data);
READ REG2 1 1 1100 12 16 DAL<--BIU addr latch<--PA[VAP]; REG1<--W-bus; RL<-ROT(cache data);
---- ---- 1 0 0011 12 1A DAL<--BIU addr latch<--PA[VAP]; W-bus<--RL+ROT(cache data);
xxxx xxxx x x xxxx 12 1A REG2<--W-bus;
ALIGNED READ THAT CROSSES PAGE BOUNDRY, DL = QUADWORD
READ REG1 0 0 1111 FC xx microtrap is forced;
UNALIGNED READ WITH TB_MISS, DL = QUADWORD
READ REG1 1 1 1100 12 xx microtrap is forced; Uinstr. is aborted.
notes: (a) DAL-busy
(b) DAL-busy and IDAL-busy
* This word is unaligned in the sense that the lowest two address bits do
not equal 00. It is not unaligned in the sense that the word crosses a
CVAX CPU CHIP DESIGN SPECIFICATION Page 190
MEMORY (M) BOX
longword boundary.
4.1.5 Registers -
This section is a summary of the registers and latches located within the
M Box and the methods available for reading and writing these storage
elements.
+-----------------------------------------------------------------------------------------------------------------------+
| Register or latch | Bits | Access | Addressing Method | Bus |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| VA | <31:0> | read | BASIC/SHIFT [B-port = VA] | B-bus |
| | | write | BASIC/SHIFT [B-port = W-bus = VA] | W-bus |
| | | write | MISC.WRITE.VA | W-bus |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| VAP | <31:0> | read | BASIC/SHIFT [B-port = VAP] | B-bus |
| | | write | BASIC/SHIFT [B-port = W-bus = VAP] | W-bus |
| | | write | MISC.WRITE.VAP | W-bus |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| VIBA | <31:0> | read | BASIC/SHIFT [B-port = VIBA], | B-bus |
| | | | Bits <1:0> read only zero | |
| | <31:2> | write | BASIC/SHIFT [B-port = W-bus = VIBA] | W-bus |
| | <31:2> | write | MISC=IF.BCOND.LOAD.V&PC | W-bus |
| | <31:2> | write | MISC=IF.BCOND.LOAD.V&PC.TRAP | W-bus |
| | <31:2> | write | MISC=LOAD.V&PC | W-bus |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| P0LR | <30:0> | read | MEM REQ MXPR [P0LR] | B-bus |
| | <30:9> | write | MEM REQ MXPR [P0LR] | W-bus |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| P1LR | <30:0> | read | MEM REQ MXPR [P1LR] | B-bus |
| | <30:9> | write | MEM REQ MXPR [P1LR] | W-bus |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| SLR | <30:0> | read | MEM REQ MXPR [SLR] | B-bus |
| | <30:9> | write | MEM REQ MXPR [SLR] | W-bus |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| MMGT.STATUS | <2:0> | read | BCS = MMGT.STATUS | uTest-Bus<2:0> |
| | | write | Written with status during all MEM REQ's | logic |
| | | | MMGT.STATUS <2:0> is frozen if REPROBE set | |
| | | write | MEM REQ MXPS [MMGT.STATUS] | W-Spur<2:0> |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| MBOX.STATUS | <2:0> | read | BCS = MBOX.STATUS | uTest-Bus<2:0> |
| | | write | Written with status during all MEM REQ's | logic |
| | | | MBOX.STATUS <2:0> is frozen if REPROBE set | |
| | | | MBOX.STATUS <2> is frozen if MMGT_TD set | |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| MREF.STATUS | <0> | read | BCS = MREF.STATUS | uTest-Bus<0> |
| | | | ( NAND of MMGT.STATUS<2:0> ) | |
| | <1> | read | BCS = MREF.STATUS | uTest-Bus<1> |
| | | write | Set by IB_FILL_ERR asserted by BIU | |
| | | write | Cleared by IB_FILL_REQ | |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| PSL | <26:24> | read | BCS = PSL 26-24 | uTest-Bus<2:0> |
CVAX CPU CHIP DESIGN SPECIFICATION Page 191
MEMORY (M) BOX
| | | write | A-port = W-bus = PSL (LOAD_PSL=1) | W-Bus<26:24> |
| | | | shadows full PSL | |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| MODE | <1:0> | write | MEM REQ MXPS [MODE] | W-Bus Spur |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| MAPEN | <0> | read | MEM REQ MXPS [MAPEN] | W-Bus Spur |
| | | write | MEM REQ MXPS [MAPEN] | W-Bus Spur |
| | | | cleared by RESET pin | |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| REPROBE | <0> | | Cleared by: | |
| | | | (a) IID_LD | |
| | | | (b) MEM REQ | |
| | | | (c) SPECIAL MISC1=ZAP.TB | |
| | | | Set by SPECIAL MISC1=SET.REPROBE | |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| MMGT_REXE | <0> | | Cleared by: | |
| | | | (a) IID_LD | |
| | | | (b) MEM REQ | |
| | | | (c) SPECIAL MISC1=ZAP.TB | |
| | | | Set by MISC field=SET.REEXECUTE | |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| MMGT_TD | <0> | | Cleared by MISC field=CLR.MMGT.TD | |
| | | | Set by hardware if a mmgt microtrap (other than XPAGE) |
| | | | occurs during MREQ | |
| | | | Set by SPECIAL MISC1=SET.MMGT.TD | |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| TAG[15:0] | <31:9> | write | TAG[NLU] written on a D stream TB Miss | Compare-bus |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
| PTE[15:0] |<29:9,7:3,1>,TB.V | PTE[NLU] Written from IDAL during MREQ PTE |
| | | | TB.V[15:0] cleared by SPECIAL MISC1=ZAP.TB |
| | | | TB.V[NLU] set by MREQ PTE with no access violations |
| | | | TB.V[NLU] cleared by TB MISS |
| | | | TB.V[HIT] cleared by: |
| | | | (a) SPECIAL MISC1=ZAP.TB(HIT).IF.HIT |
| | | | (b) hit with PTE.V=0 ;TNV does not |
| | | | have to occur (to kill TB.V on probes) |
+---------------------+-----------+---------------+----------------------------------------------+----------------------+
4.2 Function Descriptions
The major function blocks of the M Box include the central
microinstruction decoding logic, the memory address logic for producing
the starting address for memory transactions, the TB for translating
virtual addresses into physical addresses, the access logic for assuring
that memory is protected and access is allowed to translated addresses,
the microtrap logic for flagging memory management conditions requiring
trap routines to correct them, unaligned/multiword reference logic for
controlling IDAL data formatting and forcing, IDAL second cycles, length
checking logic, data latch and byte rotator.
CVAX CPU CHIP DESIGN SPECIFICATION Page 192
MEMORY (M) BOX
The M Box passes E Box data as well as virtual or physical addresses to
the IDAL. Whenever addresses are delivered the BIU operand size logic
transmits a two bit size code on the IDAL as well.
4.2.1 Memory Address Logic -
The Memory Address Logic consists of the memory address registers, a
longword incrementer, and associated control for supplying virtual
addresses to the TB or physical addresses to the IDAL. The Memory Address
Logic consists of the following blocks.
4.2.1.1 VA (Virtual Address) Register -
The VA is a longword register used to hold the initial address for memory
references. The address may be virtual or physical.
The VA register is never incremented.
The VA register is explicitly read and written via the BASIC and SHIFT
microinstructions when B-port select = VA. It is also written when the
MISC field = WRITE.VA.
STALL inhibits the writing of VA.
4.2.1.2 VAP (VA Prime) Register -
The VAP is a longword register used during unaligned memory references,
multi-word memory sequences, and Memory Management microtrap processing.
The M Box selects the VAP register during MREQ microinstructions if the
request uses VAP as the address source or during the second half of an
unaligned data reference.
The VAP register is incremented during MREQ microinstructions, EXCEPT
during MREQ PROBE, MXPS, MXPR, FPA, and the second bus cycle of an
unaligned reference (to prevent two increments in an unaligned), or a
microtrap request (to preserve VAP for when the microinstruction is
retried after the microtrap). The +4 adder requires one microcycle to
add; VAP is loaded at the beginning of the next microcycle.
The VAP register is explicitly read and written via the BASIC and SHIFT
microinstructions when the B-port select = VAP (written when WBUS=VAP).
It is also written when the MISC field = WRITE.VAP.
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MEMORY (M) BOX
4.2.1.3 VIBA (Virtual Instruction Buffer Address) Register -
The VIBA is a longword register used to hold the address of the
instruction stream that is being prefetched. IB Fills use the VIBA
register for the instruction address. The VIBA register is selected if
the current microinstruction is not a MEM REQ or BRDCST_WBUS, and
IB_FILL_REQ is asserted, but GS%ONE_SLOT_FREE_H was not asserted in the
previous microcycle (i.e. on a cache hit during a prefetch, the I Box
can't deassert IB_FILL_REQ in time to prevent a prefetch in the very next
cycle, so ONE_SLOT_FREE is sent to prevent prefetching in the very next
cycle)
The VIBA register is incremented by four if a memory management violation
does not occur during the prefetch. Since a load from the VA Adder and a
microcode write to VIBA may occur at the same time in the cycle, the
explicit write always takes precedence. The M Box determines when VIBA
will be written and sends WILL_LOAD_VIBA to the BIU. If the BIU receives
WILL_LOAD_VIBA then IB_DATA_PRS is inhibited for any prefetch currently in
progress. The potential conflict occurs during a BRANCH microinstruction.
The VIBA register is explicitly read and written via the BASIC and SHIFT
microinstructions when the B-port select = VIBA (VIBA bits <1:0> are
always read zero). It is also written via a BRANCH microinstruction when
BCS = IF.BCOND.LOAD.V&PC, or BCS = IF.BCOND.LOAD.V&PC.TRAP, and the E Box
indicates that specified branch conditions are met, or when BCS =
LOAD.V&PC.
Prefetches from VIBA are guaranteed to be aligned by hardware
(VIBA<1:0>=00).
4.2.1.4 + 4 Adder -
The 32-bit VA adder is used to increment longword addresses from VA, VAP
or VIBA by four. The result can be loaded into the VAP or VIBA register.
4.2.2 TB -
The Translation Buffer is a 32 entry fully associative memory management
array for fast virtual to physical address translation and supplying
information to the Access Logic for page protection.
The TB is utilized in the following three ways:
1. TB access - This is the normal virtual to physical address translation
process which results in the driving of the physical address onto the
IDALs. In the case of an TB Hit, a portion of the PTE is sent to the
Access Logic to determine whether the access should be allowed. This
process is described in the TB Data Path.
2. TB Fill from Memory - This operation loads a new PTE into the TB from
CVAX CPU CHIP DESIGN SPECIFICATION Page 194
MEMORY (M) BOX
Memory as a result of a Read PTE. This process is described in the TB
Read/Write Control block.
3. Invalidate - This operation invalidates one or all of the PTEs. It is
described in the TB Invalidate Logic block. When TB.V is CLEAR the state
of the rest of the PTE is irrelevant. The SPECIAL MISC1=ZAP.TB
microinstruction causes all TB.V bits to be cleared. The SPECIAL
MISC1=ZAP.TB(HIT).IF.HIT does a TB lookup using VA and invalidates any TB
entry hit.
4.2.2.1 PTEs -
The CVAX_PTEs are stored in the TB in a modified format. The unmodified
PTEs, corresponding to the format in memory, are called VAX_PTEs because
the field assignments correspond to those defined in the SRM.
The unmodified and modified PTE's are shown below.
VAX_PTE (Unmodified PTE)
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|P| |P|XXXXXXXXX| |
|T| PROT |T|XXXXXXXXX| PFN |
|E| |E|XXXXXXXXX| |
|.| |.|XXXXXXXXX| |
|V| |M|XXXXXXXXX| |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
CVAX_PTE (Modified PTE)
2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+ +-+
| | | |P|P| | |
| | | |T|T| |T|
| | | |E|E| |B|
| PFN | | PROT |.|.| |.|
| | | |M|V| |V|
| | | | | | | |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+ +-+
PTE.V is the PTE Valid bit. It governs the validity of the Modify (M) bit
and the Page Frame Number (PFN). When PTE.V = 1, M and PFN are valid;
when PTE.V = 0, M and PFN are reserved. The PTE.V bit is not altered when
PTEs are read from memory into the TB.
PROT is the PTE Protection code. This field is always valid in the
VAX_PTE but is only valid in the CVAX_PTE if the TB.V is valid. The PROT
field describes the accessibility (read, write, no access) of the given
page for each mode (kernel, executive, supervisor, user). The VAX_PTE
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MEMORY (M) BOX
codes are partially decoded before being stored in the CVAX_PTE, the table
below shows how the CVAX_PTE Protection field is decoded from the VAX_PTE
ACCESS
VAX_PTE CVAX_PTE K E S U
0000 0000 0000 - - - -
0001 0000 0000 - - - -
0010 1000 1000 RW - - -
0011 1000 0000 R - - -
0100 1111 1111 RW RW RW RW
0101 1100 1100 RW RW - -
0110 1100 1000 RW R - -
0111 1100 0000 R R - -
1000 1110 1110 RW RW RW -
1001 1110 1100 RW RW R -
1010 1110 1000 RW R R -
1011 1110 0000 R R R -
1100 1111 1110 RW RW RW R
1101 1111 1100 RW RW R R
1110 1111 1000 RW R R R
1111 1111 0000 R R R R
PTE.M is the PTE Modify bit. If PTE.M = 1, the page has been recorded as
modified and if PTE.M = 0 the page has not been recorded as modified. It
is used only if PTE.V = 1. It is SET by microcode on a valid, write
access check.
PFN is the Page Frame Number, which is the upper 21 bits of the physical
address. This page address is valid only if PTE.V = 1.
TB.V is the TB Valid bit. There is a TB.V bit associated with each PTE.
The TB.V bit is not part of the PTE or TAG but is in the control logic.
When TB.V = 1, the CVAX_PTE entry is valid and corresponds to a VAX_PTE
entry. When TB.V = 0, the entry is invalid. A SPECIAL microinstruction
may be used to invalidate the entire TB. There is a TB hit when there is
a tag match and the TB.V bit associated with the PTE corresponding to that
tag is SET. When there is an TB hit but PTE.V = 0, hardware clears the
TB.V bit associated with the accessed PTE. When a PTE is read from memory
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MEMORY (M) BOX
into the TB via a MREQ PTE, TB.V is set by the M Box.
4.2.2.2 NLU -
When a D stream TB_MISS occurs, a new tag must be written with bits <31:9>
of the virtual address that resulted in a miss. This new tag must be
written over an existing tag entry in the TB. Statistics show that the
least recently used entry is the best one to replace; however the control
logic required to implement this algorithm is rather complex. A much
simpler approach to implement is the not last used (NLU) algorithm, which
which has only slightly degraded performance from that of LRU. The NLU
circuit merely guarantees that its pointer is not pointing at the last TB
entry to be used. This is accomplished by moving the pointer if it is
pointing to the PTE/TAG pair that has just been hit. Thus the pointer
rotates to the next sequential TB entry (PTE/TAG pair) each time the entry
it is presently pointing to is hit, and will replace the entry it is
pointing to if a TB miss occurs. Both D stream and I stream hits cause
the NLU to cycle. However, an I stream miss does not cause the PTE/TAG
entry, pointed to by the NLU, to be replaced. RESET forces the NLU
POINTER to a particular PTE/TAG pair, while clearing the NLU POINTER at
all other PTE/TAG locations.
4.2.2.3 TB Data Path -
The TB data path consists of 32 TB entries (which can be used for both I
and D stream), plus logic to facilitate data formatting and transfers
described below. Each TB entry consists of a 23-bit Tag/Comparator
register (CAM), a 31-bit PTE register (21-bits for PFN, 8-bits for PROT, 1
for PTE.V and 1 for PTE.M), and a TB.V bit.
If the Memory Management Enable (MME) bit of the MAPEN register is CLEAR,
or if the reference is physical, then the TB is turned off and the virtual
address is transmitted as the physical address. Otherwise, a TB access is
performed as described below.
Note that a TB hit requires that two conditions be met: first that the
TAG and the appropriate field of the virtual address agree, and second
that the TB.V bit of the CVAX_PTE pointed to by the TB_TAG is SET.
4.2.2.3.1 I Stream Access -
Whenever the microinstruction is not a MEM REQ or BRDCST_WBUS, MMGT_TD=0,
IB_FILL_REQ is asserted and ONE_SLOT_FREE was not asserted in the previous
cycle, and M_STALL is not asserted, the TB attempts an address translation
using VIBA. M_STALL is generated by the BIU whenever the arbitration
logic has determined that the IDAL will not be available. IB_FILL_REQ is
generated by the I Box whenever prefetch data is desired. Even though the
TB attempts a translation, a prefetch will not occur (address strobe will
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MEMORY (M) BOX
be inhibited) if the translation results in IB_FILL_ERR being asserted
(BIUNOP will be asserted), or M_STALL is asserted before internal clock
Phase 2.
4.2.2.3.1.1 I Stream TB Hit -
During a virtual I stream access, the TAGS are compared to bits <31:9> of
the VIBA register. If the comparison is successful and TB.V is SET, there
is a TB hit and the NLU is cycled (if it was pointing to the tag that was
hit, its pointer will be moved). A physical address composed from the
CVAX_PTE and VIBA<8:0> is passed to the IDAL. The CVAX_PTE is compared
with PSL<25:24>, and read access check is performed, to determine if the
access is allowed or whether the IB_FILL_ERR signal should be asserted.
No microtraps are ever taken; MMGT.STATUS and MBOX.STATUS in the Access
Logic are not altered. If the access is allowed VIBA is incremented.
4.2.2.3.1.2 I Stream TB Miss -
If the comparison was unsuccessful, or if the tag comparison was
successful but TB.V is CLEAR (the CVAX_PTE may not correspond to the
VAX_PTE), if PTE.V is not asserted or if an access violation occurs, then
the signal IB_FILL_ERR is sent to the I Box to disable prefetching and
VIBA is not incremented. No microtraps occur because the data being
prefetched may not be used. Only when the prefetcher eventually runs out
of valid data does the microcode force an I stream related memory
management fault.
4.2.2.3.2 D Stream Access -
Besides I stream accesses described above, the TB is also activated
whenever the microinstruction is a virtual MREQ, and MME is enabled, and
the IDAL is not busy, the exception being that PROBES execute even if the
IDAL is busy.
4.2.2.3.2.1 D Stream TB Hit -
On a D stream translation, the TAGS are compared to bits <31:9> of either
the VA or the VAP register, depending on the type of memory request. If
the comparison is successful and TB.V is SET, there is a TB hit. The NLU
is cycled (if the entry pointed to is hit). For a TB hit, a physical
address is passed to the IDAL as in the I stream case. The CVAX_PTE
protection field is compared with PSL<25:24> or MODE<1:0> to determine if
the access is allowed or whether a MMGT_TRAP should be issued and a Memory
Management microtrap taken.
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MEMORY (M) BOX
4.2.2.3.2.2 D Stream TB Miss -
If the comparison was unsuccessful, or if there was a successful
comparison but TB.V was CLEAR (the CVAX_PTE may not correspond to the
VAX_PTE), then a TB_MISS occurs. A tag is written when a D stream miss
occurs. If MMGT_TD = 0, REPROBE = 0, and BIU_TRAP is not asserted, then a
TB_MISS microtrap occurs.
4.2.2.3.3 TB Data Formatting -
This logic properly formats addresses delivered to the IDAL.
4.2.2.3.3.1 TB Bypasses -
If the MME bit of the MAPEN register is CLEAR, or if the MREQ is physical,
then the contents of one of the address registers (VIBA, VAP, or VA), bits
<29:0>, are passed to the IDAL. The operand size bits are placed on
<31:30> by the Memory Operand Size Logic in the BIU. The NLU logic,
memory management status registers, and memory management trap logic are
all disabled.
4.2.2.3.3.2 TB Accesses -
Whenever there is a TB hit, the physical address must be constructed and
driven onto the IDAL during the address portion of the cycle. The
physical address is built as follows. The upper two bits of the IDAL (the
operand size of the request) are driven by the Memory Operand Size Logic
in the BIU. The next 21 bits are the page frame number (PFN) and are
driven by bits <29:9> of the CVAX_PTE. The low nine bits of the IDAL are
driven from the selected address register, bits <8:0>. The protection
(PROT) field is compared against either PSL<25:24> or MODE<1:0> and
whether the reference is a READ or WRITE. If the MREQ.ACC field of the
microinstruction specifies NONE, access is always granted.
4.2.2.4 TB Fills From Memory -
Memory fills to the TB are performed during Read PTE microinstructions.
The TB fill happens during the execution of that microinstruction.
During a Read PTE, the NLU pointer identifies the CVAX_PTE to be written.
The associated tag was written when the D Stream TB miss occurred. The
CVAX_PTE is written from the IDAL via a hardwired rotator and the access
decoder logic.
Whenever the TB is loaded from memory, the TB.V bit is set by hardware,
indicating that the entry is valid.
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MEMORY (M) BOX
If an ACV/TNV or TB miss is detected during a READ PTE, the M Box asserts
BIU_NOP, a TB fill does not occur and TB.V is not set.
4.2.2.5 TB Invalidate Logic -
The TB entries may be invalidated (the TB.V bits cleared) either
collectively or individually. The reason for marking entries invalid is
to prevent TB hits.
The SPECIAL microinstruction is used to invalidate the entire TB (via
MISC1 = ZAP.TB). MISC1=ZAP.TB(HIT).IF.HIT invalidates the TB location hit
by VA (this type of microinstruction must not allocate TAG entries on
misses or take any MMGT traps). When TB entries are loaded from memory,
they are marked valid (TB.V is SET) by the M Box.
When there is an TB Hit but PTE.V is not asserted, hardware clears the
TB.V bit in the accessed PTE to prevent future incorrect TNV microtraps.
Since the software can validate a VAX_PTE without notifying the hardware,
unless the TB entry is replaced with an updated version of the CVAX_PTE,
TB hits with TNV microtraps will continue to occur (at that TB location)
even after the VAX_PTE in memory has become valid. Thus TB.V is cleared
by hardware to cause a TB Miss to occur and a new entry to be loaded in
the TB. Note that I stream references cannot cause TNV or any other
microtrap.
4.2.2.6 TB Miss Logic -
If the microinstruction is a virtual MREQ, REPROBE is not set, and memory
management is enabled, and there is no TB hit, then TB_MISS is asserted.
If a memory reference using VIBA is attempted, and memory management is
enabled, and there is no TB hit, then TB_MISS is asserted.
TB_MISS is asserted only if there is no match in the TB. A match means
that the TAG comparison was successful and that the selected CVAX_PTE TB.V
bit was SET.
4.2.2.7 TB Summary -
! No TB translation attempted
If NOT(MME) OR PHYSICAL MREQ
Then
If VIBA is the selected address source
Then
IDAL <== PA[<31:30> = 11, <29:0> = VIBA<29:0>]
If VAP is the selected address source
Then
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MEMORY (M) BOX
IDAL <== PA[<31:30> = 11, <29:0> = VAP<29:0>]
If VA is the selected address source
Then
IDAL <== PA[<31:30> = 11, <29:0> = VA<29:0>]
Note: PA<31:30> are driven to there correct value by the BIU when written
to the DAL. They are driven to 11 so that the IDAL does not just float.
! I Stream TB translation attempted
If MME AND NOT(MREQ) AND IB_FILL_REQ AND NOT MMGT_TD
Then
If TB Hit ! TB Hit
Then
IDAL <== PA[<31:30> = 11, <29:9> = CVAX_PTE<29:9>, <8:0> = VIBA<8:0>];
If no TB Hit ! TB Miss
Then
Assert IB_FILL_ERROR
! D Stream TB translation attempted using VAP as the address source
If MME AND (MREQ using VAP OR second half of unaligned reference)
Then
If TB Hit ! TB Hit
Then
IDAL <== PA[<31:30> = 11, <29:9> = CVAX_PTE<29:9>, <8:0> = VAP<8:0>];
If no TB Hit ! TB Miss
Then
TB_TAG[NLU] <== VAP<31:9>
TB_MISS, TB MISS MICROTRAP
! D Stream TB translation attempted using VA as the address source
If MME AND MREQ using VA
Then
If TB Hit ! TB Hit
Then
IDAL <== PA[<31:30> = 11, <29:9> = D_STREAM_CVAX_PTE<29:9>, <8:0> = VA<8:0>];
If no TB Hit ! TB Miss
Then
TB_TAG[NLU] <== VA<31:9>
TB_MISS, TB MISS MICROTRAP
! TB Fill from Memory, D Stream only
If Read PTE AND no access violation ! Read SPTE or PPTE
Then
CVAX_PTE[NLU] <== [<29:9>=IDAL<20:0>, PROT=IDAL<30:27>(decoded),CVAX_PTE.V=IDAL<31>],CVAX_PTE.M=IDAL<26>;
CVAX CPU CHIP DESIGN SPECIFICATION Page 201
MEMORY (M) BOX
! TB Invalidate
If SPECIAL AND (MISC1 = ZAP.TB) ! All entries invalidated
Then
CVAX_PTE[0:31] TB.V = 0
If SPECIAL and (MISC1 = ZAP.TB(HIT).IF.HIT) ! invalidate entry HIT by VA
Then
CVAX_PTE[HIT] TB.V = 0
4.2.3 Access Logic -
The Access Logic function determines if the memory reference request
produces an access violation. It is made up of the following blocks.
4.2.3.1 Privilege Check Logic -
The Privilege Check Logic compares the CVAX_PTE protection code bits to
the bits specified by the MREQ.ACC field and then determines whether or
not there is a privilege violation.
The Privilege Check Logic compares the PSL.CURM (the two CURRENT MODE bits
from the PSL<25:24>) or MODE<1:0> with the Protection Code (PROT) to
determine whether Read or Write Access is allowed to the addressed page
for the given memory request. Read Access is granted whenever Write
Access is granted. If the MREQ.ACC field of the microinstruction
specifies NONE, then access is always granted.
A privilege violation occurs if a Read Access Check is requested and no
Read Access is allowed, or if a Write Access Check is requested and no
Write Access is allowed.
Note that Write Access is independent of PTE.M. However if the PTE.M is
not set when a Write Access is determined, and MMGT_TD is cleared, then
the memory management microtrap M=0 is taken to set PTE.M in the PTE
stored in memory and in the modified version in the CVAX_PTE.
A privilege violation during IB Fills can be determined by checking for a
Read Access and PSL.CURM when fills are taking place.
If the MME bit in the MAPEN register (bit 0) is clear then privilege
checking is disabled. If MME is set and the reference is to reserved
address space (VA<31:30>=11), then a length violation occurs.
4.2.3.2 Length Check Logic -
The length check logic consists of three registers and a subtracter. The
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MEMORY (M) BOX
three registers are the System Length Register (SLR), Process Space 0
Length Register (P0LR), and Process Space 1 Length Register (P1LR).
During a virtual memory request the upper two bits of the virtual address
select one of the three length registers. The selected register is
compared against the page frame number (PFN) of the virtual address. This
comparison is performed by the length subtractor. For P0 and System
address space, length violations occur if the PFN is greater than or equal
to the associated length register. For P1 space, length violations occur
if the PFN is less than the P1LR. For reserved system space
(VA<31:30>=11), length violations always occur.
4.2.3.3 Inhibit IB Fill Logic -
When prefetching is halted and data is needed by the instruction buffer,
microroutines are entered which load VIBA into VA and do a MREQ to bring
the VAX_PTE into the TB if it is not already there and check for ACVs and
TNVs. Microtraps are enabled. The result of this MREQ is not stored.
Prefetching is restarted only if there is no ACV or TNV.
This guarantees that no ACV or TNV will occur when prefetching is
restarted. However, there are other cases where an ACV or TNV may occur
when VIBA is used. If mapping VIBA results in a TB Miss, ACV, or TNV,
IB_FILL_ERROR and BIU_NOP are asserted, but since the microinstruction is
allowed to continue MMGT_TRAP and STALL are not asserted. No memory
reference is started and VIBA is not incremented.
4.2.3.4 MMGT.STATUS -
The MMGT.STATUS register contains three status bits. MMGT.STATUS is
loaded on every DEMAND Virtual MREQ, including PROBE, unless REPROBE is
set.
MMGT.STATUS<2> = 0 for ACV, 1 for TNV or TB miss or reference ok
MMGT.STATUS<1> = 0 for ACV or TNV or TB miss, 1 for reference ok
MMGT.STATUS<0> = 0 for ACV or TNV, 1 for TB miss or reference ok
------------- ACV (access violation)
| ---------- TNV (translation not valid)
| | ------- TB-miss
| | | ---- Reference OK
| | | |
V V V V
MMGT.STATUS<2> 0 1 1 1
MMGT.STATUS<1> 0 0 0 1
MMGT.STATUS<0> 0 0 1 1
NOTE: reference ok means that there was not a ACV/TNV, and there was not
a TB miss.
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MEMORY (M) BOX
With the above encoding, four of the legitimate values of MMGT.STATUS
(000, 100, 101,111) are generated automatically by hardware, and the
others are generated within the memory management flows. All are unique:
MMGT.STATUS<2:0> = 000 for process ACV (hardware) <-
001 for process length violation (microcode)
010 for ppte ACV - impossible PER VAXB ECO
011 for ppte length violation (microcode)
100 for process TNV (hardware) <-
101 for TB miss (hardware) <-
110 for ppte TNV (microcode)
111 for reference ok (hardware) <-
MMGT.STATUS can be accessed as a case branch or written with a MXPS
Transfer. When accessed as a case branch, its three bits are mapped
directly onto the Microtest Bus. When written via MEM REQ MXPS
[MMGT.STATUS], MMGT.STATUS<2:0> are written from W_Bus<2:0>.
A BCS = MMGT.STATUS or BCS = MREF.STATUS during a MREQ that loads the
MMGT.STATUS register will use the value of MMGT.STATUS from the previous
microcycle for the BRANCH.
The definition of "memory reference ok" is MMGT.STATUS<2:0> = 111 or
MREF.STATUS<0> = 0. These codes are used for testing certain branch
conditions.
PROBE microinstructions must exercise the TB and Access Logic to determine
if the CVAX_PTE is present and access is permitted. PROBE
microinstructions take TB miss but do not take ACV/TNV, M=0, or cross page
microtraps. MMGT.STATUS is loaded during probe microinstructions. The
result of a PROBE is determined by examining MMGT.STATUS.
MMGT.STATUS is NOT updates during prefetching.
MMGT.STATUS is NOT updated if REPROBE is set.
MMGT.STATUS is NOT updated if MME=0.
MMGT.STATUS is NOT updated if MREQ PHYS.
MMGT.STATUS is NOT updated if (M_STALL AND NOT PROBE) is asserted.
MMGT.STATUS is NOT updated if STALL is asserted by another box.
When set MMGTTD disables prefetching, inhibits further TB Miss, ACV/TNV,
cross page or M=0 microtraps (NOT, however, bus error microtraps). With
memory management traps disabled, an M=0 microtrap situation is ignored
completely, and the memory access completes normally; however a TB miss,
ACV/TNV, and cross page situation will cause the M Box to perform a NOP,
while updating MMGT.STATUS. When set REPROBE suppresses the execution of
the next MREQ. No TB lookup occurs; MMGT.STATUS and MBOX.STATUS are not
updated.
4.2.3.5 MBOX.STATUS -
This three bit register is loaded during all DEMAND virtual MREQ
microinstructions, unless REPROBE is set. If MMGT.TD is set
CVAX CPU CHIP DESIGN SPECIFICATION Page 204
MEMORY (M) BOX
MBOX.STATUS<2> is frozen.
MBOX.STATUS<2> = 0 NOT Write Check
1 Write Check
MBOX.STATUS<1:0> = 00 P0 Space Reference with no length violation
01 P1 Space Reference with no length violation
10 System Space Reference with no length violation
11 Length Violation or Reserved Space Reference
The contents of this register are tested by microcode using BCS =
MBOX.STATUS.
A length error will always cause a MISS of the TB and during the MISS
flows the microcode cases on the MBOX.STATUS register to detect a length
error.
MBOX.STATUS is NOT updated during prefetching.
MBOX.STATUS is NOT updated if REPROBE is SET.
MBOX.STATUS is NOT updated if MME=0.
MBOX.STATUS is NOT updated in MREQ PHYS.
MBOX.STATUS is NOT updated if (M_STALL AND NOT PROBE) is asserted.
MBOX.STATUS is NOT updated if STALL is asserted by another box.
4.2.3.6 MREF.STATUS -
This two bit register is defined as follows:
MREF.STATUS<1> = 1 BIU has asserted IB_FILL_ERR
0 I Box has asserted IB_FILL_REQ
MREF.STATUS<0> = 0 if MMGT.STATUS = 111 else,
1.
MREF.STATUS<0> is used for a simple case on whether the reference was OK
or not.
MREF.STATUS<1> is used to indicate whether VIBA contains the address of
the prefetch fault or address +4.
4.2.4 Memory Management Microtrap Logic -
4.2.4.1 Partial PSL Logic -
The following processor status longword register bits are stored locally:
CVAX CPU CHIP DESIGN SPECIFICATION Page 205
MEMORY (M) BOX
PSL.IS - INTERRUPT STACK flag, PSL<26>, indicates use of the special
interrupt stack and kernel mode. Although PSL.IS is only used for
Microtest Bus testing, the bit is located in this block.
PSL.CURM - CURRENT MODE Bits, PSL<25:24>, indicate the privilege level of
the currently executing program. PSL.CURM bits are used for access
checking (see Privilege Check Logic). Testing by the Microtest Bus is
also done on these bits.
These bits are loaded whenever the E Box asserts LOAD_PSL. They may be
tested via Branch microinstructions with BCS = PSL<26:24>.
4.2.4.2 Cross Page Detection Logic -
The Cross Page logic examines the VA, the data length, and the L bit of
the microinstruction to determine if the reference will cross a page
boundary. The Cross Page logic examines VA and data length and is
activated only during virtual references that use VA as the address
source. The Cross Page conditions are summarized in the following table:
DATA LENGTH VA<8:0> IF CROSS PAGE ?
----------- ------- -- ------------
BYTE ------- -- NO
WORD 11111111x x.NE.0 YES
LONG 1111111xx xx.NE.00 YES
QUAD 111111xxx xxx.NE.000 YES
MMGT_REXE disables the Cross Page Detection Logic. MMGT_REXE may be set
by microcode, and is reset by any MREQ microinstruction, by IID_LD, or by
SPECIAL ZAP.TB.
After a cross page microtrap is taken, the microcode routine probes on
both sides of the page boundary. If everything is OK then MMGT_REXE is
set and the original memory reference is re-tried. Setting MMGT_REXE
inhibits the cross page microtrap during the retry. The trailing edge of
the retry resets MMGT_REXE so that ensuing references will microtrap if
they cross a page boundary.
4.2.4.3 Microtrap And Abort Determination Logic -
Before an access is deemed valid or not, one or more microtraps may occur.
There are four memory management microtraps initiated by the
Microsequencer as a result of trap requests by the M Box. The microtraps,
in the order of their priority and with their associated microtrap vectors
are:
highest: Cross Page 0
TB Miss 1
ACV/TNV 2
CVAX CPU CHIP DESIGN SPECIFICATION Page 206
MEMORY (M) BOX
lowest: M=0 3
The M Box will have one trap line (M Box_TRAP) that will indicate to the
u-sequencer that a M Box trap has occured. The M Box will then drive the
uTest bus with a trap code as shown below. However, if the BIU
simultaneously asserts BIU_TRAP, then the M Box will NOT drive the uTest
bus.
uTest<2:0> TRAP type
------------------------
000 MISS
001 M=0
010 ACV/TNV
011 XPAGE
A LENGTH ERROR will always cause a miss of the TB and during the MISS
flows the microcode cases on the MBOX.STATUS register to detect a LENGTH
ERROR.
The following describes when these microtraps are generated. If MMGT_TD
is set, or if MME is clear, or if an MREQ PHYSICAL, then only bus error
microtraps are enabled.
1. The cross page microtrap occurs as a result of a Cross Page condition
(described above), and MMGT_REXE = 0, and MREQ VA, and not MREQ PROBE and
REPROBE = 0.
2. The TB Miss microtrap occurs because of a miss in the TB and REPROBE =
0.
3. The ACV/TNV microtrap is taken if not MREQ PROBE and MMGT_TD = 0 and
(the memory request has insufficient privilege or REPROBE is set or the
page is not in memory). A page is not in memory when PTE.V is clear and
there is a hit. When a page is not in memory (TNV), reading the VAX_PTE
from memory to guarantee a fresh CVAX_PTE is not necessary, since a TNV
can only take place after a TB miss/fill routine and return and retry have
taken place. Therefore, if a TNV takes place the CVAX_PTE in the TB is
fresh.
4. The M=0 microtrap occurs if there is a hit and the PTE.M bit is 0 and
there is a write check, REPROBE = 0, and the microinstruction is not a
PROBE.
5. If the external Bus Error signal is asserted during a D stream read or
write, the transaction is terminated and one of seven bus error microtraps
is taken. The Bus Error microtrap cannot be disabled. If a Bus Error
occurs during an I Stream read, then the transaction is terminated and
IB_FILL_ERROR is asserted by the BIU, but a microtrap is not taken. The M
Box sets MREF.STATUS<1> = 1 if the BIU asserts IB_FILL_ERROR.
MREF.STATUS<1> is cleared by IB_FILL_REQ. If MMGT_TRAP and BIU_TRAP are
asserted together the M Box does not drive the uTest bus.
The I Box prefetcher needs to know when microtrap conditions occur so that
it can halt loading of its instruction buffer stack. The memory
CVAX CPU CHIP DESIGN SPECIFICATION Page 207
MEMORY (M) BOX
management microtrap logic notifies the I Box of an IB Fill Error if abort
conditions are detected. Note that no microtraps are taken and MTRAP is
not asserted during attempted IB Fills. If mapping VIBA results in a TB
miss, access violation, or PTE not valid, then the IB_FILL_ERROR is
asserted. If mapping VIBA results in a bus error assertion by the
external pin then prefetching is halted, a microtrap is NOT taken and
MREF.STATUS<1> is set.
No memory management microtraps are taken when VIBA is mapped. This is
true because when IB is dry and halted, prefetch requests a microtrap to
locations where VIBA is loaded into VA, then a MREQ VA with microtraps
enabled is used to bring the VAX_PTE into the TB and do validity,
protection, and length checks. Bus error microtraps can also occur at
this point. CVAX has no provision for memory management microtraps using
VIBA.
The M Box will have to STALL any MREQ or Broadcast on the cycle following
a write. In order to do this the BIU will assert MSTALL on a MREQ_WRITE.
The M Box will ignore this on the data-cycle of the write, but will STALL
the CVAX if a new MREQ or BRDCST_WBUS is encountered.
4.2.5 Memory Management Controller -
4.2.5.1 Trap Disable Logic -
The Memory Management Trap (and Prefetch) Disable (MMGT_TD) bit is set by
a TB Miss, ACV/TNV, or M = 0 memory management microtrap (NOT, however, by
a cross page or bus error microtrap), and by a SPECIAL MISC1=SET.MMGT.TD,
and cleared by a MISC=CLR.MMGT_TD field in an executed microinstruction.
When set, MMGT_TD disables prefetching, inhibits further TB Miss, ACV/TNV,
cross page, or M = 0 microtraps (NOT, however, bus error microtraps).
With memory management traps disabled, an M = 0 microtrap situation is
ignored completely, and the memory access completes normally; however a TB
Miss, ACV/TNV, and Cross Page situation will cause the M Box to perform a
NOP, while updating MMGT.STATUS.
Memory Management Trap Disable, MMGT_TD, enables and disables I Box
prefetching during Memory Management exceptions because it is necessary to
preserve the NLU pointer to allow writing to the correct PTE. Note that
probes may result in an ACV or TNV, and since no microtrap occurs, MMGT_TD
is not set; if prefetching is desired to be disabled in this case it must
be disabled using the MISC field= DISABLE.IB.PREFETCH (this does not set
MMGT_TD).
4.2.5.2 Reexecute Reference Logic -
MMGT_REXE is used after the Memory Management microcode has made sure that
CVAX CPU CHIP DESIGN SPECIFICATION Page 208
MEMORY (M) BOX
a reference that trapped will now execute properly. MMGT_REXE disables
the Cross Page detection logic. MMGT_REXE is CLEARed after one memory
reference by hardware. It is also CLEARed by the SPECIAL microinstruction
with MISC1 = ZAP.TB. IID_LD also CLEARs MMGT_REXE. This bit is SET by
MISC = SET.REEXECUTE.
4.2.5.3 REPROBE Flag - -
REPROBE is set via MISC1 field=SET.REPROBE. REPROBE is cleared by any
MREQ, by IID_LD, or by a ZAP.TB microinstruction. When set REPROBE
suppresses the execution of the next MREQ. No TB lookup occurs;
MMGT.STATUS and MBOX.STATUS are not updated. Instead, an ACV/TNV
condition is forced. If the MREQ was not a probe, a ACV/TNV microtrap
occurs; if it was a probe, a microtrap does not occur. In order to stop
the BIU from executing the next microinstruction, BIU_NOP is asserted.
4.2.5.4 Memory Management Enable Logic -
The TB function is enabled by the MME bit being set. This bit is written
by the microcode by writing to bit zero of MREQ.REG = MAPEN with the MXPS
microinstruction. It is read by reading bit zero of MREQ.REG = MAPEN with
the MXPS microinstruction. This function controls all TB writing and
access control in normal running and in maintenance operations.
When MME is clear, the entire TB mechanism is turned off. No traps will
occur for any reason related to Memory Management, including cross page
references.
When MME is clear, addresses are not translated and are considered
physical. Access privilege is not checked. When MME is set, address
translation is enabled.
4.2.6 Second IDAL Cycle Detection Logic -
This logic determines if the data transfer requested will require more
than one cycle per four bytes (or less) of data. The data length and VA
are examined. If no extra cycle is required, based upon the address and
data length, the REQ_2ND_REF is not asserted and control goes on to the
next microinstruction. If an extra cycle is required, REQ_2ND_REF is
asserted.
Probe, Read PTE, and Read Interrupt Vector memory request functions are
always aligned. When using VIBA there is no REQ_2ND_REF, since all
prefetching is guaranteed to be aligned by hardware (i.e. since VIBA<1:0>
= 00).
The memory request microinstructions use the data length (DL) from the I
Box or assume the length is long.
CVAX CPU CHIP DESIGN SPECIFICATION Page 209
MEMORY (M) BOX
Once the correct data length is determined, the low two bits of VA are
examined to decide whether the (first/last) register-worth of data will
take one or two IDAL cycles to transfer from/to memory. When the
microinstruction is determined to require two references, REQ_2ND_REF is
asserted. The MREQ microinstruction is re-executed in the sense that
another request is to be done. The M Box will use VAP on the second
reference.
4.2.6.1 REQ_2ND_REF Logic -
The following table indicates when REQ_2ND_REF is asserted.
DATA LENGTH VA<1:0> REQ_2ND_REF
----------- ------- -----------
BYTE -- NO...bytes are never unaligned
WORD 11 YES
LONG 01,10,11 YES
QUAD 01,10,11 YES
4.2.7 M Box Data Latches And Positioners -
4.2.7.1 M Box Data Latch And Byte Rotator -
This logic will latch write data from the W-bus destined for the BIU data
latches, and place it on the IDAL during the proper clock phase. It also
will latch read data on the IDAL destined for the W-bus. Between this
latch and the W-bus is a byte rotator used to rotate data during unaligned
writes to or reads from memory.
The table below shows how bytes are rotated as a function of Physical
Address (PA<1:0>).
BYTE
PA<1:0> W4 W3 W2 W1
00 I4 I3 I2 I1 no rotation
01 I3 I2 I1 I4 rotate 1 byte
10 I2 I1 I4 I3 rotate 2 bytes
11 I1 I4 I3 I2 rotate 3 bytes
W is W-bus byte #
CVAX CPU CHIP DESIGN SPECIFICATION Page 210
MEMORY (M) BOX
I is IDAL byte #
4.2.7.2 Internal Byte Mask -
This logic generates the internal byte mask used by the BIU and the M Box
Data Latch. The BIU uses the internal byte mask to generate BM<3:0>
during a write MEM REQ. The M Box Data Latch uses the internal byte mask
to select the bytes to be latched during a read MEM REQ.
The internal byte mask will be a function of Physical Address (PA<1:0>)
and the Data Length (DL<1:0>) as follows:
PA<1:0>
00 01 10 11
DL<1:0>
byte 00 0001 0010 0100 1000
word 01 0011 0110 1100 1000*
long 10 1111 1110* 1100* 1000*
quad 11 1111 1110* 1100* 1000*
* these are unaligned references and require a second access with
internal byte masks as shown below:
2nd reference
PA<1:0>
00 01 10 11
byte 00 ---- ---- ---- ----
word 01 ---- ---- ---- 0001
long 10 ---- 0001 0011 0111
quad 11 ---- 0001 0011 0111
The Byte Mask is generated by a PLA with PA<1:0>, DL<1:0> and 2nd ref
as inputs and BM<3:0> as the outputs as shown in the table below.
CVAX CPU CHIP DESIGN SPECIFICATION Page 211
MEMORY (M) BOX
2nd ref | DL<1:0> | PA<1:0> | BM<3:0>
------------------------------------------
0 00 0X 00PP
0 00 X0 0P0P
0 XX 11 P0PP
0 XX X1 PPP0
0 XX 1X PP00
0 0X 0X 0PPP
0 0X 00 P0PP
1 0X XX P00P
1 XX XX 0PPP
1 XX 0X P00P
1 XX X0 P0PP
note: a X in the input terms means don't care and a P in
BM<3:0> means that output remains precharged '1' unless
discharged by another minterm.
4.2.8 Control Signals Sent To BIU -
4.2.8.1 BIU_NOP -
This signal is sent to the BIU when the M Box encounters a MMGT error.
This tells the BIU that the instruction has run into a MMGT error, and
that the BIU should not continue with this instruction. This occurs when
the M Box gets a MMGT_TRAP, or when the M Box gets an IB_FILL_ERR.
4.2.9 IB_FILL_VALID -
This signal is sent to the BIU when the M Box can perform a prefetch
cycle. When the I Box asserts IB_FILL_REQ, and the M Box is not
performing any other MEMREQ operation, and Traps are disables, then the M
Box asserts this signal.
CVAX CPU CHIP DESIGN SPECIFICATION Page 212
MEMORY (M) BOX
4.2.10 MBOXBM -
This is the Byte-Mask that is in current use by the M Box, it is sent to
the BIU where it is used for Cache, and Memory control.
4.2.11 Control Signals Sent To E Box -
4.2.11.1 WSEL_UPDATE_H -
WSEL_UPDATE_H is used by the E Box during PH2 to enable loading of the
register file WRITE latch. During a D-stream READ that misses the CACHE
the update of the WRITE latch with the write destination from the current
microinstruction must be inhibited until the BIU indicates that READ data
has been received.
WSEL_UPDATE_H = ~EXT_MEMREQ_READ
EXT_MEMREQ_READ is SET by CACHE MISS on a D-stream read <---- during PHI_4
is RESET by IDAL_DATA_PRS <--- during PHI_1
4.2.11.2 REG_WRITE_H -
REG_WRITE_H is used to enable the write of the E Box registers from the
WBUS if true during PHI_4 and PHI_1. If the current cycle is STALLed for
any reason other than a CACHE MISS the registers should not be written.
REG_WRITE_H = (~STALL + EXT_MEMREQ_READ)<-- sampled at the
rising edge of PHI_3
4.2.11.3 SET_RESTART -
If the M Box successfully translates a write to memory it asserts
SET_RESTART which is sent to the E Box. The E Box sets a flag marking
this macroinstruction non-restartable.
4.2.11.4 NOT_MEM_REQ_R_H -
This signal is sent to the E Box in order to enable precharging of the
MW_Bus. This Bus must not be precharged for cases where the M Box is
CVAX CPU CHIP DESIGN SPECIFICATION Page 213
MEMORY (M) BOX
writing to the MW_Bus. Writes to the MW_Bus occur for MREQ READ.
4.2.11.5 MW_TO_W_H -
This signal is sent to the E Box to enable MW_Bus writes to the W_Bus.
This occurs for MREQ and MREF_READ, and for WBUS_BRDCST.
4.3 M Box Intersection And Intrasection Signals
4.3.1 M BOX Global Signal Timing -
The diagram below gives a list of global signals used or generated in the
M BOX. C Load refers the capacitance on that signal, which was extracted
from the CVAX Layout (the actual worst-case capacitance).
CVAX CPU CHIP DESIGN SPECIFICATION Page 214
MEMORY (M) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_C%PHI1_H |/~~~~~~~\\\____________________________| PHASE 1 CLOCK C Load = 123pF |
| | | | | | |
| G_C%PHI2_H |_________/~~~~~~~~\\\__________________| PHASE 2 CLOCK C Load = 107pF |
| | | | | | |
| G_C%PHI3_H |___________________/~~~~~~~~\\\________| PHASE 3 CLOCK C Load = 105pF |
| | | | | | |
| G_C%PHI4_H |\\___________________________/~~~~~~~~~| PHASE 4 CLOCK C Load = 142pF |
| | | | | | |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%B_BUS_H<31:0> |~~xxxxxx======================HHHHHHHHH| B_BUS C Load = 2.9pF |
| | | | | | * Simulated with 4pF |
| Note: Valid PHI1 + 18ns |
| Source - EBOX, IBOX, MBOX (mlr) Destination - EBOX |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%IB_FILL_ERR_L |HHHHHHHHHH~~~~~xxxx====================| Error Signal for I-Steam C Load = 3.7pF |
| | | | | | * Simulated with 4pF |
| Note: Valid PHI2 + 21ns to BPHI1 |
| Source - BIU, MBOX (mts) Destination - IBOX |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%MMGT_TRAP_L |HHHHHHHHHH~~xxxxxxx====================| Memory-Management Error |
| | | | | | C Load = 3.0pF |
| | | | | | * Simulated with 4pF |
| Note: Valid PHI2 + 21nS to BPHI1 |
| Source - MBOX (mts) Destination - USEQ,IBOX, MBOX (mps,mut) |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 215
MEMORY (M) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%MW_BUS_H<31:0> | | | | | The Bi-Directional Data Bus between IDAL |
| Write |xxxxxxx======================HHHHHHHHHH| and the W-Bus |
| | | | |^-- Precharged Conditionally |
| Read |=============================xxxx======| |
| | | | | | C Load = 1.6 pF |
| * Simulated with 1.5pF |
| Note: Valid PHI4 + 10ns on READ |
| Note: Valid PHI1 + 21ns on WRITE |
| Source - EBOX,MBOX (mrot) Destination - EBOX,MBOX (mrot) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%STALL_L |HHHHHHHHHH~~xxxxxx=====================| CHIP-WIDE STALL SIGNAL C Load = 12.23 pF |
| | | | | | |
| Note: Valid PHI2 + 21ns to BPHI1 |
| Source - EBOX,BIU,IBOX,uSEQ,MBOX (mts) Destination - GLOBAL,MBOX (mdpc,mic,mps,mrs,mst,mut) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%UTEST_L<2:0> |~xxxx===============HHHHHHHHHH~~~~~~~~~| MICRO-TEST BUS C Load = 4.4 pF |
| | | | | | Latched on falling edge of PHI1. Must |
| | | | | | be valid 15 nS after rising edge of PHI1 |
| Note: Valid PHI1 + 14ns |
| Source - GLOBAL,MBOX (mut) Destination - USEQ |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PH%W_SPUR_H<7:0> | | | | | W-BUS SPUR C Load = 7.1 pF |
| WRITE |~xxxxxxxx=====================HHHHHHHHH| * Valid PHI1 + 21ns |
| | | | | | |
| READ |==========HHHHHHHHHH~xxxxxxxxxxxxx=====| * Valid PHI4 + 10nS |
| | | | | | |
| |
| Source - GLOBAL, MBOX (mut) Destination - GLOBAL, MBOX (mut) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_PL%CASH_BUS_H<5:0> |__xxx=========================LLLLLLLLL| Address Bus for CACHE C Load = 2.1 pF |
| | | | | | |
| Note: Valid PHI1 + 14ns |
| Source - MBOX (mar) Destination - CACHE |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 216
MEMORY (M) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%AT_EQ_MOD_H |===================xxxxxxxxxxxx========| Access-Type = Modify (WRITE) C Load = 4pF |
| | | | | | |
| Note: Assumed valid PHI4 + 3ns to BPHI3 |
| Source - IBOX Destination - MBOX (mpd) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%BIU_NOP_H |xxx~~~~~~xxxxxxxxx=====================| BIU should NOP this microinstruction |
| | | | | | * Simulated with 1.5pF |
| Note: Valid PHI2 + 21ns to BPHI1 |
| Source - MBOX (mts) Destination - BIU C Load = 2.2 pF |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%BIU_TRAP_L |==========xxxxxxx======================| BIU Trap cond. detected C Load = 3.8pF |
| | | | | | note: Assumed Valid at PHI2 + 18ns |
| |
| Source - BIU Destination - IBOX,USEQ,MBOX (mst,mut) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%BRDCST_BASIC_H |xxx==========================xxxxxxxxxx| BASIC Broadcast Cycle C Load = 2.9 pF |
| | | | | | note: Assumed Valid at PHI1 + 11ns |
| BIU has it valid at PHI4 + 23ns |
| Source - BIU Destination - MBOX (mmc,mrc,mst,mts) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%BRDCST_OK_H |====================xxxxxxxxxx=========| FPU BASIC O.K. Flag C Load = 4.2 pF |
| | | | | | note: Assumed Valid at PHI3 + 21ns to BPHI3|
| |
| Source - IBOX Destination - BIU,MBOX (mmd) |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 217
MEMORY (M) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%DL_H<1:0> |=====================xxxxxxxxx=========| Data-Length Reg. Content C Load = 5.4pF |
| | | | | | note: Assumed Valid at PHI4 + 1ns to BPHI3 |
| |
| Source - IBOX Destination - EBOX,USEQ,MBOX (mdpc) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%IB_FILL_REQ_H |=========xxxxxxxxxxxxxxxxxxxx==========| IB Fill Request C Load = 3.1 pF |
| | | | | | note: Assumed Valid at PHI3 + 21ns to BPHI2|
| |
| Source - IBOX Destination - MBOX (mst) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%IB_FILL_VALID_H |=============================xxxxxxx===| Validate IB Fill Request for BIU |
| | | | | | * Simulated with 3pF |
| | | | | | note: Valid PHI4 + 13ns to BPHI4 |
| C Load = 2.1 pF |
| Source - MBOX (mst) Destination - BIU |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%IDAL_H<31:0> | | | | | Internal DAL C Load = 10.5 pF |
| WRITE |=========xxxxxxxxxx====================| note: Valid PHI2 + 19ns 12.3 pF |
| | | | | | ^ |
| READ |=============================xxxxxxxx==| note: Valid PHI4 + 08ns IDAL<29> ^ |
| | | | | | * Simulated with 10pF |
| |
| Source - CACHE,BIU,MBOX (mdrv) Destination - CACHE,BIU,IBOX,MBOX (mdrv) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%IID_LD_H |________________________/==============| IID signal to Chip C Load = 4.0 pF |
| | | | | | note: Assumed Valid PHI3 + 17ns to BPHI1 |
| |
| Source - IBOX Destination - EBOX,MBOX (mps) |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 218
MEMORY (M) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%LOAD_VIBA_AND_PC__H |==========xxxxxxxxxxxxxxx==============| LOADING VIBA and PC C Load = 6.0 pF |
| | | | | | note: Valid PHI3 + 6ns to BPHI2 |
| |
| Source - EBOX Destination - IBOX,BIU,MBOX (mrs) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%LOAD_PSL_H |____________/======\___________________| LOADING PSL ENABLE C Load = 5.6 pF |
| | | | | | |
| |
| Source - EBOX Destination - IBOX,INT LOGIC,BIU,MBOX(mut) * Valid PHI2 + 7ns |
| * thru EPHI2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%MBOX_BM_L<3:0> |=xxxxxxxxxxxxx=========================| MBOX Generated Byte-Mask |
| | | | | | * Simulated with 1.9pF |
| Note: Valid PHI2 + 15ns to BPHI1 |
| Source - MBOX (mmc) Destination - BIU C Load = 1.0 pF |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%MIB_H<40:7> |===================xxxxxxxxxx==========| Micro-Instruction Bus |
| G_S%MIB_L<40:7> | | | | | C Load = 8.0 pF |
| | | | | | Note: Assumed Valid PHI3 + 21ns to BPHI3 |
| |
| Source - Control Store Destination - GLOBAL,MBOX (mmd,mpd) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%M_STALL_H |xxxxxxxxx====================xxxxxxxxxx| MBOX can NOT use the IDALs |
| | | | | | C Load = 5.2 pF |
| | | | | | Note: Assumed Valid PHI1 + 21ns to BPHI3 |
| Currently BIU has it valid at PHI1 + 24ns |
| >>>>> MBOX needs it sooner <<<<< |
| Source - BIU Destination - MBOX (mdpc,mic,mrs,mst,mts,mut) |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 219
MEMORY (M) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%MOD_INTENT_H |xxxxxxxxxxx========xxxxxxxxxxxxxxxxxxxx| Modify Intent |
| | | | | | * Simulated with 2.0pF |
| Note: Valid PHI2 + 5ns to BPHI3 |
| Source - MBOX (mpd) Destination - BIU C Load = 1.0 pF |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%MW_DRIVE_H |===================xxxxx/==============| When asserted enables the EBOX to drive |
| | | | | | the MW_BUS |
| Note: Valid PHI3 + 12ns to BPHI3 |
| * Simulated with 1.7pF |
| Source - MBOX (mst) Destination - EBOX C Load = 4.1 pF |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%MW_TO_W_H |=========xxxxxxxxxxx/==================| When asserted selects the MW_BUS as |
| | | | | | the data source for driving the W_BUS |
| Note: Valid PHI3 + 1ns to BPHI2 |
| Source - MBOX (mst) Destination - EBOX * Simulated with 2.3pF |
| C Load = 1.9 pF |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%ONE_SLOT_FREE_H |========xxxxxxxxxxxx===================| Only One slot left in the Prefetch queue |
| | | | | | C Load = 2.7 pF |
| Note: Assumed Valid PHI2 + 21ns to BPHI2 |
| Source - IBOX Destination - MBOX (mst) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%READ_DATA_PRS_H |___/===============xxxxxxxxxxxxxxxxxxxx| IDAL has Read Data on it C Load = 2.1 pF |
| | | | | | Note: Assumed Valid PHI1 + 08ns to BPHI3 |
| |
| Source - BIU Destination - MBOX (mdpc,mic,mst) |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 220
MEMORY (M) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%READ_HIT_H |_/=================xxxxxxxxxxxxxxxxxx\_| Cache Hit Gated by BIU C Load = 3.3 pF |
| | | | | | Note: Assumed Valid PHI4 + 24ns to BPHI3 |
| |
| Source - BIU Destination - MBOX (mdpc,mic,mmd,mrc,mst) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%REG_WRITE_H |===================xxxxx===============| Write register enabled in EBOX and MBOX |
| | | | | | Note: Valid PHI3 + 11ns to BPHI3 |
| * Simulated with 6.1pF |
| Source - MBOX (mst) Destination - EBOX, MBOX (mrs) C Load = 4.1 pF |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%RESET_S_H |~~\____________________________________| RESET Stretched C Load = 19.5 pF |
| | | | | | Assertion is asynchronous |
| |
| Source - Clock Logic Destination - Global,MBOX (mdpc,mhit,mst,mut) |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%SET_RESTART_H |===================xxxxxx==============| NO MMGT_ERROR on Write |
| | | | | | Note: Valid PHI3 + 12ns to BPHI3 |
| * Simulated with 4.2pF |
| Source - MBOX (mst) Destination - EBOX (strobed with PHI4) C Load = 0.8 pF |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%WSEL_UPDATE_H |xxxxxxxxx==============================| Update WSEL Latches in EBOX |
| | | | | | Note: Valid PHI1 + 21ns to BPHI1 |
| * Simulated with 4.0pF |
| Source - MBOX (mst) Destination - EBOX C Load = 2.7 pF |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 221
MEMORY (M) BOX
+----------+---------+---------+----------+
GLOBAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| G_S%W_BUS_H<31:0> |=============================xxxxxxxxx=| W-BUS C Load = 4.3 pF |
| | | | | | * Simulated with 4.0 pF |
| * Valid before 1 thru |
| Source - EBOX Destination - EBOX,MBOX (mar,mlr) * start of PHI4 |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 222
MEMORY (M) BOX
4.3.2 M BOX Internal Signal Timing -
The diagram below lists all the internal M BOX signals that cross
schematic boundaries. C Load refers to the capacitance on that signal
line. This capacitance value was extracted from the CVAX layout. This is
that 'actual' worst-case capacitance on this signal line.
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------^
| | | | | | |
| M_PH%B_BIT_H<31:0> |~~xxx========================HHHHHHHHHH| B Bit Bus Precharged high |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL TOO_IDAL_NEW_SS_1 Last Updated: 9/30/86 |
| C Load = 0.57 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mlr,mar PHI1 + 13ns mlr 1 gate delay No |
| before LE PHI2 |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PH%C_BUS_H<31:0> |~~xxx========================HHHHHHHHHH| C Bus Precharged high |
| | | | | | |
| Spice Ref (Block/Text): M_ADDRESS_REG_SEL TOO_HIT_5_SS Last Updated: 9/30/86 |
| M_REG_SEL TOO_IDAL_NEW_SS_1 |
| C Load = 0.46 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mlr,mar PHI1 + 12ns mar early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PH%C_BUS_L<31:0> |~~xxx========================HHHHHHHHHH| C Bus Precharged high |
| | | | | | |
| Spice Ref (Block/Text): M_ADDRESS_REG_SEL TOO_HIT_5_SS Last Updated: 9/30/86 |
| M_REG_SEL TOO_IDAL_NEW_SS_1 |
| C Load = 0.62 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mlr,mar PHI1 + 11ns mar early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PH%HIT_H<28:1> |~~xxxxxx=====================HHHHHHHHHH| HIT lines of TAG Array Precharged high |
| | | | | | |
| Spice Ref (Block/Text): M_ADDRESS_REG_SEL TOO_HIT_5_SS Last Updated: 9/30/86 |
| M_REG_SEL TOO_IDAL_NEW_SS_1 |
| C Load = 1.81 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mtag PHI1 + 21ns mhit late in PHI1 Yes |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 223
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PH%LEN_RESULT_L |xxxxxxxxxxxxxxxxxxxx=========HHHHHHHHHH| Length Violation Precharged high |
| | | | | | |
| ^-- Input C-Bus and B-Bus in PHI2 |
| ^-- Valid result 5 phases later |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 2.31 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mlr PHI3 + 0ns mdpc early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PH%PHI2_COND_L |HHHHHHHHH~~========xxxHHHHHHHHHHHHHHHHH| Is a Translation to be Performed |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL TOO_IDAL_NEW_SS_1 Last Updated: 9/30/86 |
| C Load = 9.35 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI2 + 03ns mhit early in PHI2 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PH%PHYS_BUS_H<29:9> | | | | | Physical Address (TRANSLATED) Bus |
| Read -> |~~~~~~~~~~~~~~~~=============HHHHHHHHHH| Precharged High |
| | | | | | |
| Write -> |=========~~~~~~~~~~~~~~~~~~~~~~~~~~====| |
| | | | | ^ | |
| ^-- PTE entry written here, no Precharge Cycle |
| Spice Ref (Block/Text): M_ADDRESS_REG_SEL TOO_HIT_5_SS Last Updated: 9/30/86 |
| M_REG_SEL TOO_IDAL_NEW_SS_1 |
| C Load = 2.73 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mpte,mdrv,mpp PHI2 + 20ns mdrv late in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PH%PH_C_BUS_L<2:0> |xxxxx========================HHHHHHHHHH| External C-Bus Precharged High, Valid Low |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.47 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mar PHI1 + 15ns mdpc,mxp middle of PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 224
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PH%PTE_M_H | | | | | PTE.M Signal for HIT entry of PTE |
| Read -> |~~~~~~~~~~~~~~~~=============HHHHHHHHHH| Precharged High |
| | | | | | |
| Write -> |=========~~~~~~~~~~~~~~~~~~~~~~~~~~====| |
| | | | | ^ | |
| ^-- PTE.M entry written here, no Precharge Cycle |
| Spice Ref (Block/Text): M_ADDRESS_REG_SEL TOO_HIT_5_SS Last Updated: 9/30/86 |
| M_REG_SEL TOO_IDAL_NEW_SS_1 |
| C Load = 2.48 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mpte,mdrv,mpp PHI2 + 20ns mts late in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PH%PTE_V_H | | | | | PTE.V Signal for HIT entry of PTE |
| Read -> |~~~~~~~~~~~~~~~~=============HHHHHHHHHH| Precharged High |
| | | | | | |
| Write -> |=========~~~~~~~~~~~~~~~~~~~~~~~~~~====| |
| | | | | ^ | |
| ^-- PTE.M entry written here, no Precharge Cycle |
| Spice Ref (Block/Text): M_ADDRESS_REG_SEL TOO_HIT_5_SS Last Updated: 9/30/86 |
| M_REG_SEL TOO_IDAL_NEW_SS_1 |
| C Load = 2.49 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mpte,mdrv,mpp PHI2 + 20ns mts late in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PH%P_CODE_H<8:1> | | | | | Protection Code for ACV Check |
| |xxxxx=====_____________________________| NOT Precharged High |
| | | | | | |
| |
| Spice Ref (Block/Text): M_PROT_GEN_SIM SIM_40 Last Updated: 9/30/86 |
| C Load = 1.76 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mpl PHI1 + 07ns mpte late in PHI1 Yes |
| ^-- At Vtn |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PH%RAW_ACV_L | | | | | Unconditioned Access Violation (ACV) |
| |HHHHHHHHHHxxxxxxx======================| Precharged High |
| | | | | | |
| |
| Spice Ref (Block/Text): M_PROT_GEN_SIM SIM_F Last Updated: 9/30/86 |
| C Load = 1.47 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
CVAX CPU CHIP DESIGN SPECIFICATION Page 225
MEMORY (M) BOX
| mpte,mpp PHI2 + 15ns mts late in PHI2 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 226
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PL%HIT_SEL_H | | | | | Conditioned HIT Line (a Translation will |
| |~~~~~~~~~xxxx=================LLLLLLLLL| occur) Precharged Low |
| | | | | | |
| |
| Spice Ref (Block/Text): M_ADDRESS_REG_SEL TOO_HIT_5_SS Last Updated: 9/30/86 |
| M_REG_SEL TOO_IDAL_NEW_SS_1 |
| C Load = 2.62 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mhit PHI2 + 12ns mpte early in PHI2 Yes |
| ^-- At Vtn |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PL%LOAD_PTE_H | | | | | Load a PTE Entry |
| |=========LLLLLLLLLL~~~~~~~~~~xxxxx=====| Precharged Low |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.89 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mhit PHI4 + 06ns mpte early in PHI4 Yes |
| ^-- At Vtn |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PL%MISS_H | | | | | There is a TB Miss (not conditioned) |
| |_________xxxxxxx=============xxxxxxx___| Precharged Low (this signal burns power) |
| | | | | | |
| |
| Spice Ref (Block/Text): M_REG_SEL TOO_IDAL_NEW_SS_1 Last Updated: 9/30/86 |
| C Load = 2.46 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mhit PHI2 + 21ns mdpc late in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_PL%PXPAGE_L | | | | | A POSSIBLE Cross-Page Condition |
| |xxxxxxx======================LLLLLLLLLL| Precharged Low |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = ?.?? pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mlr PHI1 + 18ns mdpc, mxp early in PHI2 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 227
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%2ND_CYCLE_H | | | | | We are in the 2nd_cycle of an unaligned |
| |xxxxxxx============xxxxx===============| |
| | | | | | * Simulated with 4.7pF |
| |
| Spice Ref (Block/Text): M_STATE_SIM MSTA3_SS_1 Last Updated: 9/30/86 |
| C Load = 3.96 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mlr PHI1 + 16ns mdpc,mmc,mrs, early in PHI2 No |
| PHI3 + 10ns mrc,mst |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%2ND_CYCLE_L | | | | | inverted 2nd_cycle_h |
| |xxxxxxxxx===========xxxxx==============| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.49 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI1 + 21ns mts early in PHI2 No |
| PHI3 + 15ns |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%2ND_REF_H | | | | | A 2nd reference is required for this MREQ |
| |xxxxxxxxx===========xxxx===============| |
| | | | | | * Simulated with 2.4pF |
| |
| Spice Ref (Block/Text): M_STATE_SIM MSTC3_SS_1 Last Updated: 9/30/86 |
| C Load = 1.69 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mst PHI1 + 19ns mmd, mrs early in PHI2 No |
| PHI3 + 14ns |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ACV_H | | | | | There is an Access Violation |
| |=========xxxxx=========================| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.00 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mts PHI2 + 15ns mut early in PHI3 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 228
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ACV_PREC_L | | | | | RAW_ACV Precharge signal |
| |xxxx_____xxxx~~~~~~~~~~~~~~~~~~~~~~~~~~| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.33 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI1 + 07ns mpp early in PHI1 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ADD_PREC_H | | | | | +4 Adder precharge signal |
| |xxxx~~~~~xxxx__________________________| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.88 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI1 + 07ns mpp early in PHI1 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ADD_SELECT_H<3:1> | | | | | Select which address is written to |
| |_________xxxx======xxxxx_______________| the IDAL |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 4.14, 2.12, 6.83 pF for <3>, <2>, and <1> |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mic PHI2 + 05ns mdrv early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ASSERT_MMGT_TRAP_H | | | | | There is a MMGT_TRAP condition |
| |_________xxxxxxxx======================| |
| | | | | | |
| |
| Spice Ref (Block/Text): M_TRAP_STALL SS_M_TRAP_STALL_SIMULATIONS Last Updated: 9/30/86 |
| C Load = 0.72 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mts PHI1 + 22ns mst early in PHI2 Yes |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 229
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%BM_L<3:0> | | | | | M Box Byte-Mask Conrol Signals |
| |=========xxxx________________xxxxx=====| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 5.97 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mic PHI4 + ??ns mdrv early in PHI4 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%BM_UNCLK_H<3:0> | | | | | M Box Byte-Mask Unclocked Control Signals |
| |=========xxxx________________xxxxx=====| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.24 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmc PHI2 + ??ns mic early in PHI4 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%BUF_BIT_30_H | | | | | Buffered C_BUS, Bit 30 |
| |xxxxxxx======================xxxx~~~~~~| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 2.03 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrl PHI1 + 21ns mdpc,mrs,mut early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%BUF_BIT_31_H | | | | | Buffered C_BUS, Bit 31 |
| |xxxxxxx======================xxxx~~~~~~| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 2.14 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrl PHI1 + 21ns mrs,mut early in PHI2 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 230
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%CHECK_EQ_NONE_H | | | | | No Access Check is to be performed |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.04 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mts early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%CHECK_XPAGE_H | | | | | No Access Check is to be performed |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.04 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mts early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%CROSS_PAGE_H | | | | | A Cross-Page error has occured |
| |xxxxxxxxxxxxxxx=====================___| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.77 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mts PHI2 + 21ns mps,mut early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%DATA_SELECT_H | | | | | Drive Data out on IDAL |
| |_________xx========xxxx________________| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 4.68 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mic PHI2 + 05ns mdrv early in PHI2 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 231
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%DL_H<1:0> | | | | | Data Length for M Box use, which includes |
| |xxxxxxxxxxxxxxx=====================___| the L (forced long) Bit in the MIB field |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.86 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI1 + 10ns mmc,mun,mxp early in PHI1, No |
| before the C_BUS's |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%DRIVE_B_BUS_L | | | | | Drive the data which is on the B_BIT Bus |
| |x________x~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| to the B_BUS |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 6.00 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mbbc PHI2 + 05ns mlr early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%DR_PRECHARGE_L | | | | | Precharge the Tri-State node in the IDAL |
| |xxxx~~~~~~~~~~~~~~~~~~~~~~~~~xx________| driver |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 3.15 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mic PHI4 + 05ns mdrv early in PHI4 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%DST_B_L | | | | | DST.B MIB Decode |
| |===================~~~~~~~~~~~xxxxxx===| |
| | | | | | * Simulated with 2.0pF |
| |
| Spice Ref (Block/Text): M_MIB_DEC SIM1 Last Updated: 9/30/86 |
| C Load = 1.03 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI4 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 232
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%DST_VIBA_1_H | | | | | WSEL_VIBA (Writing VIBA from the W-Bus) |
| |===================xxxxxx==============| |
| | | | | | * Simulated with 2.0pF |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.44 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI3 + 14ns mut early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%DST_VIBA_2_H | | | | | Load VIBA and PC Occured |
| |===================xxxxxx==============| |
| | | | | | * Simulated with 2.0pF |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 2.80 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI3 + 14ns mut early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%EXT_MREF_RD_H | | | | | Missed the cache, and had to go external |
| |xxxxxxx================================| for the data |
| | | | | | * Simulated with 2.6pF |
| |
| Spice Ref (Block/Text): M_STATE_SIM MSTB3 Last Updated: 9/30/86 |
| C Load = 2.80 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mst PHI1 + 18ns mdpc,mut late in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%FLUSH_TB_H | | | | | Flush (set TB.V = 0) the entire TAG Array |
| |xxxxx==============~~~~~~~~~~~xxxxxxxxx| |
| | | | | | * Simulated with 3.0pF |
| |
| Spice Ref (Block/Text): M_MIB_DEC SIM6 Last Updated: 9/30/86 |
| C Load = 1.56 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mdpc,mps early in PHI2 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 233
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%FPA_READ_H | | | | | This is a MEM_REQ FPA Inst. |
| |xxxxxxxxxxxxxxx=====================___| |
| | | | | | |
| |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.97 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI2 + 21ns mic early in PHI4 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |<
| M_S%INVAL_ON_HIT_H | | | | | set TB.V=0 for the TB entry with is HIT |< This might
| |xxxxx==============~~~~~~~~~~xxxxxxxxxx| |< have to be
| | | | | | * Simulated with 3.0pF |< sped up,
| |< M_STATE
| Spice Ref (Block/Text): M_MIB_DEC SIM3 Last Updated: 9/30/86 |< needs it
| C Load = 1.17 pF |< early in
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |< PHI1
| mmd PHI1 + 15ns mdpc,mst early in PHI1 No |<
| |<
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LATCH_REG_SEL_H | | | | | Latch the register selects before they |
| |~~~~~~~~~xxxxxx______________xxxx~~~~~~| go away |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.12 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI4 + 05ns mrs early in PHI4 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LATCH_REG_SEL_L | | | | | Latch the register selects before they |
| |_________xxxxxx~~~~~~~~~~~~~~xxxx______| go away |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.00 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI4 + 05ns mrs early in PHI4 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 234
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LATCH_ROT_BM_H | | | | | Latch the Rotator and the Byte-Mask |
| |_________xxxxx=====xx__________________| Control Signals |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.85 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrc PHI2 + 10ns mmc early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LD_ADDER_H | | | | | Load inputs into the +4-Adder |
| |xxx~~~~~~~~~~~~~~~~xxxx________________| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 3.34 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI1 + 10ns mar early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LD_ADDER_L | | | | | Load inputs into the +4-Adder |
| |xxx________________xxxx~~~~~~~~~~~~~~~~| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 5.44 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI1 + 10ns mar early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LD_VAP_ADD_H | | | | | Load VAP Register with the output of the |
| |xxx__________________________xxxx======| +4-Adder |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 2.40 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI4 + 07ns mar early in PHI4 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 235
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LD_VIBA_ADD_H | | | | | Load VIBA Register with the output of the |
| |xxx__________________________xxxx======| +4-Adder |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 2.31 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI4 + 07ns mar early in PHI4 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LD_VIBA_ADD_LAT_H | | | | | Latched signal to load VAP Register with |
| |===================xxxx================| the output of the +4-Adder |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.64 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI3 + 14ns mut early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LEN_LOAD_H | | | | | Load the inputs into the Length-Compare |
| |_________xx========xxxxx_______________| Logic |
| | | ^ | | | |
| Spice Ref (Block/Text): ^-- Input C-Bus and B-Bus (conditionally) Last Updated: 9/30/86 |
| C Load = 2.27 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI2 + 05ns mlr early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LEN_PREC_L | | | | | Precharge the LEN_RESULT line |
| |xx~~~~~~~~~~~~~~~~~~~~~~~~~~~xx========| Logic |
| | | ^ | | | |
| Spice Ref (Block/Text): ^-- Input C-Bus and B-Bus (conditionally) Last Updated: 9/30/86 |
| C Load = ?.?? pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI4 + 05ns mlr early in PHI4 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 236
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LEN_VIO_STROBE_L | | | | | Strobe out the Length-Violation in PHI3 |
| |~~~~~~~~~~~~~~~~~~~~xx=======xxxxx~~~~~| |
| | | ^ | | | |
| Spice Ref (Block/Text): ^-- Input C-Bus and B-Bus (conditionally) Last Updated: 9/30/86 |
| C Load = 0.39 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI3 + 05ns mut early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%LMW_BUS_H<31:0> | | | | | The Bi-Directional Data Bus between IDAL |
| Write |xxxxxxx======================~~~~~~~~~~| and the MW-Bus (the Rotator Latch) |
| | | | |^-- Precharged Conditionally |
| Read |=============================xxxx======| |
| | | | | | C Load = 3.12 pF |
| * Simulated with 3.2pF |
| Note: Valid PHI4 + 10ns on READ |
| Note: Valid PHI1 + 21ns on WRITE |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrot,mdrv PHI1 + 21ns mrot,mdrv early in PHI2 No |
| (E Box) PHI4 + 10ns early in PHI4 |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MBOX_STALL_H | | | | | The STALL condition was caused by the MBox |
| |xxx______xxxxxxxx======================| |
| | | | | | |
| Spice Ref (Block/Text): M_STATE_SIM MMS Last Updated: 9/30/86 |
| C Load = 0.97 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mst PHI3 + 04ns mps,mut early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MDPC_PHI4_L | | | | | Data-Path control signal (~PHI4) |
| |xx~~~~~~~~~~~~~~~~~~~~~~~~~~~xx________| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 11.79 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI4 + 03ns mhit,mar,mlr early in PHI4 Yes |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 237
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MEM_REQ_FPA_H | | | | | FPA Data Transfer decoded of the MIB's |
| |xxxxx==============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | * Simulated with 3.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM3 Last Updated: 9/30/86 |
| C Load = 2.41 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mdpc,mmc,mrc middle of PHI1 No |
| mts |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MEM_REQ_READ_H | | | | | A MEM_REQ Read operation on the MIB's |
| |xxxxx==============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | * Simulated with 3.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM6 Last Updated: 9/30/86 |
| C Load = 0.98 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mst middle of PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MEM_REQ_WRITE_H | | | | | A MEM_REQ Write operation on the MIB's |
| |xxxxx==============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | * Simulated with 3.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM6 Last Updated: 9/30/86 |
| C Load = 1.28 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mrs,mst middle of PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MISC_CLR_MMGT_TD_H | | | | | A Clear MMGT Trap Disable operation |
| |xxxxx==============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | * Simulated with 1.5pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM5 Last Updated: 9/30/86 |
| C Load = 0.52 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mps middle of PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 238
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MISC_SET_MMGT_TD_H | | | | | A SET MMGT Trap Disable operation |
| |xxxxx==============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | * Simulated with 1.5pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM5 Last Updated: 9/30/86 |
| C Load = 0.66 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mps middle of PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MISC_SET_REEXECUTE_H | | | | | A SET Re-Execute operation |
| |xxxxx==============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | * Simulated with 1.5pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM5 Last Updated: 9/30/86 |
| C Load = 0.55 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mps middle of PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MISC_SET_REPROBE_H | | | | | A SET Reprobe operation |
| |xxxxx==============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | * Simulated with 1.5pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM5 Last Updated: 9/30/86 |
| C Load = 0.53 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mps middle of PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MISS_COND_L | | | | | Control signal to write a TB Entry on a |
| |~~~~~~~~~xxxxx=====xxxx~~~~~~~~~~~~~~~~| TB Miss |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 4.57 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI2 + 07ns mhit early in PHI2 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 239
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MISS_SEL_H<28:1> | | | | | Control signal to write a TB Entry |
| |~~~~~~~~~xxxxx=====xxxx~~~~~~~~~~~~~~~~| pointed to by the NLU |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.73 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mhit PHI2 + 10ns mtag early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MME_H | | | | | Memory Management Enable (MME) signal, |
| |=========xxxxxxxx======================| basically says Translations are enabled |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.88 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mut PHI2 + 21ns mdpc,mic,mts early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MME_READ_H | | | | | Control signal to Read the MME register to |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| the W-Spur (W-spur <-- MME) |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.98 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mut early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MME_WRITE_H | | | | | Control signal to Write the MME register |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| from the W-Spur (W-spur --> MME) |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.68 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mut early in PHI3 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 240
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MMGT_ERROR_H | | | | | There was a MMGT Error |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): M_TRAP_STALL SS_M_TRAP_STALL_SIMULATIONS Last Updated: 9/30/86 |
| C Load = 1.33 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mts PHI3 + 03ns mrs,mst early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MMGT_TD_H | | | | | MMGT Trap Disable Decoded from the MIB's |
| |xxxx===================================| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.19 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mps PHI1 + 10ns mmd,mst,mts, early in PHI3 No |
| mut |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MODE_H<1:0> | | | | | Output of the MODE Register |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.55 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mut PHI2 + 21ns mpl early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MREF_H | | | | | This is a TRUE MEMORY TRANSFER Operation |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| on the MIB's |
| | | | | | * Simulated with 3.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM6 Last Updated: 9/30/86 |
| C Load = 1.98 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mps,mst,mts early in PHI2 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 241
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MREF_PHYS_H | | | | | This is a TRUE PHYSICAL MEMORY TRANSFER |
| |===================~~~~~~~~~~xxxxx=====| Operation on the MIB's |
| | | | | | * Simulated with 3.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM7 Last Updated: 9/30/86 |
| C Load = 1.43 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mic early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MREF_PTE_H | | | | | This is a TRUE PTE READ Operation |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| on the MIB's |
| | | | | | * Simulated with 3.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM6 Last Updated: 9/30/86 |
| C Load = 1.72 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mdpc,mic early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MREQ_PROBE_H | | | | | This is a MEM_REQ PROBE Operation |
| |===================~~~~~~~~~~xxxxx=====| |
| | | | | | * Simulated with 3.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM7 Last Updated: 9/30/86 |
| C Load = 2.80 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mic early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%MREQ_VIRT_H | | | | | This is a Virtual MEM_REQ Operation |
| |===================~~~~~~~~~~xxxxx=====| on the MIB's |
| | | | | | * Simulated with 3.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM7 Last Updated: 9/30/86 |
| C Load = 2.43 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mic early in PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 242
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%M_EQ_ZERO_H | | | | | This is the PTE.M = 0 signal |
| |_________xxxxxxxxxxxxx=======__________| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.82 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mts PHI3 + 06ns mut early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%PAGE_OVFL_H | | | | | There is a Cross-Page Condition |
| |___xxxxxxxxx=================__________| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.83 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mxp PHI2 + 08ns mts middle of PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%PHYS_PREC_L | | | | | Precharge control for M_PH%PHYS_BUS_H, |
| |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~xx========| conditional on ~LOAD_PTE |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 2.59 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI4 + 05ns mpp early in PHI4 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%PL_C_BUS_H<1:0> | | | | | A buffered C_BUS, acts like it was |
| |xxx==========================xx________| precharged Low, valid High |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 3.90 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI1 + 16ns mmc,mrc,mua middle of PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 243
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%PREFETCH_CYCLE_H | | | | | This is a PREFETCH CYCLE, a prefetch WILL |
| |___xxxxxxxxx=================__________| occur |
| | | | | | |
| Spice Ref (Block/Text): M_STATE_SIM MSTE3 Last Updated: 9/30/86 |
| C Load = 3.62 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mst PHI4 + 21ns mdpc,mic,mmc early in PHI1 No |
| mrs,mts,mut |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%PROT_COMP_PREC_L | | | | | Precharge control for M_PH%PROT_COMP_H |
| |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~xx________| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 2.71 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mic PHI4 + 05ns mpte early in PHI4 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%PROT_DEC_H<8:1> | | | | | The re-decoded Protection Field to write |
| |========xxxxxxxxxxxxxxxxxxxxxxxxx======| into the PROTECTION cell |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.28 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mid PHI4 + 12ns mpte early in PHI4 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%PSL_L<26:24> | | | | | The PSL Bits (buffered W-Bus<26:24>) |
| |xxx==========================xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.47 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mar PHI1 + 05ns mdpc early in PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 244
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%PSL_OUT_H<25:24> | | | | | The Latched PSL Bits |
| |==========xxxxxxxxx====================| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.37 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mut PHI2 + 21ns mpl early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_B_SEL_P0LR_L | | | | | This is an MXPR Operation with B Select |
| |===================~~~~~~~~~~xxxxx=====| P0LR |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM1 Last Updated: 9/30/86 |
| C Load = 0.99 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_B_SEL_P1LR_L | | | | | This is an MXPR Operation with B Select |
| |===================~~~~~~~~~~xxxxx=====| P1LR |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM1 Last Updated: 9/30/86 |
| C Load = 1.10 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_B_SEL_SLR_L | | | | | This is an MXPR Operation with B Select |
| |===================~~~~~~~~~~xxxxx=====| SLR |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM1 Last Updated: 9/30/86 |
| C Load = 1.17 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 245
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_B_SEL_VAP_L | | | | | This is a BASIC Inst. with B Select VAP |
| |===================~~~~~~~~~~xxxxx=====| |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM1 Last Updated: 9/30/86 |
| C Load = 1.03 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_B_SEL_VA_L | | | | | This is a BASIC Inst. with B Select VA |
| |===================~~~~~~~~~~xxxxx=====| |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM1 Last Updated: 9/30/86 |
| C Load = 1.02 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_B_SEL_VIBA_L | | | | | This is a BASIC Inst. with B Select VIBA |
| |===================~~~~~~~~~~xxxxx=====| |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM1 Last Updated: 9/30/86 |
| C Load = 1.22 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_C_SEL_VAP_H | | | | | This is a MEM_REQ Inst. with VAP |
| |===================~~~~~~~~~~xxxxx=====| |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM2 Last Updated: 9/30/86 |
| C Load = 1.39 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 246
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_C_SEL_VA_H | | | | | This is a MEM_REQ Inst. with VA |
| |===================~~~~~~~~~~xxxxx=====| |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM2 Last Updated: 9/30/86 |
| C Load = 1.62 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_LD_VAP_ADD_H | | | | | Possible Load VAP with the +4-Adder Result |
| |===================~~~~~~~~~~xxxxx=====| |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM2 Last Updated: 9/30/86 |
| C Load = 0.86 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_MISC_VAP_L | | | | | This is a MISC VAP Inst. |
| |===================~~~~~~~~~~xxxxx=====| |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM1 Last Updated: 9/30/86 |
| C Load = 1.51 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_MISC_VA_L | | | | | This is a MISC VA Inst. |
| |===================~~~~~~~~~~xxxxx=====| |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM1 Last Updated: 9/30/86 |
| C Load = 1.02 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs early in PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 247
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_MXPS_MMGT_H | | | | | This is a MEM_REQ MXPS (Spur Transfer) |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| with MMGT.STATUS as the source/dest. |
| | | | | | * Simulated with 1.5pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM5 Last Updated: 9/30/86 |
| C Load = 0.75 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mut early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_MXPS_MODE_H | | | | | This is a MEM_REQ MXPS (Spur Transfer) |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| with PROBE.MODE as the source/dest. |
| | | | | | * Simulated with 1.5pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM5 Last Updated: 9/30/86 |
| C Load = 0.68 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mut early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RAW_PREFETCH_CYCLE_H | | | | | Thiis is possibly a PREFETCH Cycle |
| |===================__________xxxxxx====| |
| | | | | | * Simulated with 2.0pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM5 Last Updated: 9/30/86 |
| C Load = 0.99 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mrs,mst early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RD_IN_PROG_H | | | | | There is a MEM_REQ Read in Progress (i.e |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| missed the cache and went external) |
| | | | | | * Simulated with 3.6pF |
| Spice Ref (Block/Text): M_STATE_SIM MST3 Last Updated: 9/30/86 |
| C Load = 3.83 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mst PHI3 + 15ns mdpc,mic,mmd early in PHI4 No |
| mrc |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 248
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RD_P0LR_B_H | | | | | Put P0LR on the B_Bus |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.90 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI1 + 05ns mlr early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RD_P1LR_B_H | | | | | Put P1LR on the B_Bus |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.90 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI1 + 05ns mlr early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RD_SLR_B_H | | | | | Put SLR on the B_Bus |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.94 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI1 + 05ns mlr early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RD_VAP_B_H | | | | | Put VAP Register contents on the B_Bus |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.54 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI1 + 05ns mlr early in PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 249
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RD_VAP_C_H | | | | | Put VAP Register Contents on the C_Bus |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 3.93 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI1 + 05ns mlr early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RD_VA_B_H | | | | | Put VA Register contents on the B_Bus |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.52 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI1 + 05ns mlr early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RD_VA_C_H | | | | | Put VA Register contents on the C_Bus |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 3.93 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI1 + 05ns mlr early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RD_VIBA_B_H | | | | | Put VIBA Register contents on the B_Bus |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.51 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI1 + 05ns mlr early in PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 250
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%RD_VIBA_C_H | | | | | Put VIBA Register contents on the C_Bus |
| |xxxx===============~~~~~~~~~~xxxxxxxxxx| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 3.80 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI1 + 05ns mlr early in PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
| | | | | | |
| M_S%READ_CHECK_H | | | | | Check Read Access on this MREQ |
| |===================~~~~~~~~~~xxxxxx====| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.92 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mpl early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%READ_PTE_OK_L | | | | | Control signal to read a PTE Entry |
| |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~xx========| (i.e. write too the PFN and PROT Cell) |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 6.22 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI4 + 05ns mhit early in PHI4 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%REEXECUTE_L | | | | | Re-Execute (MMGT_REXE) Bit |
| |xx=====================================| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.69 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mps PHI1 + 05ns mts early in PHI2 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 251
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%REPROBE_L | | | | | Re-Probe (REPROBE) Bit |
| |xx=====================================| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.84 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mps PHI1 + 05ns mdpc,mts,mut early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ROT0_H | | | | | Rotate Data (from or too IDAL) 0-Bytes |
| |xx=======____________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 6.80 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrc PHI1 + 05ns mts early in PHI1 No |
| PHI4 + 05ns early in PHI4 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ROT0_L | | | | | Rotate Data (from or too IDAL) 0-Bytes |
| |xx=======~~~~~~~~~~~~~~~~~~~~xx========| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 5.92 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrc PHI1 + 05ns mts early in PHI1 No |
| PHI4 + 05ns early in PHI4 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ROT1_H | | | | | Rotate Data (from or too IDAL) 1-Bytes |
| |xx=======____________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 6.84 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrc PHI1 + 05ns mts early in PHI1 No |
| PHI4 + 05ns early in PHI4 |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 252
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ROT1_L | | | | | Rotate Data (from or too IDAL) 1-Bytes |
| |xx=======~~~~~~~~~~~~~~~~~~~~xx========| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 5.82 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrc PHI1 + 05ns mts early in PHI1 No |
| PHI4 + 05ns early in PHI4 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ROT2_H | | | | | Rotate Data (from or too IDAL) 2-Bytes |
| |xx=======____________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 6.72 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrc PHI1 + 05ns mts early in PHI1 No |
| PHI4 + 05ns early in PHI4 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ROT2_L | | | | | Rotate Data (from or too IDAL) 2-Bytes |
| |xx=======~~~~~~~~~~~~~~~~~~~~xx========| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 5.78 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrc PHI1 + 05ns mts early in PHI1 No |
| PHI4 + 05ns early in PHI4 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ROT3_H | | | | | Rotate Data (from or too IDAL) 3-Bytes |
| |xx=======____________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 6.74 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrc PHI1 + 05ns mts early in PHI1 No |
| PHI4 + 05ns early in PHI4 |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 253
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ROT3_L | | | | | Rotate Data (from or too IDAL) 3-Bytes |
| |xx=======~~~~~~~~~~~~~~~~~~~~xx========| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 5.62 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrc PHI1 + 05ns mts early in PHI1 No |
| PHI4 + 05ns early in PHI4 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ROT_DRIVE_H | | | | | Rotate Driver Control Signal |
| |xx=======____________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 2.28 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI1 + 05ns mrc early in PHI1 No |
| PHI4 + 05ns early in PHI4 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%SELECT_MW_H | | | | | MW Bus data is to go too W-Bus |
| |xx=======____________________xx========| |
| | | | | | * Simulated with 1.5pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM8 Last Updated: 9/30/86 |
| C Load = 0.94 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mst early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%SEL_MODE_H | | | | | Selects the 'mode' of Protection to check |
| |===================~~~~~~~~~~xxxxxx====| (psl.curr or mode) |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.04 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mpl early in PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 254
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%TAG_H<31:9,2:0> | | | | | The TAG Bus (used to find a CAM Match) |
| |xxxx=========================xxx_______| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL TOO_IDAL_NEW Last Updated: 9/30/86 |
| C Load = 2.67 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mar PHI1 + 18ns mdrv,mtag late in PHI1 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%TAG_L<31:9> | | | | | The TAG Bus (used to find a CAM Match) |
| |xxxx=========================xxx~~~~~~~| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL TOO_IDAL_NEW Last Updated: 9/30/86 |
| C Load = 2.28 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mar PHI1 + 18ns mtag late in PHI1 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%TBV_RESET_H | | | | | Clear (TB.V=0) TB entry pointed at by NLU |
| |___________________xxxx======xxx_______| on a TB miss or an ZAP.TB(HIT).IF.HIT |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 2.61 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdrv PHI3 + 05ns mhit early in PHI3 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%TB_HIT_H | | | | | Translation IS enabled, and there was a |
| |_________xxxxxxxxxx==========xxxxxxx___| hit in the TB |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 0.64 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI2 + 16ns mdpc,mut late in PHI2 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 255
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%TB_MISS_H | | | | | Translation IS enabled, and there was a |
| |_________xxxxxxxxxx==========xxxxxxx___| MISS on the TB |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.30 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI2 + 16ns mts late in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%TNV_H | | | | | TNV error (Translation Not Valid, PTE.V=0) |
| |_________xxxxxxxxxx==========xxxxxxx___| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL TOO_IDAL_NEW Last Updated: 9/30/86 |
| C Load = 1.22 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mts PHI2 + 21ns mdpc,mut early in PHI3 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%UNALIGNED_H | | | | | This reference is un-aligned |
| |_________xxxxxxxxxx==========xxxxxxx___| |
| | | | | | |
| Spice Ref (Block/Text): M_UNALIGNED_SIM SIM1 Last Updated: 9/30/86 |
| C Load = 1.13 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mua PHI2 + 09ns mst,mts early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%UTEST_MBOX_STAT_H | | | | | Write MBOX.STATUS to uTEST Bus |
| |===================~~~~~~~~~~xxxxxx====| |
| | | | | | * Simulated with 1.5pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM4 Last Updated: 9/30/86 |
| C Load = 0.73 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mut early in PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 256
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%UTEST_MMGT_STAT_H | | | | | Write MMGT.STATUS to uTEST Bus |
| |===================~~~~~~~~~~xxxxxx====| |
| | | | | | * Simulated with 1.5pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM4 Last Updated: 9/30/86 |
| C Load = 0.76 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mut early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%UTEST_MREF_STAT_H | | | | | Write MREF.STATUS to uTEST Bus |
| |===================~~~~~~~~~~xxxxxx====| |
| | | | | | * Simulated with 1.5pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM4 Last Updated: 9/30/86 |
| C Load = 0.74 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mut early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%UTEST_PSL_H | | | | | Write PSL Bits to uTEST Bus |
| |===================~~~~~~~~~~xxxxxx====| |
| | | | | | * Simulated with 1.5pF |
| Spice Ref (Block/Text): M_MIB_DEC SIM4 Last Updated: 9/30/86 |
| C Load = 0.75 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mut early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%WRITE_CHECK_H | | | | | Check Write Access on this MREQ |
| |===================~~~~~~~~~~xxxxxx====| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.03 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI4 + 15ns mpl early in PHI1 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 257
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%WR_CHECK_H | | | | | Latched version of M_S%WRITE_CHECK_H |
| |xxxx===================================| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.46 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mmd PHI1 + 15ns mts,mut early in PHI2 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%WR_ENABLE_H<3:1> | | | | | Enable IDAL drivers, for both Data and |
| |_________xx========xx__________________| Address writes |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 5.61, 11.22, 2.75 pF for <3>, <2> and <1> |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mic PHI2 + 05ns mdrv early in PHI2 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%WR_PFN_H | | | | | Drive data from the IDAL up to the PTE |
| |xx___________________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 3.36 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mic PHI4 + 05ns mdrv early in PHI4 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%WR_PFN_L | | | | | Drive data from the IDAL up to the PTE |
| |xx~~~~~~~~~~~~~~~~~~~~~~~~~~~xx========| |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 4.73 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mic PHI4 + 06ns mdrv early in PHI4 No |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 258
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%WSEL_P0LR_H | | | | | Write to the P0LR from the W-Bus |
| |xx___________________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.15 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI4 + 05ns mlr early in PHI4 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%WSEL_P1LR_H | | | | | Write to the P1LR from the W-Bus |
| |xx___________________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.14 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI4 + 05ns mlr early in PHI4 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%WSEL_SLR_H | | | | | Write to the SLR from the W-Bus |
| |xx___________________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.18 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI4 + 05ns mlr early in PHI4 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%WSEL_VAP_H | | | | | Write to VAP Register from the W-Bus |
| |xx___________________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.54 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI4 + 05ns mar early in PHI4 Yes |
| |
^------------------------------------------------------------------------------------------------------------------^
CVAX CPU CHIP DESIGN SPECIFICATION Page 259
MEMORY (M) BOX
+----------+---------+---------+----------+
MBOX INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| COMMENTS |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%WSEL_VA_H | | | | | Write to VA Register from the W-Bus |
| |xx___________________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.54 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI4 + 05ns mar early in PHI4 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%WSEL_VIBA_H | | | | | Write to VIBA Register from the W-Bus |
| |xx___________________________xx========| |
| | | | | | |
| Spice Ref (Block/Text): M_REG_SEL Last Updated: 9/30/86 |
| C Load = 2.40 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mrs PHI4 + 05ns mar early in PHI4 Yes |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%W_PSL_H<26:24> | | | | | The Double Buffered PSL Bits (buffered |
| |xxx==========================xxxxxxxxxx| W_BUS<26:24>) |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.03 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mar PHI1 + 05ns mdpc early in PHI1 No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| M_S%ZAP_TB_H | | | | | Clear (TB.V=0) the entire TB on a ZAP.TB |
| |_________xx========xx__________________| or during a global reset |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/30/86 |
| C Load = 1.98 pF |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| mdpc PHI2 + 06ns mhit early in PHI2 Yes |
| |
^------------------------------------------------------------------------------------------------------------------^
4.4 ISSUES
CVAX CPU CHIP DESIGN SPECIFICATION Page 260
MEMORY (M) BOX
1. What happens to TB.V on a PPTE load with a ACV/TNV or other uTrap
and MMGT_TD=1? If loaded anyway then you've got to clean it out.
ANS: 2-Apr-85 R.M.S. - Although a trap isn't taken because
MMGT_TD = 1, the PTE is not written and TB.V is not set.
ZAP.TB(NLU) is no longer necessary. Must assert BIU_NOP.
2. Does microcode guarantee that the Read Interrupt Vector uinstr is
always aligned or is it done in hardware?
ANS: ? A.O. - microcode guarantees.
3. Does PSL<26:24> get loaded into the M Box from the WBUS or the
WSPUR ?
ANS: ? D.S. - PSL<26:24> are loaded from W_BUS<26:24>.
4. Can VIBA be incremented at the end of a cycle or does it have to
wait till it gets IB_DATA_PRS, if so it must keep a temporary
copy of the incremented VIBA.
ANS: 25-Mar-85 A.O. - increment it, add status bit to
MREF.STATUS?
5. Are PROBES guaranteed not to cause crosspages by being aligned or
inhibiting crosspage checking?
ANS: ? A.O. - No, PROBEs are not aligned, don't invoke
crosspage checking.
6. Does the VIBA register have bits <1:0>, or on reads are they just
driven to zero? This may limit other uses of VIBA.
ANS: 20-Apr-85 A.O. - bits<1:0> must be read as zeroes.
7. Do registers that read from W_Spur have to drive all 8-bits?
ANS: ? A.O. - Yes, all bits must be driven to a legal value,
8. M Box may have to STALL any MREQ or Broadcast on the cycle
following a write.
ANS: 1-May-85 A.O. - The BIU will assert MSTALL during the data
portion of a write cycle. The M Box then stalls the machine if
any MREQ is detected on the cycle following the write. Once a
write MREQ starts, the write data is sent out on the IDAL
irrespective of MSTALL. Broadcast cycles that follow a write
MREQ require no special action.
CVAX CPU CHIP DESIGN SPECIFICATION Page 261
CACHE
5 CACHE
The idea behind a cache is that data recently referenced is likely to be
referenced again, and that data near that reference is also likely to be
used. By storing this data in a high speed, on chip memory, both bus
traffic and data access time are reduced.
A cache entry consists of both the address (address<28:9>) and data from a
memory reference. The address is stored in a tag array at the location
specified by bits<8:3> of the virtual address. Each address stored in the
tag array is associated with seventy two bits of data. A valid bit is
associated with each cache entry, and is used to determine whether the
data is present in the cache.
When the CPU requires data from the main memory, it first checks the cache
to see if that data is stored in the cache. Virtual address bits<8:3> are
used to index into the tag and data arrays. If the address stored in that
tag location matches the current physical address and the valid bit is
set, there is a hit in the cache and 32-bits of data are driven onto the
IDALs. Parity is also checked on the tag entry to make sure that data has
not been corrupted in the array. If there is a tag parity error, the CPU
is informed and the cache is flushed.
The combination of a tag array and data array in a cache is called a set.
The cache currently being designed contains two sets. When data is
written to the cache, the set allocated to store the data is determined by
a random allocation scheme. On a cache read, both tag entries are checked
to see if the data is present in the cache.
The cache can be broken down into five sections (See Figure below):
1. Ram Array and Sense Amps
2. Address Selection and Decode
3. Tag Data Path
4. Data Array Drivers
5. Cache Control
CVAX CPU CHIP DESIGN SPECIFICATION Page 262
CACHE
+---------
| ADR<1:0>
V
+-------------------------------------+ +----------+ REF
| | | |<---6
| | | ADDRESS | MBX 6
| RAM ARRAY | | SELECTION|<----------+-
| |<---| AND | DMA |
| | 64 | DECODE |<---6 |
| | | | OLD +---+ |
| | | |<----| O |6|
+-------------------------------------+ +----------+ 6 | L |-+
| SENSE AMPS |<-+ | | D |
+-------------------------------------+ | +----------+ +---+
^ ^ | | | CTL
|88 |288 +-| |<---3
V V | | MISC
+------------+ +---------------------+ | CACHE |<---4
| | | | | CONTROL | OUT
+-->| TAG DATA | | DATA ARRAY DRIVER |<---| |--->3
| | PATH | | | | | BTMK
| | | | | +->| |<---4
| +------------+ +---------------------+ | +----------+
| ^ 20 ^36 |
| | | |
+---------)----------------------)----------+
| |
| V
======================================================================
IDAL<31:0> + PARITY
5.1 Ram Array And Sense Amps
The ram array is 33 cells in the short dimension and 376 cells in the long
dimension. The cell implemented is a one transistor dynamic ram cell with
a storage capacitance of 110 fF. The ram array uses a folded bit line
structure. In a folded bit line implementation the two bit lines that are
being sensed are located next to each other in the array. The array also
incorporates a dummy cell which is used in place of a voltage reference.
The dummy cell contains a storage capacitance half that found in the
storage cell. When data is read from the array, the actual storage cell
is read onto one bit line, and the dummy cell is read onto the other.
Since the dummy cell has half the capacitance of the storage cell, it will
only take half as much charge off its bit line.
The sense amp detects the difference in charge between the two bit lines,
and amplifies it. The output from the sense amp is data and data_bar,
each driven to the rail.
CVAX CPU CHIP DESIGN SPECIFICATION Page 263
CACHE
The only exception in the array is the valid bit. In order to simplify
the cache flush operation, the cell which stores the valid bit differs
from the rest of the array. The storage capacitance of the valid bit cell
will be twice that of other storage cells. The dummy cell associated with
the valid bits will also have twice the capacitance of the other dummy
cells. Another difference is that there will be a pulldown in the cell
which will clear the valid bit on a cache flush operation. Because of the
larger cell size, the valid bit will not be included in the parity
generation/checking. This eliminates the need for inverting the parity
bit on a flush of the cache.
5.2 Address Selection And Decode
The cache can receive its address from four sources:
1. M Box address
2. Refresh Counter
3. DMA address
4. Latched M Box address
Each address is six bits wide. These addresses are brought into a four to
one multiplexer (MUX) which selects the appropriate address via the two
address select lines. The two address select lines are decoded locally
and driven into the MUX. The decode for the address select lines is as
follows:
g_s%cache_addr_src<1> | g_s%cache_addr_src<0> | Address Selected
------------------------------------------------------------
0 | 0 | Refresh Address
0 | 1 | M Box Address
1 | 0 | Latched M Box Address
1 | 1 | DMA Address
The selected address is latched on phase two and driven into the first
stage of the row decoder. This stage does some of the initial decode and
avoids having long AND stacks in the row decoder. The outputs from the
first stage are decoded further by the final stage of the row decoder and
the appropriate row is enabled in the ram array.
If the address selected by the address multiplexer was an M Box address,
the address is latched into the Latched M Box address register on phase
two. This address is used to address into the ram array during cache
write operations.
The DMA address is used to check if a DMA transfer is changing a memory
CVAX CPU CHIP DESIGN SPECIFICATION Page 264
CACHE
location that is currently in the cache. A cache read is performed with
the DMA address and if a hit occurs, the data in the cache must be
invalidated.
The refresh address is required in order to make sure that the data stored
in the cache does not leak away. Because the storage cell is dynamic, the
charge stored on the capacitor has to be refreshed. The refresh address
makes sure that every location in the cache is refreshed.
5.3 Tag Data Path
The tag data path is responsible for getting data into the tag array,
generating and checking parity, and determining if there is data in the
cache. The tag data path consists of the following logic blocks (see
Figure below):
1. M Box Address Latch
2. Parity Generator/Checker
3. Match Address Latch
4. Match Address Drivers
5. Address Match Detection
6. Tag Write Multiplexer
CVAX CPU CHIP DESIGN SPECIFICATION Page 265
CACHE
Note : All busses contain true and complement data (except IDALs).
TO TAG ARRAY1 TO TAG ARRAY0
^ ^
|44 |44
+-----------------------+
Write Tag 1 --->| Tag Write Mux |
Write Tag 0 --->| |
+-----------------------+ |FROM BOTH TAG ARRAYS
Valid ^ ^ ^ |84
-------+4 |4 | 40 +----------+
Parity | +------(----------+
-----------+ | |
V |
+-----------------------+ |
| Address Match Detect |-----(-----> Match Set 0
| (21 bits) |-----(-----> Match Set 1
+-----------------------+ |
^ |
|42 |
| |
+-----------------------+ |
| Match Address Drivers | |
Match Enable--->| | |
+-----------------------+ |
2 ^ ^ |
Valid Bit ------+ | |
|40 |
| |
+-----------------------+ |
| Match Address Latch |<----(---- phi2
| | |
+-----------------------+ |
To Tag write mux ^ |
^ Parity Bits |20 |
|4 from tag array +---------+ |
+-------+ |4 | |
| V | |
+-----------------------+ | |
Tag Parity Error <---| Parity Gen/Check | | |
| (21 bits) | | |
+-----------------------+ | |
^ | |
| | |
+--------------(--+
|40 |
+-----------------------+ |
| M Box Address Latch |<-(---- M Box Address strobe
+-----------------------+ |
^ 20 |
| | IDAL
============================+==============+===============
CVAX CPU CHIP DESIGN SPECIFICATION Page 266
CACHE
5.3.1 M Box Address Latch -
The M Box Address Latch samples the IDAL whenever an M Box address is
indicated on the g_s%cache_addr_src<1:0> lines. During a cache write
operation, the data stored in the M Box address latch is written into the
tag array. Tag parity is also calculated using the address stored in the
M Box address latch.
5.3.2 Parity Generator/Checker -
The parity generator calculates parity only on the physical address stored
in the M Box address latch. On a cache write operation, the tag parity is
calculated and driven into the tag array. On a cache read cycle, tag
parity is calculated and compared to the parity bit stored in the tag
array. If the calculated parity is different from the stored parity and
the read operation resulted in a cache hit, then a tag parity error is
reported to the BIU. The tag parity error signal is valid midway through
phase four. A tag parity error is NOT reported on a cache miss. A tag
parity check is only performed when an mbox address is decoded from the
cache address source lines. Tag parity is not checked during a DMA
invalidate look up.
5.3.3 Match Address Latch -
The match address latch samples the IDAL every phase two. This latch is
primarily used to store either the DMA address or the M Box address. To
determine if there is stale data in the cache, a cache read is performed
using the DMA address. If there is a hit in the cache, the cache entry
must be invalidated. The M Box address is used to determine if there is
current data in the cache.
5.3.4 Address Match Detection -
During a cache read, the data from both tag arrays is compared to the
current physical address. The valid bits from both tag arrays are also
compared to a one. If the two addresses are identical and the valid bit
is true, a cache hit is signaled to the bus interface unit. If the data
from the matching set is required by the bus interace unit, the data is
driven onto the IDALs at the beginning of phase four.
5.3.5 Tag Write Mux -
The physical address bits <28:9> can be stored in one of two tag arrays.
The tag write mux places the address into the tag array determined by the
cache allocation logic.
CVAX CPU CHIP DESIGN SPECIFICATION Page 267
CACHE
5.4 Data Array Drivers
The data array drivers are primarily responsible for getting data into and
out of the data array. The data array driver is composed of three logic
blocks;
1. IDAL Input Buffer
2. Data Multiplexer
3. IDAL Output Buffer
CVAX CPU CHIP DESIGN SPECIFICATION Page 268
CACHE
To/From Ram array
^
|144
V
+----------------------+---------------+
| Data Mux |<-- Mux Ctrl<3:0>
| |
+--------------------------------------+
| ^ |
+--------+ |36 +------------+
| | |
| +---------------------------------------+ |
| | Input Buffer |<---(-- Data_Enable
| | |<---(-- Data_in
| +---------------------------------------+ |
| ^ ^ |
| |4 |32 |
| | | |
| | +-------------------------(-----------+
| +------+ | |
| | | |
+--)----------+ +------------+ |
| |36 |36 |
Parity Logic V V |
+---------------+ +---------------+ |
Phi3 --->| Output Latch | | Output Latch |<--- Phi3 |
| | | | |
+---------------+ +---------------+ |
|36 |36 |
V V |
+---------------------------------------+ |
| Output Multiplexer | |
| |<--- Match_set1 |
+---------------------------------------+ |
|36 |
V |
+---------------------------------------+ |
| Output Driver |<--- Phi4 |
| | |
+---------------------------------------+ |
| |
|36 |
IDAL V |
=========================================================================+====
5.4.1 IDAL Input Buffer -
The IDAL input buffer stores the 36-bits of data which will be written
into the cache. The data is valid at the cache on two different phases
CVAX CPU CHIP DESIGN SPECIFICATION Page 269
CACHE
depending on where the data is sourced. If the data is coming from the
MBOX, it is sampled on phase three, and if the data is coming from the
BIU, it is valid on phase one. The cache uses the read cycle which occurs
prior to the write to determine when to latch data. If a read with data
cycle was indicated, the data is latched on phase one. Otherwise, the
data is sampled on phase three.
The data input buffer for each parity bit of the data array, stores either
the correct parity bit or the inverted parity bit. The inverted parity
bit is stored in the array in order to test the parity checking logic of
the bus interface unit. The parity bits are not read from the four IDAL
parity lines, but are direct inputs from the four IDAL parity generators.
The data input buffer also allows for byte, word, and longword writes to
the cache. The four byte mask inputs are used to drive only the specified
bytes into the data multiplexer.
5.4.2 Data Multiplexer -
On a cache read operation, the data multiplexer determines which longword
(two longwords accessed simultaneously from each set) is latched into the
output buffer. The data multiplexer uses physical address bit<2> to
select the appropriate longword.
On a cache write, the data multiplexer uses the set select input and
physical address bit<2> to determine where to write the incomimg data.
The set select input is used to write the allocated set, and physical
address bit<2> determines which longword within the quadword block.
5.4.3 IDAL Output Buffer -
The IDAL output buffer latches the information from a cache read
operation, and enables the data onto the IDAL on phase four depending on
the following set of conditions. Data is driven on the IDALs only when it
is requested by the bus interface unit. The data from set one is driven
if there was a hit in set one. Data from set two is driven on a miss in
set one. This scheme insures that the IDAL is always driven during phase
four on a cache read-with-data cycle.
Because it is possible to hit in both sets (parity error) it has to be
guaranteed that the two output drivers are not both enabled. By driving
data from set two only on a miss in set one, you assure that there will
not be a conflict. This scheme also guarantees that data will be driven
when the cache misses in both sets.
5.5 Cache Control
CVAX CPU CHIP DESIGN SPECIFICATION Page 270
CACHE
The cache control logic performs the following functions:
1. Operation Decode
2. Set Selection
3. Multiple Write Control
4. Refresh Counter
5.5.1 Operation Decode -
The cache receives two encoded control lines, and one dedicated flush
signal from the bus interface unit. These lines determine what cache
operation is performed. The table below summarizes the decode of the two
encoded control lines.
g_s%cache_fcn<1> g_s%cache_fcn<0> OPERATION
----------------+-----------------+-----------
0 | 0 | READ WITH DATA
0 | 1 | READ NO DATA
1 | 0 | CACHE WRITE
1 | 1 | INVALIDATE
The two other cache operations, refresh and flush, are not encoded in the
cache function control lines. A refresh cycle is requested via the cache
address source control lines. Whenever the refresh address is decoded
from the cache address source signals, a refresh operation is performed.
The cache flush operation has its own dedicated control line.
The refresh operation restores the stored charge inside the ram cell. One
row of the ram array is read each refresh cycle. No action is taken on
the data except to write it back into the ram array. All match detection
logic is disabled during a refresh. The row address is generated by a
six-bit refresh counter.
The cache write operation stores both the address and data from a given
memory reference. The physical address is stored in the tag array, the
data (byte,word,longword) is stored in the data array, parity is generated
for the tag entry, and the valid bit for the cache entry is set to one.
If the cache operation is a cache fill, the valid bit is set to one only
after the second longword write. If the cache operation is a write
through, the valid bit is always written to a one.
If the cache has valid data for a given memory location, and that memory
location has been altered without updating the cache, the cache entry must
be invalidated. The invalidate operation clears the valid bit for the
CVAX CPU CHIP DESIGN SPECIFICATION Page 271
CACHE
cache entry, removing that memory location from the cache.
The flush operation clears out the cache. On a flush, every valid bit in
both tag arrays is set to zero. Because the valid bit is not part of the
parity calculation, no other data manipulation has to be performed. A
flush is performed on the following phase one. A cache flush operation
also initializes the set allocation logic. In the case of a tag parity
error on a cache read no data cycle, it is possible for the GS%FLUSHH
signal to be active at the same time as a write operation is being
requested. In this case, the cache write is performed, and the cache is
flushed on the following phase one.
The last cache operation is the cache read. The cache read no data
operation does not enable data onto the IDALs. The read without data
cycle checks to see if there is data stored in the cache for the current
physical address. If so, it reports a cache hit but does not drive data.
The second type of cache read is the normal cache read operation. If
there is valid data in the cache for the current physical address, a hit
is reported and data is driven onto the IDALs at the beginning of phase
four.
5.5.2 Set Selection -
The set selection logic determines which set to access on a write, and
which set hit on a read. On a cache write operation, the set written is
allocated with the following logic equations:
c_set1_select = (cache_miss AND g_s%set1_en_h AND
(NOT(g_s%set2_en_h) OR NOT(random)) OR c_hit_set1) AND write
c_set2_select = (cache_miss AND g_s%set2_en_h AND
(NOT(g_s%set1_en_h) OR random) OR c_hit_set2) AND write
These equations state that on a write, a set is allocated for the
following three reasons:
1. The set is enabled, there was a cache miss, and the random master
slave flip-flop is pointing to the set ( i.e a zero signifies set
1).
2. The other set is disabled.
3. The read, before the write, hit in the set.
On a cache read the set that matched is determined by the address match
detection logic. A cache hit is determined by the following logic
equations:
CVAX CPU CHIP DESIGN SPECIFICATION Page 272
CACHE
c_hit_set1 = (match_set1 AND g_s%set1_en_h AND read)
c_hit_set2 = (match_set2 AND g_s%set2_en_h AND read)
g_s%cache_hit_h = (c_hit_set1 OR c_hit_set2) AND read
The signal which tells the bus interface unit which set is being allocated
on a cache miss is simply:
g_s%alloc_set_h = c_set1_select
Where g_s%alloc_set_h is a one when set one is accessed and a zero when set
two is accessed.
The random master slave flip-flop determines which set is allocated after
a cache miss. The flip-flop is clocked every cycle in order to generate a
fairly random event. The random flip-flop is initialized to one during a
cache flush operation in order to create a reproducible environment for
the cache test patterns.
5.5.3 Multiple Write Control -
While filling the cache, it is possible to have two consecutive write
cycles without having the physical address updated. In order to write the
correct longword, physical address bit<2> must be inverted after the first
cache write. In order to accomplish this function, the fact that a cache
write has taken placed has to stored. If another write occurs, the output
from the write latch is exclusive-ored with the latched physical address
bit<2> in order to write the other longword. If a cache read occurs
between two write cycles, the write latched is cleared and physical
address bit<2> is not inverted.
5.5.4 Refresh Counter -
The refresh counter is required to make sure that every location in the
ram array is refreshed. It is a six bit counter and is incremented at the
end of a refresh operation. The refresh counter is implemeted as a linear
feedback shift register. The most significant bit of the refresh counter
is sent to the master reducer in order to ensure the proper operation of
the counter.
5.6 Cache Timing
CVAX CPU CHIP DESIGN SPECIFICATION Page 273
CACHE
0 2 4 6 0 2 4 6 0 2 4 6 0
0 3 6 9 0 3 6 9 0 3 6 9 0
+----+----+----+----+----+----+----+----+----+----+----+----+
g_pl%cash_bus ____/~~~~~~~~~~~\_______________________________
g_s%dma_inv_addr____/~~~~~~~~~~~\_______________________________
g_s%cache_adr_src___/~~~~~~~~~~~~~~~\______________ Rising edge 3-5ns before T23
g_s%idal_parity _______________/~~~~~~~~~\________ Idal parity driven by cache
g_s%wrong_parity___________/~~~~~~~~~~~~~~\_______ For cache write
g_s%cache_oper ____/~~~~~~~~~~~~~~\______________
g_s%byte_mask _____/~~~~~~~~~~~~~~~~\____________
g_s%cache_hit _________________/~~~~~~~\________
g_s%alloc_set_h _________________/~~~~~~~~~~~~~~~~
g_s%t_par_err_h _________________/~~~~~~~\________
g_s%idal ________________/~~~~\____________ On a cache read
CVAX CPU CHIP DESIGN SPECIFICATION Page 274
BUS INTERFACE UNIT (BIU)-
6 BUS INTERFACE UNIT (BIU)-
The BIU controls the internal data and address bus (IDAL), the external
data and address bus (DAL), the CFPA status lines (CPSTA), CFPA data lines
(CPDAT), and several other pins as discussed later. The following
operations are controlled by the BIU:
1. Memory reads - this includes reads of cached data as well as data
resident in main memory
2. Memory writes - this involves writing to both cache (if the data
is cached already) and main memory
3. External Processor Register (EPR) reads - data read operations
from registers not resident on the CVAX chip
4. External Processor Register (EPR) writes - data writes to
registers not resident on the CVAX chip
5. Interrupt Acknowledge Read Cycles
6. DMA Cache Invalidate Operations - During a DMA cycle, the owner
of the DAL may request that a cache location be invalidated.
6.1 BIU Controlled Pins
The BIU controls and/or monitors the following CVAX CPU chip pins:
Signals Signal Type Number of Pins
------- ----------- --------------
Cycle status/parity I/O 4
Data and Address I/O 32
Data parity enable I/O 1
Address strobe I/O 1
Data strobe O 1
Byte mask O 4
Write O 1
Data buffer enable O 1
Ready I 1
Error I 1
DMA request I 1
DMA grant O 1
Cache control I 1
FP Unit data I/O 6
FP Unit status I/O 2
Refer to the CVAX CPU External Specification for a description of each of
these pins.
CVAX CPU CHIP DESIGN SPECIFICATION Page 275
BUS INTERFACE UNIT (BIU)-
6.1.1 Internal Pin Names -
The following table shows the input/output characteristics for each pin
and internal signal names mapping to each pin.
Internal signal Pin Name Function Type
--------------- -------- -------- ----
P_S%DAL_H<31:0> DAL<31:0> H data and address lines IO
P_S%CS/DP<3:0> CS/DP<3:0> L cycle status & dal parity IO
P_S%BYTE_MASK_L<3:0> BM<3:0> L byte mask IO
P_S%DPE_L DPE L DAL parity enable IO
P_S%AS_L AS L address strobe IO
P_S%DS_L DS L data strobe IO
P_S%DBE_L DBE L enables data buffers IO
P_S%WRITE_L WR L write cycle indicator IO
P_S%READY_L RDY L memory system ready I
P_S%ERROR_L ERR L memory system error I
P_S%DMR_L DMR L DMA request I
P_S%DMG_L DMG L DMA GRANT O
P_S%CCTL_L CCTL L cache control I
P_S%CP_DAT_L<5:0> CPDAT<5:0> H CFPA data IO
P_S%CP_STA_L<1:0> CPSTA<1:0> H CFPA status IO
6.2 BIU Controlled Internal Bus - IDAL BUS (G_S%IDAL_H<31:0>)
The IDAL is driven from either the DAL input buffers, cache or the M Box.
If the operation in progress is a read from memory, read from EPR, or
interrupt acknowledge, the M BOX drives the IDAL with the required address
during PHI2 and PHI3. If the reference is cacheable, the cache is
accessed and drives data to the IDAL during PHI4 and PHI1. If the memory
reference has accessed external memory, the DAL buffers will drive the
IDAL during PHI4 and PHI1 with the returned data. If the operation in
progress is a write to memory, the M BOX sends the address during one
cycle as described above, followed by the data during the next PHI2 and
PHI3. If the operation in progress is a conditional DMA cache invalidate,
the DAL buffers will send the address to the IDAL during PHI2 and PHI3.
6.3 BIU Logic Blocks
6.3.1 IDAL Control Machine -
The IDAL controller controls the following: arbitrates the usage of DAL's
and strobe lines;latching of outgoing address and data at the DAL pads;
source of address used by the cache; cache function code; stall of the M
BOX; FLUSH operations in the cache; updating of the CADR and MSER
registers. This machine evaluates its inputs during PHI4 and updates to
its next state in PHI1. A PLAD description for the IDAL state machine can
be found in section 6.5.
CVAX CPU CHIP DESIGN SPECIFICATION Page 276
BUS INTERFACE UNIT (BIU)-
6.3.2 DAL Control Machine -
The DAL controller controls the following: all pads as listed above; bus
grant for DMA operations; bus locking for interlocked operations. The DAL
machine evaluates inputs and updates outputs during PHI2. A PLAD
description for the DAL state machine can be found in section 6.6.
6.3.3 Cache Disable Register (CADR) -
CADR control the operation of the cache. It is read and written on the
W_SPUR bus by an MXPS1 microinstuction with a MEMREG.REG encoding of CADR
(1).
7 6 5 4 3 2 1 0
+---+---+---+-+-+
|SEN|CEN| |W|D|
| | |1 1|W|I| : CADR
| | | | |A|
+---+---+---+-+-+
CADR<3:2> are not implemented in the BIU, and therefore will read as 11 on
the W_SPUR. CADR<7:4,1:0> are read/write and are undefined at power up.
If CADR<0> is 0, the cache flush signal G_S%FLUSH_H is asserted when the
CADR is written. The signal is inhibited when CADR<0> is 1.
CADR <7:6> (Set Enable) are read/write and are encoded as follows:
<7:6> Set 2 Set 1
----- ----- -----
00 disabled disabled
01 disabled enabled
10 enabled disabled
11 enabled enabled
CADR <5:4> (Cache Enable) are read/write and are encoded as follows:
<5:4> Action
----- ------
00 Cache disabled
01 D-stream only stored in cache (diagnostic use)
10 I-stream only stored in cache
11 I-stream and D-stream stored in cache
CADR <1> (Write Wrong Parity) is read/write. When set, incorrect parity
is stored in the cache whenever the cache is written.
CADR <0> (Diagnostic mode) is read/write. When set, all write references
write through the cache irrespective of hit/miss or bus error status. In
addition, the BIU assertion of TRAP and STALL are inhibited during a bus
write. When cleared, a normal non-allocating cache write through
operation occurs during write cycles. Diagnostic mode does not effect
read operations.
CVAX CPU CHIP DESIGN SPECIFICATION Page 277
BUS INTERFACE UNIT (BIU)-
Cache diagnostic mode, which is selected when CADR<0> is written as a 1,
has several restrictions.
Cache diagnostic mode was designed to allow the internal cache tag RAM to
be fully tested without requiring the full compliment of VAX physical
memory (512Mbytes). Originally, diagnostic mode was going to force all
write references to write through the cache (write allocate), irrespective
of whether or not the data was previously stored in the cache. In
addition, bus errors (write cycles terminated by asserting ERR L and
deasserting RDY L) were to be ignored (no machine check is generated).
The final implementation of diagnostic mode did implement the spirit of
these goals. However, several restrictions where added on the exact way
they can be used.
1. A validated write allocation will only occur on instructions that have
a quadword write destination (such as MOVQ). Any longword destination
write that accesses a location that is not stored in the cache will
invalidate a cache entry. The second longword write is needed to validate
the cache enty during a write allocation. It is recommended to only use
MOVQ when write allocating the cache.
2. A read operation must occur in between all write allocation
operations. A prefetch read is sufficient although great care must be
taken to insure that one occurs in between write allocates. It is
recommended to read some bit bucket data in between write allocations in
order to guarantee that restriction 2 is met.
3. When the above restrictions are observed, the data that is actually
written into the cache is convoluted. The second longword write will
always overwrite the first longword write. Therefore, the longword in the
cache that is accessed by the first longword write will contain the data
that was written second. Furthermore, the alternate longword will contain
whatever data was in the cache prior to the write allocation. A quadword
aligned MOVQ followed by a MOVQ to the alternate longword can be used to
define both longwords of a cache entry.
6.3.4 Low Memory System Error Register (MSER) -
7 6 5 4 3 2 1 0
+-+-+-+-+-+-+-+-+
|H|D|M|M| | |D|T|
|M|A|C|C|0|0|A|A| : MSER
| |L|D|C| | |T|G|
+-+-+-+-+-+-+-+-+
MSER <7:4,1:0> are read/write and are undefined at power up. MSER<3:2>
are not implemented in the BIU, and therefore will read as 11 on the
W_SPUR.
MSER <7> (hit/miss) is updated only on references that can be potentially
stored in the cache. This excludes all I/O space references; if CADR <5>
CVAX CPU CHIP DESIGN SPECIFICATION Page 278
BUS INTERFACE UNIT (BIU)-
= 0, all memory space instruction stream references; if CADR <4> = 0, all
memory space data stream references; and all read lock references. On all
references that qualify, MSER <7> is set if the reference is stored in the
cache and cleared if it is not stored in the cache.
MSER<6> (DAL parity error) is set whenever a DAL parity error is detected
on either a demand or request read cycle.
MSER <5> (machine check abort - DAL parity error) is set whenever a
machine check is caused by a DAL parity error. A DAL parity error will
only cause a machine check on a demand read cycle.
MSER <4> (machine check abort - cache parity error) is set whenever a
machine check is caused by a cache parity error (tag or data). A cache
parity error will only cause a machine check on a demand read cycle.
MSER<1:0> are independently set to show the scope of a cache parity error
on either a demand or request cycle. MSER<0> is set to indicate that the
cache parity error was caused by a tag error; MSER<1>, by a data error.
MSER <6:4,1:0> are sticky in the sense that once set, they remain set
until MSER is explicity cleared by a wirting MSER (MXPS1 MSER write
irrespective of the data). Parity errors occurring while an error
condition is posted in MSER can only set additional bit, i.e., MSER<6:0>
cannot be cleared on subsequent errors.
Cache parity is checked only on cacheable read references that hit the
cache. The action following the detection of a cache parity error depends
on the reference type: during a demand D-stream reference, the cause of
the error is logged in MSER.LOW<6:0>, the cache is flushed (i.e.,
G_S%FLUSH_H is asserted) CADR<7:0> is cleared, and a microtrap is
generated; request I-stream reference, the cache is flushed, the cause of
the error is logged in MSER.LOW<6:0>, G_S%IB_FILL_ERR_H is asserted, no
microtrap is generated and CADR remains unchanged.
uTrap G_S%IB_FILL_ERR_H G_S%FLUSH_H CADR MSER
----- ----------------- ----------- ---- ----
D-demand yes deasserted asserted cleared error logged
I-request no asserted asserted no change error logged
D-request can not generate cache parity error
6.3.4.1 DAL H Parity -
CVAX protects DAL data with parity. Each eight bit DAL byte is
conditionally checked by a parity bit. Odd data bytes show odd parity;
even data bytes, even parity. The parity sense is alternated in order to
catch both stuck at one and stuck at zero faults. DAL H parity checking
can be disable, reference by reference, by deasserting the external pin
DPE L.
The action following the detection of a DAL H parity error depends on the
reference type: during a demand D-stream reference, the cache entry is
CVAX CPU CHIP DESIGN SPECIFICATION Page 279
BUS INTERFACE UNIT (BIU)-
invalidated if the access is cacheable, the cause of the error is logged
in MSER.LOW<7,3:0>, and a microtrap is generated; request D-stream
references, the cache entry is invalidated if the access is cacheable, the
cause of the error is logged in MSER.LOW<7,3:0>, and no microtrap occurs;
I-stream references, the cache entry is invalidated, the cause of the
error is logged in MSER.LOW<7,3:0>, G_S%IB_FILL_ERR_H is asserted and no
microtrap occurs
uTrap G_S%IB_FILL_ERR_H G_S%FLUSH_H CADR MSER
----- ----------------- ----------- ---- ----
D-demand yes deasserted deasserted no change error logged
I-request no asserted deasserted no change error logged
D-request no deasserted deasserted no change error logged
Note that in all cases, the cache entry that is being allocated
will be invalidated if the reference is cacheable.
6.3.5 MIB Decoder -
The MIB decoder decodes the microinstruction for the BIU.
" MEM REQ Format Macros"
[]<--MEM(VA) "MEMREQ/FORMAT,MEMREQ.FNC/MEM.VIRT.VA,MEMREQ.ACC/RCHK.CURR,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
[]<--MEM(VA).CHECK(AT) "MEMREQ/FORMAT,MEMREQ.FNC/MEM.VIRT.VA,MEMREQ.ACC/AT.CURR,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
[]<--MEM(VA).LOCK "MEMREQ/FORMAT,MEMREQ.FNC/MEM.VIRT.VA.LOCK,MEMREQ.ACC/WCHK.CURR,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
[]<--MEM(VA).IPR "MEMREQ/FORMAT,MEMREQ.FNC/MEM.PHYS.VA.IPR,MEMREQ.ACC/NONE,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
[]<--MEM(VA).PHYS "MEMREQ/FORMAT,MEMREQ.FNC/MEM.PHYS.VA,MEMREQ.ACC/NONE,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
[]<--MEM(VA).WCHECK "MEMREQ/FORMAT,MEMREQ.FNC/MEM.VIRT.VA,MEMREQ.ACC/WCHK.CURR,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
[]<--MEM(VAP) "MEMREQ/FORMAT,MEMREQ.FNC/MEM.VIRT.VAP,MEMREQ.ACC/NONE,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
[]<--MEM(VAP).INTVEC "MEMREQ/FORMAT,MEMREQ.FNC/MEM.PHYS.VAP.INTVEC,MEMREQ.ACC/NONE,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
[]<--MEM(VAP).PPTE "MEMREQ/FORMAT,MEMREQ.FNC/MEM.VIRT.VAP.PTE,MEMREQ.ACC/NONE,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
[]<--MEM(VAP).PHYS "MEMREQ/FORMAT,MEMREQ.FNC/MEM.PHYS.VAP,MEMREQ.ACC/NONE,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
[]<--MEM(VAP).SPTE "MEMREQ/FORMAT,MEMREQ.FNC/MEM.PHYS.VAP.PTE,MEMREQ.ACC/NONE,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
MEM(VA)<--[] "MEMREQ/FORMAT,MEMREQ.FNC/MEM.VIRT.VA,MEMREQ.ACC/WCHK.CURR,A/@1,
MEMREQ.RW/WRITE,DST/DST.ZILCH"
MEM(VA).IPR<--[] "MEMREQ/FORMAT,MEMREQ.FNC/MEM.PHYS.VA.IPR,MEMREQ.ACC/NONE,A/@1,
MEMREQ.RW/WRITE,DST/DST.ZILCH"
MEM(VA).PHYS<--[] "MEMREQ/FORMAT,MEMREQ.FNC/MEM.PHYS.VA,MEMREQ.ACC/NONE,A/@1,
MEMREQ.RW/WRITE,DST/DST.ZILCH"
MEM(VA).UNLOCK<--[] "MEMREQ/FORMAT,MEMREQ.FNC/MEM.VIRT.VA.LOCK,MEMREQ.ACC/WCHK.CURR,A/@1,
CVAX CPU CHIP DESIGN SPECIFICATION Page 280
BUS INTERFACE UNIT (BIU)-
MEMREQ.RW/WRITE,DST/DST.ZILCH"
MEM(VAP)<--[] "MEMREQ/FORMAT,MEMREQ.FNC/MEM.VIRT.VAP,MEMREQ.ACC/NONE,A/@1,
MEMREQ.RW/WRITE,DST/DST.ZILCH"
MEM(VAP).PHYS<--[] "MEMREQ/FORMAT,MEMREQ.FNC/MEM.PHYS.VAP,MEMREQ.ACC/NONE,A/@1,
MEMREQ.RW/WRITE,DST/DST.ZILCH"
[]<--FPA.DATA "MEMREQ/FORMAT,MEMREQ.FNC/FPA.DATA,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
[]<--MXPR[] "MEMREQ/FORMAT,MEMREQ.FNC/MXPR,MEMREQ.PR/@2,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
MXPR[]<--[] "MEMREQ/FORMAT,MEMREQ.FNC/MXPR,MEMREQ.PR/@1,A/@2,
MEMREQ.RW/WRITE,DST/DST.ZILCH"
[]<--MXPS0[] "MEMREQ/FORMAT,MEMREQ.FNC/MXPS0,MEMREQ.REG.RD.0/@2,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
MXPS0[]<--[] "MEMREQ/FORMAT,MEMREQ.FNC/MXPS0,MEMREQ.REG.WR.0/@1,A/@2,
MEMREQ.RW/WRITE,DST/DST.ZILCH"
[]<--MXPS1[] "MEMREQ/FORMAT,MEMREQ.FNC/MXPS1,MEMREQ.REG.RD.1/@2,W/@1,A/@1,
MEMREQ.RW/READ,DST/<MEMORY.DST>"
MXPS1[]<--[] "MEMREQ/FORMAT,MEMREQ.FNC/MXPS1,MEMREQ.REG.WR.1/@1,A/@2,
MEMREQ.RW/WRITE,DST/DST.ZILCH"
6.3.6 CFPA Machine - This controller contains the logic for encoding and
decoding the CFPA data and status lines as described above.
6.4 Descriptions Of BIU Cycles
This section describes the various kinds of memory cycles available.
Functionality of the chip signals and some internal logic is discussed for
each case. The cycle types described are as follows:
1. DMA cycle - DMA has been granted by the assertion of DMG in
response to external assertion of DMR. In this case, the CVAX
gives up ownership of the DAL until DMR is released.
2. DATA READ cycle - A read request has been received by the BIU,
and the DAL is free. Address is sent out, the reference misses
the cache, then CVAX waits for memory system response.
3. DATA WRITE cycle - A write request has been queued up for the
BIU. The write address is sent out, followed by the write data.
CVAX then waits for memory system response before proceeding.
4. CFPA cycles - CFPA cycles send opcode information to the CFPA,
broadcast operands to the CFPA, and return information from the
CFPA.
CVAX CPU CHIP DESIGN SPECIFICATION Page 281
BUS INTERFACE UNIT (BIU)-
5. INSTRUCTION STREAM READ cycle - The I Box has requested I-stream
data for the prefetch queue. This cycle acts like a data read
cycle in most respects.
6. IDLE cycle - No memory activity has been requested.
6.4.1 DMA Cycle - -
During a DMA cycle, CVAX gives up control of the DAL<31:0> H. DAL<31:0>
H, CS/DP<3:0> L, DPE L, CPDAT<5:0> H, and CPSTA<1:0> H are tri-stated; AS
L, DS L, DBE L, WR L, and BM<3:0> L are driven high and tri-stated; RDY L
and ERR L may be driven by the memory system to respond to DMA operations;
RESET L, HALT L, IRQ<3:0> L, CRD L, INTTIM L, PWRFL L, and TEST<0> H are
typically high; DMR L and DMG L are low. The DMA device owning the DAL
may request a cache invalidate cycle by asserting cctl and placing an
address on the DAL. In this case, the DAL is latched into the read data
latch and driven to the IDAL for use as a cache address. The cache does a
read during one cycle, and does an invalidate on the next if the read
operation produced a cache hit. The read address, write address, and
write data latches are unaffected during DMA cycles. If a demand memory
read is posted during a DMA cycle not requiring a cache invalidate
operation, a cache read is done. If the cache read result is a HIT, data
is returned to the W-BUS as described in the section on data read cycles.
If a prefetch request is received from the I Box during a DMA cycle not
requiring a cache invalidate operation, a cache read is done. If there is
a cache miss or the prefetch caching is disabled the machine is not
stalled. If a write request is received during a DMA cycle, the processor
stalls. If a second write request is received, the processor will stall
until the first request can be serviced.
6.4.2 Data Read Cycle - -
During a data read cycle, the IDAL is driven with the desired address
during PHI2 and PHI3. The cache does a read operation based on this
address, and reports a hit or miss late in PHI4. The read address latch
is loaded with the address during PHI2 and PHI3. The cache drives the
result of the read operation to the IDAL during PHI4. If the result is a
MISS and the DAL is free, i.e. no DMA operation is happening and no data
write or read is already in progress, the DAL is driven with the address
latch contents. In the next cycle, AS L is asserted during PHI1 and DS L
is asserted during PHI3, and the machine waits for some combination of RDY
L and ERR L to indicate the end of the cycle. During each cycle in which
CVAX is waiting for memory response, the read data latch is loaded during
PHI4. This data is then broadcast to the W-BUS via the IDAL late during
PHI4 and during PHI1. When RDY L or ERR L is received, DS L and AS L are
deasserted and the cycle ends. If the cache read result is a HIT, AS L in
not asserted, and the cache result is driven to the W-BUS during PHI4 and
PHI1. If any additional non-prefetch memory requests are received during
CVAX CPU CHIP DESIGN SPECIFICATION Page 282
BUS INTERFACE UNIT (BIU)-
a read cycle, the machine stalls until the current request is finished.
6.4.3 Data Write Cycle - -
During a data write cycle, the IDAL is driven with the address during PHI2
and PHI3. This value is latched in the write address latch. The cache
system also uses this address to perform a read operation, reporting a hit
or miss in PHI4, without driving the resultant read data onto the IDAL.
The address is sent onto the DAL during PHI4 and PHI1, and AS L is
asserted. During the next cycle, the IDAL is driven with the write data
during PHI2 and PHI3. If the cache reported a HIT during the previous
cycle, it writes the IDAL value to the address it used for the read. At
the same time, the IDAL data is latched in the write data latch. The data
is driven onto the DAL during PHI4 and PHI1, and DS is asserted. The
machine then waits for some combination of RDY L and ERR L to end the
cycle. If another write request is received during a write cycle, the
machine stalls until the write is completed.
6.4.4 CFPA Cycles - -
6.4.4.1 Passing Opcode Information To The CFPA -
Opcode information must be passed to the CFPA whenever it is going to
execute or accelerate any of the CVAX instructions. Most floating point
and some integer instructions pass opcode information when CFPA activity
is desired (assuming the CFPA is present). In either case, only the six
lower order opcode bits are passed to the CFPA. CVAX drives an
f/d_floating point opcode on CPDAT when CPSTA<1:0> H=10; a g_floating
point opcode when CPSTA<1:0>=11; and an integer opcode when CPSTA<1:0>
H=01. The following opcodes are passed to the CFPA:
Full CPDAT CPSTA
Opcode Instruction (hex) (binary)
------ ----------- ----- --------
C4 MULL2 04 01
C5 MULL3 05 01
C6 DIVL2 06 01
C7 DIVL3 07 01
7A EMUL 3A 01
40 ADDF2 00 10
41 ADDF3 01 10
42 SUBF2 02 10
43 SUBF3 03 10
44 MULF2 04 10
45 MULF3 05 10
46 DIVF2 06 10
47 DIVF3 07 10
CVAX CPU CHIP DESIGN SPECIFICATION Page 283
BUS INTERFACE UNIT (BIU)-
48 CVTFB 08 10
49 CVTFW 09 10
4A CVTFL 0A 10
4B CVTRFL 0B 10
4C CVTBF 0C 10
4D CVTWF 0D 10
4E CVTLF 0E 10
4F ACBF 0F 10
50 MOVF 10 10
51 CMPF 11 10
52 MNEGF 12 10
53 TSTF 13 10
54 EMODF 14 10
55 POLYF 15 10
56 CVTFD 16 10
60 ADDD2 20 10
61 ADDD3 21 10
62 SUBD2 22 10
63 SUBD3 23 10
64 MULD2 24 10
65 MULD3 25 10
66 DIVD2 26 10
67 DIVD3 27 10
68 CVTDB 28 10
69 CVTDW 29 10
6A CVTDL 2A 10
6B CVTRDL 2B 10
6C CVTBD 2C 10
6D CVTWD 2D 10
6E CVTLD 2E 10
6F ACBD 2F 10
70 MOVD 30 10
71 CMPD 31 10
72 MNEGD 32 10
73 TSTD 33 10
74 EMODD 34 10
76 CVTDF 36 10
75 POLYD 35 10
40FD ADDG2 00 11
41FD ADDG3 01 11
42FD SUBG2 02 11
43FD SUBG3 03 11
44FD MULG2 04 11
45FD MULG3 05 11
46FD DIVG2 06 11
47FD DIVG3 07 11
48FD CVTGB 08 11
49FD CVTGW 09 11
50FD MOVG 10 11
4AFD CVTGL 0A 11
4BFD CVTRGL 0B 11
4CFD CVTBG 0C 11
4DFD CVTWG 0D 11
CVAX CPU CHIP DESIGN SPECIFICATION Page 284
BUS INTERFACE UNIT (BIU)-
4EFD CVTLG 0E 11
4FFD ACBG 0F 11
51FD CMPG 11 11
52FD MNEGG 12 11
53FD TSTG 13 11
54FD EMODG 14 11
55FD POLYG 15 11
99FD CVTFG 19 11
33FD CVTGF 33 11
6.4.4.2 Passing Operands To The CFPA -
Operands that are to be passed to the CFPA can come from three sources:
memory, the internal cache, or the general purpose registers. CVAX drives
CPSTA<1:0> H=00 and CPDAT<1> H=1 when a longword of operand data is on
DAL<31:0>; and CPDAT<0> H=1 when a short literal operand is on DAL<5:0>
(DAL<31:6> will be 0). If the source of the operand is either memory or
the internal cache, CPDAT<5:4> are driven with the two low order address
bits of the reference; otherwise the source is the general purpose
registers and CPDAT<5:4> are driven as 00. The CFPA must align all
unaligned data. If the data is coming from memory (AS L is asserted), the
CFPA reads the DALs according to the full memory read protocol (RDY L
and/or ERR L asserted); otherwise, the data is coming from CVAX (internal
cache or the general purpose registers), is driven on the DALs at PHI3 and
is sampled by the CFPA at the next PHI1. If the source of the operand is
either memory or the internal cache and a parity error is detected by
CVAX, the chip aborts the CFPA operation, and never signals the CFPA for
the current result. The CFPA is reset when CVAX sends a new CFPA opcode.
In parallel with each operand transfer, CPDAT<2> H will be asserted if
PSL<6> is set; otherwise, it is deasserted.
In summary, CPDAT<5:0> H are encoded as follows when operands are being
passed to the CFPA:
CPDAT<5:0>
----------
<5:4> Address alignment code
<3> = 0 will always be deasserted
<2> = 0 this bit will be set if
1 PSL<6> is set; otherwise cleared
<1> = 0 no action
= 1 DAL<31:0> is CFPA operand
<0> = 0 no action
= 1 DAL<5:0> is short literal; DAL<31:6> are 0's.
CVAX CPU CHIP DESIGN SPECIFICATION Page 285
BUS INTERFACE UNIT (BIU)-
6.4.4.3 Passing Results Back From The CFPA -
CVAX informs the CFPA when it is ready for a result by deasserting
CPSTA<1:0> H (00), and asserting CPDAT<3> H (1) at a PHI3 edge. CVAX then
gives up ownership of the CPDAT, CPSTA, and DAL by tri-stating these lines
at the next PHI2 edge; the CFPA gains ownership of CPDAT and CPSTA by
driving them at the next PHI3 edge. The DAL remains tri-stated while CVAX
waits for the CFPA result.
While waiting, CVAX can grant DMG L on a PHI4 edge. If no DMG L is
granted, CVAX continuously samples the CFPA CPSTA and CPDAT lines on each
PHI1 edge; if granted, the CPSTA and CPDAT lines are ignored. The CFPA
asserts CPSTA<1:0> H=00 at a PHI3 edge to indicate that the result is not
ready; and CPSTA<1:0> H=11, to indicate that they are ready. Any other
encoding will generate a protocol error. If the CFPA indicates that the
condition codes are ready (PHI3) at the same time that CVAX grants DMG L
(PHI4), the CFPA repeats the response until DMG L is deasserted;
otherwise, the CFPA tri-states the CPDAT and CPSTA lines on the next PHI2
edge. CVAX then regains CPDAT and CPSTA on the next PHI3 edge.
Once CVAX detects that the condition code results are ready, the CPDAT
lines are used to determine the response, and DMG L will not be granted
until the end of the operation. CPDAT<5:0> H are encoded as follow:
CPDAT<5> = 0 the result clears the PSL N bit.
= 1 the result sets the PSL N bit.
CPDAT<4> = 0 the result clears the PSL Z bit.
= 1 the result sets the PSL Z bit.
CPDAT<3> = 0 the result clears the PSL V bit
= 1 the result sets the PSL V bit
(integer overflow/ACB condition met)
CPDAT<2:0> Status Data Transfer Microcode
---------- ------ ------------- ---------
000 protocol error aborted machine check
001 reserved opcode aborted machine check
010 reserved operand aborted reserved operand fault
011 divide by zero aborted arithmetic fault
100 floating point overflow aborted arithmetic fault
101 floating point underflow aborted arithmetic fault
110 reserved - protocol error aborted machine check
111 no error continue machine check if CPSTA<1:0>=10 or
CPSTA<1:0>=01; else normal
The CFPA returns protocol error under the following conditions:
1. CVAX signals ready for result when the CFPA is idle.
2. CVAX signals data on DAL when no data is due.
CVAX CPU CHIP DESIGN SPECIFICATION Page 286
BUS INTERFACE UNIT (BIU)-
3. CVAX signals ready for result when the CFPA expects data on DAL.
If CPDAT<2:0> H indicates protocol error, reserve opcode, reserved operand
trap, divide by zero, floating point overflow, or floating point
underflow, no data is transferred; otherwise, all result data is return
over the DAL on consecutive cycle immediately following the condition code
result. In any case, the CFPA gives up CPDAT and CPSTA ownership by
tri-stating these lines at the next PHI2 edge; CVAX regains ownership on
the next PHI3 edge. Note that the CFPA will never report a floating point
underflow error if PSL<6> is cleared.
In general, A single unaligned longword is transferred for a single
precision result (F), and two unaligned longwords are transferred for a
double precision result (D or G). There are exceptions to this rule:
CMPD and CMPG return only one result (DAL data is ignored); EMOD returns
three results. CVAX aligns the data and performs the final transfer if
the ultimate destination of the CFPA data is memory.
6.4.4.4 POLY Protocol -
POLYF, POLYD and POLYG use standard CPDAT and CPSTA protocols for passing
opcode and data between the CVAX and CFPA. The initialization and main
loop sequences are complex and requires special cooperation between these
chips.
6.4.4.4.1 POLY Initialization Sequence -
1. CVAX sends a POLY opcode (POLYF, POLYD, or POLYG).
2. CVAX sends the argument operand. The POLYF argument operand is
either a longword or short literal; the POLYD and POLYG argument
is either two longwords or a short literal followed by a longword
containing zero.
3. CVAX sends the table address (the CFPA does not use this
information).
4. CVAX reads the argument back from the CFPA. The CFPA has
converted all short literal into longwords. Therefore, one
longword is read for POLYF; two longwords are read for POLYD and
POLYG. Reserved operand checking is done by the CFPA and any
error is reported when the argument is read back.
5. CVAX sends the seed partial product to the CFPA. If the
instruction is first starting, the seed is 0; otherwise, the
instruction is resuming after an interrupt, and the seed is the
last partial product result.
CVAX CPU CHIP DESIGN SPECIFICATION Page 287
BUS INTERFACE UNIT (BIU)-
6.4.4.4.2 POLY Main Loop -
1. CVAX sends over a coefficient. The POLYF coefficient is one
longword; POLYD and POLYG, two longwords.
2. CVAX reads the partial product result. The POLYF result is one
longword; POLYD and POLYG are two longwords. Reserved operand
checking is done by the CFPA and any error is reported when the
result is read.
6.4.4.5 CFPA Present Indication -
The CFPA is an optional coprocessor. The CFPA informs CVAX that it is
present when RESET L is asserted. CVAX actively drives CPDAT<5:0> H and
CPSTA<1> H to L while providing a weak pullup (H) on CPSTA<0> H.
Therefore, if no coprocessor is present, CPSTA<0> H is read as H;
otherwise, the CFPA overdrives CPSTA<0> H so that it reads as L.
6.4.4.6 CFPA Forced Termination -
There are several error conditions that are detected in CVAX which cause
the CFPA to terminate the execution of a floating point or accelerated
integer instruction.
- RESET L is asserted
- CFPA operand generates a reserved addressing mode fault
- CFPA operand generates an address translation fault
- CFPA operand access causes a machine check abort
- CFPA operand access causes a cache or DAL parity error
The CFPA terminates all execution and resets whenever CVAX sends an opcode
on CPDAT<5:0> irrespective of the coprocessor state, and whenever RESET L
is asserted.
6.4.4.7 Sample CFPA Timing -
Symbol Meaning
------ -------
XXX DAL is driven by CVAX but is undefined
=== DAL is driven by CVAX with valid information
MMM DAL is driven by memory
FFF DAL is driven by CFPA
~~~ Signal is driven to a high level
CVAX CPU CHIP DESIGN SPECIFICATION Page 288
BUS INTERFACE UNIT (BIU)-
___ Signal is driven to a low level
>-- Signal is tri-stated
CVAX CPU CHIP DESIGN SPECIFICATION Page 289
BUS INTERFACE UNIT (BIU)-
BIU TIMING DIAGRAM FOR: MULF2 (R1), R2
In this case, the first operand results in a read that hits the cache.
------------------------------------+------------------------------------------------------------------------------------------>
previous macroinstruction | MULF2 (R1), R2 macroinstruction continued >
--------------------+---------------+---------------+---------------+---------------+---------------+---------------+---------->
| | | | | | |
4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3
MIB =============XXXX============XXXX============XXXX============XXXX============XXXX============XXXX============XXXX
....,DECNEXT VA <-- GRN WSN.BR<--MEM(VA) WSN<--GRN.BR ...... ...... ......
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
G_S%_STALL_H XXXXXXXXXXX\______________________________________________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\_________>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
|<------------------------------------------CVAX drives CPDAT/CPSTA--------------------------------------------->
CPDAT/CPSTA H ____________/~~~~~~~~~~~~~~~\_______________________________/~~~~~~~~~~~~~~~X~~~~~~~~~~~~~~~~\__________________>
opcode on CPDAT 1st opnd on DAL 2nd opnd on DAL
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
|<----------------------------------------------CVAX drives DAL------------------------------------------------->
DAL H XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX==============XX===============X===============XXXXXXXXXXXXXXXXXXXXX
address 1st opnd 2nd opnd
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
AS L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
DS L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
RDY L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>
-----------------------------------------------------------------------------------------------------------------------+------------
MULF2 (R1), R2 macroinstruction continued | next macro
--------------------+---------------+------------------+---------------+---------------+---------------+---------------+------------
| | | | | |
MIB =============XXXX===...=========XXXX============XXXX============XXXX============XXXX============XXXX============XXXX
....... GPR<--FPA.DATA GPR<--FPA.DATA GPR<--FPA.DATA GPR<--FPA.DATA ...
4 | 1 2 3 4 ... 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3
G_S%_STALL_H ____________________ _____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\________________________________________
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
<-------CVAX drives CPDAT/CPSTA----------->| |<-CFPA drives CPDAT/CPSTA->| |<-------CVAX drives CPDAT/CPSTA---->
CPDAT/CPSTA H ~~~~~~~~~~~~\_______ ________/~~~~~~~~~~~>---<_______________/~~~~~~~~~~~>---<____________________________________
2nd operand on DAL ready for result CC not ready CC ready
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
<---------CVAX drives DAL----------------->| |<-CFPA drives->| |<--CVAX drives DAL->
DAL H XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX>-------------------------------<FFFFFFFFFFFFFFF>---XXXXXXXXXXXXXXXXXXXXX
CFPA result address data
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
AS L ~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
DS L ~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
RDY L ~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CVAX CPU CHIP DESIGN SPECIFICATION Page 290
BUS INTERFACE UNIT (BIU)-
BIU TIMING DIAGRAM FOR: MULF3 (R1), R2, (R3)
In this case, the first operand results in a read that misses the cache.
------------------------------------+------------------------------------------------------------------------------------------>
previous macroinstruction | MULF2 (R1), R2 macroinstruction continued >
--------------------+---------------+---------------+---------------+---------------+---------------+---------------+---------->
| | | | | | |
4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3
MIB =============XXXX============XXXX============XXXX============XXXX============XXXX============XXXX============XXXX
....,DECNEXT VA <-- GRN WSN.BR<--MEM(VA) WSN<--GRN.BR WSN<--GRN.BR WSN<--GRN.BR ......
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
G_S%_STALL_H XXXXXXXXXXX\______________________________________________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\_____________________>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
|<------------------------------------------CVAX drives CPDAT/CPSTA--------------------------------------------->
CPDAT/CPSTA H ____________/~~~~~~~~~~~~~~~\_______________________________/~~~~~~~~~~~~~~~\_______________________________/~~~>
opcode on CPDAT 1st operand on DAL 2nd
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
|<-----------------CVAX drives DAL--------------------->| |<----memory drives DAL---->| |<-CVAX drives DAL->
DAL H XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX============---MMMMMMMMMMMMMMMMMMMMMMMMMMMMM----XXXXXXXXXXXXXXXX===>
address
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
AS L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\___________________________________/~~~~~~~~~~~~~~~~~~~~~~~>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
DS L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\_______/~~~~~~~\_______/~~~~~~~~~~~~~~~~~~~~~~~~~~~>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
RDY L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\_______/~~~~~~~\_______/~~~~~~~~~~~~~~~~~~~~~~~>
prefered data fill data
-----------------------------------------------------------------------------------------------------------------------+------------
MULF3 (R1), R2, (R3) macroinstruction continued | next macro
--------------------+---------------+------------------+---------------+---------------+---------------+---------------+------------
| | | | | |
4 | 1 2 3 4 ... 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3
MIB =============XXXX===...=========XXXX============XXXX============XXXX============XXXX============XXXX============XXXX
........... W0<--FPA.DATA W0<--FPA.DATA W0<--FPA.DATA W0<--FPA.DATA MEM(VA)<--W0
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
G_S%_STALL_H ____________________ _____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\________________________________________
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
<-------CVAX drives CPDAT/CPSTA----------->| |<-CFPA drives CPDAT/CPSTA->| |<-------CVAX drives CPDAT/CPSTA---->
CPDAT/CPSTA H ~~~~~~~~~~~~\_______ ________/~~~~~~~~~~~>---<_______________/~~~~~~~~~~~>---<____________________________________
2nd operand on DAL ready for result CC not ready CC ready
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
<---------CVAX drives DAL----------------->| |<-CFPA drives->| |<--CVAX drives DAL->
DAL H XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX>-------------------------------<FFFFFFFFFFFFFFF>---==============X======
CFPA result address data
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
AS L ~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\___________
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
DS L ~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\___
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
RDY L ~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CVAX CPU CHIP DESIGN SPECIFICATION Page 291
BUS INTERFACE UNIT (BIU)-
BIU TIMING DIAGRAM FOR: MULD2 (R1), R2
In this case, the first operand results in a read that hits the cache.
------------------------------------+------------------------------------------------------------------------------------------>
previous macroinstruction | MULD2 (R1), R2 macroinstruction continued >
--------------------+---------------+---------------+---------------+---------------+---------------+---------------+---------->
| | | | | | |
4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3
MIB =============XXXX============XXXX============XXXX============XXXX============XXXX============XXXX============XXXX
....,DECNEXT VA <-- GRN WSN.BR<--MEM(VA) WSN.BR<--MEM(VAP) WSN<--GRN.BR WSN<--GRN.BR ....
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
G_S%_STALL_H XXXXXXXXXXX\____________________________________________________________________________________________________>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
|<------------------------------------------CVAX drives CPDAT/CPSTA--------------------------------------------->
CPDAT/CPSTA H ____________/~~~~~~~~~~~~~~~\_______________________________/~~~~~~~~~~~~~~~X~~~~~~~~~~~~~~~X~~~~~~~~~~~~~~~X~~~>
opcode on CPDAT operand on DAL operand on DAL operand on DAL
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
|<---------------------------------------------------CVAX drives DAL-------------------------------------------->
DAL H XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX===========XXXX================X===============X===============X===>
address LSB 1st opnd MSB 1st opnd LSB 2nd opnd
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
AS L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
DS L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
RDY L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~>
-----------------------------------------------------------------------------------------------------------------------+------------
MULD2 (R1), R2 macroinstruction continued | next macro
--------------------+---------------+------------------+---------------+---------------+---------------+---------------+------------
| | | | | |
4 | 1 2 3 4 ... 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3
MIB =============XXXX===...=========XXXX============XXXX============XXXX============XXXX============XXXX============XXXX
........... GPR<--FPA.DATA GPR<--FPA.DATA GPR<--FPA.DATA GPR<--FPA.DATA GPR+1<--FPA.DATA ...
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
G_S%_STALL_H ____________________ _____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\________________________________________
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
<-------CVAX drives CPDAT/CPSTA----------->| |<-CFPA drives CPDAT/CPSTA->| |<-------CVAX drives CPDAT/CPSTA---->
CPDAT/CPSTA H ~~~~~~~~~~~~\_______ ________/~~~~~~~~~~~>---<_______________/~~~~~~~~~~~>---<____________________________________
operand on DAL ready for result CC not ready CC ready
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
<---------CVAX drives DAL----------------->| |<---------CFPA drives--------->|
DAL H =============XXXXXXX XXXXXXXXXXXXXXXXXXXX>-------------------------------<FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF>---XXXXX
MSB 2nd opnd LSB result MSB result
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
AS L ~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
DS L ~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
: | : : : ... : : : | : : : | : : : | : : : | : : : | : : :
RDY L ~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CVAX CPU CHIP DESIGN SPECIFICATION Page 292
BUS INTERFACE UNIT (BIU)-
BIU TIMING DIAGRAM FOR: MULD2 (R1), R2
In this case, the first operand is quadword aligned and results in a read that misses the cache.
------------------------------------+------------------------------------------------------------------------------------------>
previous macroinstruction | MULD2 (R1), R2 macroinstruction continued >
--------------------+---------------+---------------+---------------+---------------+---------------+---------------+---------->
| | | | | | |
4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3
MIB =============XXXX============XXXX============XXXX============XXXX============XXXX============XXXX============XXXX
....,DECNEXT VA <-- GRN WSN.BR<--MEM(VA) WSN.BR<--MEM(VAP) WSN.BR<--MEM(VAP)
WSN.BR<--MEM(VAP) WSN.BR<--MEM(VAP)
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
G_S%_STALL_H XXXXXXXXXXX\______________________________________________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\_______>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
|<------------------------------------------CVAX drives CPDAT/CPSTA--------------------------------------------->
CPDAT/CPSTA H ____________/~~~~~~~~~~~~~~~\_______________________________/~~~~~~~~~~~~~~~\___________________________________>
opcode on CPDAT 1st operand on DAL
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
|<-----------------CVAX drives DAL--------------------->| |<----memory drives DAL---->| |<-CVAX drives DAL->
DAL H XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX============---MMMMMMMMMMMMMMMMMMMMMMMMMMMMM----XXXXXXXXXXXXXXXXXXX>
address LSB 1st opnd fill data
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
AS L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\___________________________________/~~~~~~~~~~~~~~~~~~~~~~~>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
DS L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\_______/~~~~~~~\_______/~~~~~~~~~~~~~~~~~~~~~~~~~~~>
: | : : : | : : : | : : : | : : : | : : : | : : : | : : :
RDY L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\_______/~~~~~~~\_______/~~~~~~~~~~~~~~~~~~~~~~~>
prefered data fill data
--------------------------------------------------- ----------------------------------------------------------------+------------
MULD2 (R1), R2 macroinstruction continued | next macro
--------------------+---------------+-------------- ----------------+---------------+---------------+---------------+------------
| | | | | |
4 | 1 2 3 4 | 1 : 2 : 3 : 4 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3 4 | 1 2 3
MIB =============XXXX============XXXX ... =========XXXX============XXXX============XXXX============XXXX============XXX
WSN<--GPR.BR ... GPR<--FPA.DATA GPR<--FPA.DATA GPR<--FPA.DATA GPR<--FPA.DATA GPR+1<--FPA.DATA
: | : : : | : : : ... : : : | : : : | : : : | : : : | : : :
G_S%_STALL_H ____________________________________ _____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\________________________
: | : : : | : : : ... : : : | : : : | : : : | : : : | : : :
<----------------------CVAX drives CPDAT/CPSTA---------------------------->| |<-CFPA ->| |<----CVAX drives--->
CPDAT/CPSTA H ____________/~~~~~~~~~~~~~~~X~~~~~~~ ________________ ________/~~~~~~~~~~~>---<~~~~~~~~~~~>---<____________________
opnd on DAL Opnd on DAL ready for result CC ready
: | : : : | : : : ... : : : | : : : | : : : | : : : | : : :
<-------------------------CVAX drives DAL--------------------------------->| |<-------CFPA------>|
DAL H XXXXXXXXXXXX================X======= XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX>-------------------<FFFFFFFFFFFFFFFFFFFF
MSB 1st opnd LSB 2nd opnd LSB result MSB
: | : : : | : : : ... : : : | : : : | : : : | : : : | : : :
AS L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
: | : : : | : : : ... : : : | : : : | : : : | : : : | : : :
DS L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
: | : : : | : : : ... : : : | : : : | : : : | : : : | : : :
RDY L ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CVAX CPU CHIP DESIGN SPECIFICATION Page 293
BUS INTERFACE UNIT (BIU)-
6.4.4.8 CFPA Interface Overhead -
Symbol Meaning
------ -------
DOB data on DAL bus
opcode opcode on CPDAT bus
nop null cycle
rr ready for result
cc condition codes ready
cpr CFPA result
lcpr last CFPA result
adr DAL address
cdata cache or register data
data demand D-stream data from memory
fill request D-stream data from memory
cpd CFPA data
hiz DALs tri-state
-- DAL not specified
6.4.4.8.1 Opcode Transfer -
Opcode Transfer
cycle | 1 |
CP lines opcode
DAL --
CVAX CPU CHIP DESIGN SPECIFICATION Page 294
BUS INTERFACE UNIT (BIU)-
6.4.4.8.2 Passing Operands To CFPA -
Single Precision Register Transfer - 1st operand or 2nd & 3rd operand
if not preceeded by memory transfer (cache miss)
cycle | 1 | 2 |
CP lines DOB NOP
DAL cdata
Double Precision Register Transfer - 1st operand or 2nd & 3rd operand
if not preceeded by memory transfer (cache miss)
cycle | 1 | 2 | 3 |
CP lines DOB NOP DOB
DAL cdata cdata
Single Precision Register Transfer - 2nd & 3rd operand if preceeded by memory transfer (cache miss)
cycle | 1 | 2 |
CP lines nop DOB
DAL -- cdata
Double Precision Register Transfer - 2nd & 3rd operand if preceeded by memory transfer (cache miss)
cycle | 1 | 2 | 3 | 4 |
CP lines nop DOB nop DOB
DAL -- cdata -- cdata
Single Precision Memory Transfer - longword aligned, cache hit
cycle | 1 | 2 |
CP lines nop DOB
DAL adr cdata
Single Precision Memory Transfer - longword aligned, cache miss, ideal memory
cycle | 1 | 2 | 3 | 4 | 5 |
CP lines nop DOB nop nop nop
DAL adr -- data fill --
Single Precision Memory Transfer - longword unaligned, does not cross quadword, ideal memory
cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
CP lines nop DOB nop nop nop nop DOB nop
DAL adr -- data fill -- adr cdata --
Single Precision Memory Transfer - longword unaligned, crosses quadword, cache misses,
ideal memory
cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
CP lines nop DOB nop nop nop nop DOB NOP nop nop
DAL adr -- data fill -- adr -- data fill --
Double Precision Memory Transfer - quadword aligned, cache hit
cycle | 1 | 2 | 3 | 4 |
CP lines nop DOB nop DOB
DAL adr cdata -- cdata
Double Precision Memory Transfer - quadword aligned, cache miss, ideal memory
cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
CP lines nop DOB NOP nop nop nop DOB nop
DAL adr -- data fill -- adr cdata --
CVAX CPU CHIP DESIGN SPECIFICATION Page 295
BUS INTERFACE UNIT (BIU)-
Double Precision Memory Transfer - quadword unaligned, longword aligned,
1st longword cache miss, 2nd longword cache hit, ideal memory
cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
CP lines nop DOB nop nop nop nop DOB nop
DAL adr -- data fill -- adr cdata --
Double Precision Memory Transfer - quadword unaligned, longword aligned,
1st & 2nd longword cache miss, ideal memory
cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
CP lines nop DOB nop nop nop nop DOB nop nop nop
DAL adr -- data fill -- adr -- data fill --
Double Precision Memory Transfer - longword unaligned (worst case)
cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
CP lines nop DOB nop nop nop nop DOB nop nop nop
DAL adr -- data fill -- adr -- data fill --
cycle | 11 | 12 | 13 | 14 |
CP lines nop DOB nop DOB
DAL adr cdata adr cdata
6.4.4.8.3 Passing Results Back From CFPA -
Single Precision Transfers - CFPA ready with results
cycle | 1 | 2 | 3 |
CP lines rr cc lcpr
DAL adr hiz cpd
Doule Precision Transfers - CFPA ready with two results
cycle | 1 | 2 | 3 | 4 |
CP lines rr cc cpr lcpr
DAL adr hiz cpd cpd
Doule Precision Transfers - CFPA ready with three results
cycle | 1 | 2 | 3 | 4 | 5 |
CP lines rr cc cpr cpr lcpr
DAL adr hiz cpd cpd cpd
6.4.5 Instruction Stream Read Cycle -
An instruction stream read cycle acts much the same as a data read cycle.
One difference is that CVAX will not stall if an I-stream read request is
received while another DAL operation is taking place. Another difference
is that memory or parity errors during prefetches do not cause microtraps.
In the case of an error during a prefetch operation, the request is
terminated and GS%IBFILLERRH is asserted.
CVAX CPU CHIP DESIGN SPECIFICATION Page 296
BUS INTERFACE UNIT (BIU)-
6.4.6 IDLE Cycle - -
During an idle cycle, the DAL will be driven with the contents of the read
address latch at phi4 in anticipation of a read miss from the cache. If
DMR L is asserted, DMG L will be asserted in the next cycle. Cycle status
and bye mask lines are still driven, but are of no value since AS L is not
asserted.
6.4.7 Output Pin Status On RESET L -
Pin Name State
-------- -----
DAL<31:0> H tri-state
CS/DP<3:0> L tri-state
BM<3:0> L tri-state
DPE L deasserted
AS L deasserted
DS L deasserted
DBE L deasserted
WR L deasserted
DMG L deasserted
CPDAT H deasserted
CPSTA<0> H weakly asserted
CPSTA<1> H deasserted
6.4.8 Table Of Interesting Pad Values And Chip Functions During Memory
Cycles -
SIGNAL NAME DMA CYCLE DATA READ DATA WRITE CFPA READ CFPA WRITE IDLE CYCLE
------------------------+---------------+---------------+---------------+---------------+---------------+---------------+
P_S%DAL_H | TRI | ADDRESS/TRI | ADDRESS/DATA | TRI | ADDR OR DATA | OLD ADDRESS |
P_S%DPE_L | TRI | HIGH/TRI | HIGH/LOW | HIGH | HIGH | HIGH |
P_S%AS_L | HIGH AND TRI | LOW | LOW | HIGH | HIGH | HIGH |
P_S%DS_L | HIGH AND TRI | HIGH/LOW | HIGH/LOW | HIGH | HIGH | HIGH |
P_S%BM_L | TRI | MASK | MASK | DON'T CARE | DON"T CARE | DON'T CARE |
P_S%WRITE_L | HIGH AND TRI | HIGH | LOW | HIGH | HIGH | HIGH |
P_S%DBE_L | HIGH AND TRI | LOW | LOW | HIGH | HIGH | HIGH |
P_S%RDY_L | HIGH/LOW | GOES LOW PHI4 | GOES LOW PHI4 | HIGH | HIGH | HIGH |
P_S%ERR_L | HIGH/LOW | GOES LOW PHI4 | GOES LOW PHI4 | HIGH | HIGH | HIGH |
P_S%DMR_L | LOW | MAY GO LOW | MAY GO LOW | MAY GO LOW | MAY GO LOW | MAY GO LOW |
P_S%DMG_L | LOW | HIGH | HIGH | HIGH | HIGH | HIGH |
P_S%CS/DP<3:0> | TRI | CS CODE | CS CODE/PARITY| DON'T CARE | DON'T CARE | ASSERT |
P_S%CCTL_L | LOW FOR INVAL | HIGH FOR CACHE| HIGH | HIGH | HIGH | HIGH |
P_S%CP_DAT_L | HIGH/LOW | ASSERT FOR BRD| HIGH/LOW | TRI | ASSERT | LOW |
P_S%CP_STA_L | HIGH/LOW | ASSERT FOR BRD| HIGH/LOW | TRI | ASSERT | LOW |
------------------------+---------------+---------------+---------------+---------------+---------------+---------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 297
BUS INTERFACE UNIT (BIU)-
6.5 IDAL State Machine Definition
The following is the POP description of the IDAL state machine. Refer to
the BIU and global signal dictionarys for information about each of the
input and output signals.
_.i 28
_.o 18
_.p 52
_.table
field name side position
inputs
BLOCK_BRDCST < 0> x x
CP_OK < 0> x x
ARM_IB_REQ < 0> x x
AS_ASSERTED < 0> x x
DENY_CACHE < 0> x x
DMA_INV_REQ < 0> x x
BASIC_BRDCST < 0> x x
DMA_OR_WR_PND < 0> x x
READ_MISS < 0> x x
MISS < 0> x x
RDY < 0> x x
ERR < 0> x x
DMA_REQ < 0> x x
DAL_PAR_ERR < 0> x x
CACHE_PAR_ERR < 0> x x
BRDCST < 0> x x
IB_REQ < 0> x x
READ < 0> x x
WRITE < 0> x x
CACHEABLE < 0> x x
FPA_PND < 0> x x
CP_ERR < 0> x x
CP_RDY < 0> x x
FPA_READ < 0> x x
PREV_IB_REQ < 0> x x
CURRENT_STATE < 2> x x
CURRENT_STATE < 1> x x
CURRENT_STATE < 0> x x
outputs
CLR_PREV_IB_REQ < 0> x x
SIGNAL_FPA < 0> x x
INHIB_DMA < 0> x x
ARM_RD_REQ < 0> x x
MBOX_STALL < 0> x x
LD_WDAT_LAT < 0> x x
ARM_AS < 0> x x
STALL < 0> x x
IB_FILL_ERR < 0> x x
BIU_TRAP_REQ < 0> x x
INIT_IB_REQ < 0> x x
CACHE_ADDR < 1> x x
CACHE_ADDR < 0> x x
CVAX CPU CHIP DESIGN SPECIFICATION Page 298
BUS INTERFACE UNIT (BIU)-
CACHE_FCN < 1> x x
CACHE_FCN < 0> x x
NEXT_STATE < 2> x x
NEXT_STATE < 1> x x
NEXT_STATE < 0> x x
_.endtable
_.d 0XXXX00X0XXXXX00000XXXX0X000 000010000000000000
_.d XXXXX1XXXXXXXX0XXXXXXXXXX000 000010000001101001
_.d XXXXXXXXX0XXXXXXXXXXXXXXX001 000010000001111000
_.d XXXXXXXXX1XXXXXXXXXXXXXXX001 000010000000000000
_.d 0XXXXX100XXXXX0XXXXXXXXXX000 001000000000000010
_.d XXXXXXXXXXXXXXXXXXXXXXXXX010 000011000000000000
_.d XXXXX0110XXXXX0XXXXXXXXXX000 000010000000000000
_.d 0XXXXXX00XXXXX0XXX1XXXXXX000 000000000000101011
_.d XXXXXXXXX0XXXXXXXXXXXXXXX011 000011000001010000
_.d XXXXXXXXX1XXXXXXXXXXXXXXX011 000011000000000000
_.d XXXXX0X10XXXXX0XXX1XXXXXX000 000010000000000000
_.d 0XXXXX000XXXXX00100XXXX0X000 000000100010100000
_.d 0XXXX0010XXXXX00100XXXX0X000 000100000010100000
_.d XXXXXXXXXXXXXX1XXXXXXXXX1000 100010001000000000
_.d XXX1XXXX1XXXXX0XXXXXXXXXX000 001010000000000100
_.d XX10XXX01XXXXX0XXXXXXXXXX000 000010000000000100
_.d XX1XX0X11XXXXX0XXXXXXXXXX000 000010000000000000
_.d 0XXXXXX00XXXXX0XX1XXXXXXX000 000000100000100000
_.d 1XXXXXXXXXXXXX0XXXXXXXXXX000 000010000000000000
_.d 0XXXX0X10XXXXX00X1XXXXXXX000 000100000000100000
_.d XXXXXXXXXXXXXX1XXXXXXXXX0000 000010010100000000
_.d XXX0X0X11XXXXX0XXXXXXXXX0000 000010010000000000
_.d XXX0XXX01XXXXX0XXXXXXXXX0000 000010010000000100
_.d XXXXX0X10XXXXX01XXXXXXXXX000 000010000000000000
_.d XXXXXXXXXX00XXXXXXXXXXXXX100 001010000000000100
_.d XXXXXXXXXX10X0XXXXX0XXXXX100 000010000000000000
_.d XXXXXXXXXX10X1XXXXX0XXXX0100 000010010100000000
_.d XXXXXXXXXX10X1XXXXX0XXXX1100 000010000000000000
_.d XXXX0XXXXX10X0XXXXX1XXXXX100 000010000001010110
_.d XXXX1XXXXX10X0XXXXX1XXXXX100 000010000000000000
_.d XXXX0XXXXX10X1XXXXX1XXXX0100 000010010100000110
_.d XXXX1XXXXX10X1XXXXX1XXXX0100 000010010100000000
_.d XXXX0XXXXX10X1XXXXX1XXXX1100 000010000000000110
_.d XXXX1XXXXX10X1XXXXX1XXXX1100 000010000000000000
_.d XXXXXXXXXX11XXXXXXXXXXXXX100 000010000000000000
_.d XXXXXXXXXX01XXXXXXXXXXXXX100 000010000000000101
_.d XXXXXXXXXX1XXXXXXXXXXXXXX101 000010000000000000
_.d XXXXXXXXXX0XXXXXXXXXXXXX0101 000010010100000000
_.d XXXXXXXXXX0XXXXXXXXXXXXX1101 000010001000000000
_.d XXXXXXXXXX00XXXXXXXXXXXXX110 000010000000000110
_.d XXXXXXXXXX10X0XXXXXXXXXXX110 000010000001010000
_.d XXXXXXXXXX10X1XXXXXXXXXXX110 000010000000000000
_.d XXXXXXXXXXX1XXXXXXXXXXXXX110 000010000000000000
_.d 0XXXXXX00XXXXX0XXXXX0XX1X000 010010000000000000
_.d XXXXX0X10XXXXX0XXXXX0XX1X000 000010000000000000
_.d X0XXXXXXXXXX0XXXXXXX100XX000 000010000000000000
CVAX CPU CHIP DESIGN SPECIFICATION Page 299
BUS INTERFACE UNIT (BIU)-
_.d X0XXX0XXXXXX1XXXXXXX100XX000 000010000000000000
_.d X1XXXXXXXXXX1XXXXXXX1XXXX000 001000000000000000
_.d XXXXXXXXXXXX1XXXXXXX11XXX000 001010010000000000
_.d XXXXXXXXXXXX0XXXXXXX11XXX000 000010010000000000
_.d X1XXXXXXXXXX0XXXXXXX1XXXX000 000000000000000000
_.d XXXXXXXXXXXXXXXXXXXX1X1XX000 001000000000000000
_.end
6.6 DAL State Machine Definition
The following is the POP description of the DAL state machine. Refer to
the BIU and global signal dictionarys for information about each of the
input and output signals.
_.i 16
_.o 14
__.p 35
_.table
field name side position
inputs
INHIB_DMA < 0> x x
DENY_CACHE < 0> x x
RDY < 0> x x
ERR < 0> x x
DMA_REQ < 0> x x
BRDCST_REQ < 0> x x
RD_FPA_REQ < 0> x x
FPA_SEZ_RDY < 0> x x
WR_REQ < 0> x x
RD_REQ < 0> x x
CACHE_ACC < 0> x x
ARM_RD_REQ < 0> x x
CURRENT_STATE < 3> x x
CURRENT_STATE < 2> x x
CURRENT_STATE < 1> x x
CURRENT_STATE < 0> x x
outputs
BLOCK_DPE < 0> x x
DIS_DMG < 0> x x
DATA_IN < 0> x x
DAL_CONT < 1> x x
DAL_CONT < 0> x x
AS_EN < 0> x x
DS_EN < 0> x x
DMG_EN < 0> x x
LD_RD_LAT < 0> x x
CLR_READ_FLAGS < 0> x x
NEXT_STATE < 3> x x
NEXT_STATE < 2> x x
NEXT_STATE < 1> x x
NEXT_STATE < 0> x x
_.endtable
CVAX CPU CHIP DESIGN SPECIFICATION Page 300
BUS INTERFACE UNIT (BIU)-
_.d XXXX000X00XX0000 00000000000000
_.d XXXXX1XXXXXX0000 10001000000000
_.d 0XXX10XXXXXX0000 00100001000001
_.d XXXX1XXXXXXX0001 00100000000001
_.d XXXX0XXXXXXX0001 01000000000000
_.d XXXXXX11XXXX0000 00100000100000
_.d XXXX0X10XXXX0000 00100000000000
_.d XXXX0XXX1XXX0000 00010100000010
_.d XXXXXXXXXXXX0010 00001010000011
_.d XX00XXXXXXXX0011 00001000000011
_.d XX10XXXX0XXX0011 00000000000000
_.d XX10XXXX1XXX0011 00010100000010
_.d XX11XXXXXXXX0011 00000000000000
_.d XX01XXXXXXXX0011 00001000000100
_.d XXXXXXXXXXXX0100 00000000000000
_.d XXXXXXXXX1000000 00100010101001
_.d XXXXXXXXX1100000 00100010100110
_.d 0XXX0XXX01X10000 00000100000101
_.d 1XXXXXXX01X10000 00000100000101
_.d XXXXXXXXXX0X0101 00100010101001
_.d XXXXXXXXXX1X0101 00100010100110
_.d XX00XXXXXXXX0110 00100000100110
_.d X010XXXXXXXX0110 00100000101000
_.d X110XXXXXXXX0110 00000000010000
_.d XX11XXXXXXXX0110 00000000000000
_.d XX01XXXXXXXX0110 00100000000111
_.d XXXXXXXXXXXX0111 00000000000000
_.d XX00XXXXXXXX1000 00100000101000
_.d XXX1XXXXXXXX1000 00000000010000
_.d XX10XXXXXXXX1000 00000000010000
_.d XX00XXXXXXXX1001 00100000101001
_.d XX11XXXXXXXX1001 00000000000000
_.d XX10XXXXXXXX1001 00000000010000
_.d XX01XXXXXXXX1001 00100000001010
_.d XXXXXXXXXXXX1010 00000000000000
_.end
6.7 Stall And Trap Behavior Of The BIU - A Summary
6.7.1 Mbox_stall - What It Means And When It's Used -
Mbox_stall indicates that the IDAL is being used by some other source and
is not available for M Box use. If the M Box receives a microinstruction
requiring the IDAL while Mbox_stall is asserted, the M Box will assert
STALL until Mbox_stall goes away. Mbox_stall is asserted by the BIU
whenever a read operation is pending, or the current microinstruction
implies no memory reference.
CVAX CPU CHIP DESIGN SPECIFICATION Page 301
BUS INTERFACE UNIT (BIU)-
6.7.2 Stall -
Stall is asserted by the BIU only when a read operation is in progress and
the demand read data has not been returned yet. This keeps the chip from
proceeding without the required data. NOTE: Mbox_stall is asserted
whenever Stall is asserted.
6.7.3 BIU Trap Request -
A BIU trap request is signaled if a cache parity error is detected during
a cacheable demand read cycle; a DAL parity error is detected during
demand read cycle; or a demand read, write, interrupt vector read, or EPR
read cycle is terminated with the assertion of ERR L.
6.7.4 BIU Trap Vectors -
BIU drives utest bus<3:1> during PHI1 if the trap line was asserted by BIU
in phi2 of the previous micro-cycle.
1.
Microinstruction R/W Trap Vector NAME Adr UTEST<3:1>
---------------- --- ----------------- --- ---------
MEM.VIRT.VA R IE.BUSERR.READ.VIRT 130 000
MEM.VIRT.LOCK R IE.BUSERR.READ.VIRT 130 000
MEM.VIRT.VAP R IE.BUSERR.READ.VIRT 130 000
MEM.VIRT.VAP.PTE R IE.BUSERR.READ.VIRT 130 000
MEM.PHYS.VA R IE.BUSERR.READ.PHYS 132 001
MEM.PHYS.VAP R IE.BUSERR.READ.PHYS 132 001
MEM.PHYS.VAP.PTE R IE.BUSERR.READ.PHYS 132 001
MEM.PHYS.VA.IPR R IE.BUSERR.READ.IPR 134 010
MEM.PHYS.VAP.INTVEC R IE.BUSERR.READ.VEC 136 011
MEM.VIRT.VA W IE.BUSERR.WRITE.VIRT 138 100
MEM.VIRT.LOCK W IE.BUSERR.WRITE.VIRT 138 100
MEM.VIRT.VAP W IE.BUSERR.WRITE.VIRT 138 100
MEM.VIRT.VAP.PTE W IE.BUSERR.WRITE.VIRT 138 100
MEM.PHYS.VA W IE.BUSERR.WRITE.PHYS 13A 101
MEM.PHYS.VAP W IE.BUSERR.WRITE.PHYS 13A 101
MEM.PHYS.VAP.PTE W IE.BUSERR.WRITE.PHYS 13A 101
6.7.5 CFPA Trap Request -
A CFPA trap request is signaled whenever the CFPA returns a protocol
CVAX CPU CHIP DESIGN SPECIFICATION Page 302
BUS INTERFACE UNIT (BIU)-
error, reserved opcode error, divide by zero error, overflow error, or
underflow error with a result; if a CFPA CPSTA code of 110 is detected; or
if a CFPA CPDAT code of 10 or 01 is detected.
6.7.6 CFPA Exception Trap Vectors -
BIU drives utest bus<3:1> during PHI1 if a CFPA trap request is generated.
Condition CPDAT<2:0> Trap Vector NAME Adr UTEST<3:1>
---------------- ---------- ---------------- --- ---------
protocol error 000 FP.PROT.ERROR 140 000
reserved instruction 001 FP.RSRV.INST 142 001
reserved operand 010 FP.RSRV.OPER 144 010
divide by zero 011 FP.DIVIDE.BY.ZERO 146 011
underflow 101 FP.UNDERFLOW 148 100
overflow 100 FP.OVERFLOW 14A 101
illegal CPDAT code 110 FP.UNKNOWN.6 14C 110
illegal CPSTA code 111 FP.UNKNOWN.7 14E 111
CVAX CPU CHIP DESIGN SPECIFICATION Page 303
BUS INTERFACE UNIT (BIU)-
6.8 BIU Internal Signal Timing
The diagram below lists all the internal BIU signals that cross schematic
boundaries.
CVAX CPU CHIP DESIGN SPECIFICATION Page 304
BUS INTERFACE UNIT (BIU)-
6.9 BIU Internal Signal Timing
The diagram below lists all the internal BIU signals that cross schematic
boundaries.
+----------+---------+---------+----------+
BIU INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------^
| | | | | | |
| B_S%arm_as_lat_h |==========xxxx=========================| |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/10/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+12 BAS,BDI,BPC phi1-5 None BAS = 74 ff (phi1) |
| Ct = 1.6 pf BDI = 80 ff (phi1) |
| BPC = 42 ff (phi1-5) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%arm_ib_req_lat_h |==========xxxx=========================| |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/10/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+12 BIC BEG phi4 None BIC = 28 ff |
| Ct = 0.675 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%arm_rd_req_lat_h |==========xxxx=========================| |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/10/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+12 BCO,BDI BEG phi3 None BCO = 62 ff (phi3) |
| Ct = 1.3 pf BPC = 42 ff (phi1-5) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%as_latch_h | | | | | |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/10/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BAS 6ns after valid BCO Used asynchronously None BCO = 110 ff |
| externally Ct = 0.74 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | Note: Used by RDY_L and ERR_L pin to |
| B_S%as_lat_h | | | | | prevent from sampling during |
CVAX CPU CHIP DESIGN SPECIFICATION Page 305
BUS INTERFACE UNIT (BIU)-
| | | | | | non-io cycles. |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/10/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BAS 6ns after valid BER,BRY phi4-5 None BER = 48 ff |
| externally Ct = 1.1 pf BRY = 48 ff |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | Note: This siganl is directly driven by |
| B_S%b0_parity_h | | | | | data driven onto idal |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/10/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPT idal+11 BPD phi3+10 OR 690 ff BPD = 160 ff |
| Ct = 1.1 pf phi4+15 BPT = 260 ff
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%b0_par_err_l |===xxxxxx|xxxxxxxxx|xxxxxxxxx|xxxxxxx==| |
| | | | | | |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/10/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPT phi4+20 BPE phi4+20 BPE = 146 ff |
| Ct = 1.03 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | Note: This siganl is directly driven by |
| B_S%b1_parity_h | | | | | data driven onto idal |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/10/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPT idal+11 BPD phi3+10 OR 690 ff BPD = 160 ff |
| Ct = 1.05 pf phi4+15 BPT = 260 ff
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%b1_par_err_l |===xxxxxx|xxxxxxxxx|xxxxxxxxx|xxxxxxx==| |
| | | | | | |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPT phi4+20 BPE phi4+20 BPE = 146 ff |
| Ct = 1.0 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | Note: This siganl is directly driven by |
| B_S%b2_parity_h | | | | | data driven onto idal |
| | | | | | |
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 306
BUS INTERFACE UNIT (BIU)-
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPT idal+11 BPD phi3+10 OR 690 ff BPD = 160 ff |
| Ct = 1.07 pf phi4+15 BPT = 260 ff
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%b2_par_err_l |===xxxxxx|xxxxxxxxx|xxxxxxxxx|xxxxxxx==| |
| | | | | | |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPT phi4+20 BPE phi4+20 BPE = 146 ff |
| Ct = 0.95 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | Note: This siganl is directly driven by |
| B_S%b3_parity_h | | | | | data driven onto idal |
| | | | | | |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPT idal+11 BPD phi3+10 OR 690 ff BPD = 160 ff |
| Ct = 0.87 pf phi4+15 BPT = 260 ff
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%b3_par_err_l |===xxxxxx|xxxxxxxxx|xxxxxxxxx|xxxxxxx==| |
| | | | | | |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPT phi4+20 BPE phi4+20 BPE = 146 ff |
| Ct = 0.89 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%block_dpe_l |xxxxxxxxx|xxxxxxxxxxx==================| |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPP phi3+4 BDP phi3+7 None BDP = 110 ff |
| Ct = 0.83 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%brdcst_cp_lat_h |xxxxxxxxx|xxx=========xxxxxxx|xxxxxxxxx| |
| | | | | | |
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 307
BUS INTERFACE UNIT (BIU)-
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi2+11 BCD phi2+15 None BCD = 216 ff |
| Ct = 3.2 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%buf_dmg_en_lat_h |=========|=========|=xxxxx============== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi3+14 BCT phi4-3 None BCT = 44 ff |
| Ct = 1.95 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%cacheable_h |====================xxx================= Note: clock skew between 3 & 4 can affect it|
| | | | | | 3 gate delay margin. |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi3+10 BDI,BIC, phi4-5 None BDI = 88 ff (phi1) |
| BMR,BPE BIC = 98 ff (phi4-5) |
| BMR = 72 ff (phi1) |
| Ct = 2.6 pf BPE = 36 ff (phi4) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%cacheable_ref_h |====================xxx================= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+10 BGB Beg. phi3 None BGB = 126 ff |
| Ct = 1.16 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%cache_par_err_h |x=============================xxxxxxxxxx |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCR phi4+29 BCR,BMB,BMR Beg. phi1 None BCR = 92 ff (phi1) |
| Ct = 0.79 pf BMB = 36 ff (phi2) |
| BMR = 64 ff (phi2) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%cache_rd_h |==========xxxxxx======================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
CVAX CPU CHIP DESIGN SPECIFICATION Page 308
BUS INTERFACE UNIT (BIU)-
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi2+19 BPT Beg. phi4 None BPT = 66 ff |
| Ct = 0.97 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%clear_rd_flags_h |====================xxxx================ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCF phi3+12 BDC,BDI, phi3+15 None BDC = 32 ( during phi3) |
| BIC,BMA BDI = 80 ( " " ) |
| BIC = 46 ( " " ) |
| Ct = 1.53 pf BMA = 40 ( " " ) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%clr_cpdat_h |====================xxxxxx============== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi3+18 BCT Beg. phi2 None BCT = 36 ff |
| Ct = 1.85 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%clr_cp_latches_h |xxxxxxxxxxxx=========xxxxxxxxxxxxxxxxxxx |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCT phi2+8 BCD phi2+15 None BCD = 288 ff |
| Ct = 1.32 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%clr_mser_h |xxxx==================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi1+15 BMR Beg. phi3 None BMA = 150 ff |
| Ct = 0.64 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%clr_write_flags_h |==========xxxxxx======================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
CVAX CPU CHIP DESIGN SPECIFICATION Page 309
BUS INTERFACE UNIT (BIU)-
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCF phi2+15 BIC,BMA Beg. phi3 None BIC = 76 ff (phi3) |
| Ct = 0.93 pf BMA = 42 ff (phi4) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%cp_data_h<5:0> |===xxxxxxxxxxxxxxxxxxxxxxxxxxxxx======== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCD phi4+5 BCT phi4+5 150 ff BCT = 150 ff |
| Ct = 0.825 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%cp_stat_h<1:0> |===xxxxxxxxxxxxxxxxxxxxxxxxxxxxx======== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCD phi4+5 BCT phi4+5 150 ff BCT = 150 ff |
| Ct = 0.83 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dal_in_vec<3:0> |xxx===================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDO phi1+10 BDI,BPP phi2-4 None BDI = 60 ff (phi2) |
| Ct = 0.82 pf BPP = 192 ff (phi2-4) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dal_out_vec<3:0> |xxxxxxxxxxxxxxxxxxx===================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPP Beg. phi3 BDO phi3+3 175 ff BDO = 374 ff |
| Ct = 0.86 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dal_par_err_h |====================xxxxxxxxxxxxxxxxxxxx |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCG phi4+29 BMR Beg. of phi2 None BMR = 64 ff |
| Ct = 0.45 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 310
BUS INTERFACE UNIT (BIU)-
| B_S%decoded_mib_h<2:0> |==========xxxxx===============xxxxxxxxxx |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCG phi2+15 BCC phi2+17 275 No |
| Ct = 1.0 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%deny_cache_h |==============================xxxxxxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDI phi4+19 BIP,BPP phi1-1 None BIP = 214 ff (phi1-1) |
| Ct = 1.0 pf BPP = 192 ff (phi2-4) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dgn_mode_h |==========xxxxx========================= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCR phi2+15 BIC phi4-3 None BIC = 48 ff |
| Ct = 1.0 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dis_dmg_l |xxxxxxxxxxxxxxxxxxxxx==========xxxxxxxxx |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPC phi3+4.5 BDG phi3+4.5 None BDG = 100 ff |
| Ct = 0.67 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dis_ds_l |x=========xxxxxxxxxxx==========xxxxxxxxx |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPC phi1 OR phi3+7 BDS phi3+10 None BDS = 130 ff |
| Ct = 1.2 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dis_strobes_l |xxxxxxxxxxxx==========xxxxxxxxxxxxxxxxxx For MEM REQ cycle |
| | | | | | |
| |xxxxxxxxxxxxxxxxxxxxxx=========xxxxxxxxx For DMA cycle |
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 311
BUS INTERFACE UNIT (BIU)-
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPC phi2 OR phi3+6 BAS,BDB, phi2+7.5 OR None BAS = 100 ff |
| BWR phi3+7.5 BDB = 100 ff |
| Ct = 1.85 pf BWR = 100 ff |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dma_req_h |==============================xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDI phi4+12 BIP,BPP phi1-1 None BIP = 214 ff (phi1-1) |
| Ct = 0.94 pf BPP = 192 ff (phi2-4) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dmg_en_lat_h |====================xxxx================ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDO phi3+10 BCA,BCB,BER,BIC phi3+10 None BCA = 36 ff (phi4) |
| BCO,BIE,BRY BCB = 42 ff (phi3+10) |
| BER+BRY = 72 ff (phi4) |
| Ct = 3.15 pf BIC = 28 ff (phi4-4) |
| BCO = 88 ff (phi3+10) |
| BIE = 60 ff (phi4) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dmg_en_l |====================xxxxxxxx============ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi3+23 BPB phi3+30 None BPB = 304 ff |
| Ct = 0.77 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dpe_lat_l |===xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx======= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDP phi4+10 BPE phi4+12 None BPE = 66 ff |
| Ct = 0.25 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dr_cp_lines_l |====================xxx================= Note: drives trnasistors |
CVAX CPU CHIP DESIGN SPECIFICATION Page 312
BUS INTERFACE UNIT (BIU)-
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCT phi3+8 BCD phi3+6 None BCD = 1.86 pf |
| Ct = 6.0 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dr_dma_addr_l |==========xxx========xxxxxx============= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi2+8 B_IO phi2+10 None B_IO = 1.85 pf |
| Ct = 10.5 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dr_radr_lat_h |====================xxx===========xxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi3+7 BCC,BPB,B_IO phi3+7 None BCC,BPB = 608 ff (phi3+7) |
| Ct = 11.0 pf B_IO = 2.432 pf (phi3+7) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dr_wadr_lat_h |====================xxx===========xxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi3+7 BCC,BPB,B_IO phi3+7 None BCC,BPB = 608 ff (phi3+7) |
| Ct = 10.8 pf B_IO = 2.432 pf (phi3+7) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%dr_wdat_lat_h |====================xxx===========xxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi3+7 BCC,BPB,B_IO phi3+7 None BCC,BPB = 608 ff (phi3+7) |
| Ct = 10.5 pf B_IO = 2.432 pf (phi3+7) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_arm_rd_req_h |xxxxx=================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
CVAX CPU CHIP DESIGN SPECIFICATION Page 313
BUS INTERFACE UNIT (BIU)-
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDI phi1+15 BPP phi2-4 None BPP = 192 ff |
| Ct = 0.45 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_as_en_h |xxxxx===========xxxx==================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPP Beg. phi3 BDO During phi3 150 ff No |
| Ct = 0.43 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_as_en_lat_h |==============================xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDO phi4+11 BAS,BPC phi1-5 None BAS = 74 ff (phi1) |
| Ct = 1.33 pf BPC = 42 ff (phi-5) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_block_dpe_h |xxxxxx==========xxxx==================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPP Beg. phi3 BCO Beg. phi3 None BCO = 104 ff |
| Ct = 1.35 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_brdcst_req_h |xxxx==========================xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi1+10 BPP phi2-4 None BPP = 192 ff |
| Ct = 1.0 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_cache_acc_h |xxxxx===============xxxxxxxx============ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDI phi1+15 BPP phi2-4 None BPP = 192 ff |
| Ct = 0.52 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 314
BUS INTERFACE UNIT (BIU)-
| | | | | | |
| B_S%ds_clr_read_flags_h |xxxxxx==========xxx===================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPP Beg. phi3 BCF Beg. phi3 None BCF = 90 ff |
| Ct = 0.57 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_dal_cont_h<1:0> |xxxxxx==========xxx===================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPP Beg. phi3 BCO Beg. phi3 None BCO = 350 ff |
| Ct = 1.7 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_data_in_h |xxxxxx==========xxx===================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPP Beg. phi3 BCO Beg. phi3 None BCO = 288 ff |
| Ct = 1.7 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_dis_dmg_h |xxxxxx==========xxx===================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPP Beg. phi3 BDO,BPC Beg. phi3 None BDO = 50 ff (phi3) |
| Ct = 0.8 pf BPC = 140 ff(phi3) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_dma_state_h |=xxxx===============xxxx================ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDO phi3+12 BIC phi4-4 None BIC = 40 ff |
| Ct = 0.75 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_dmg_en_h |xxxxxx==========xxx===================== Note: Drives a transistor |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
CVAX CPU CHIP DESIGN SPECIFICATION Page 315
BUS INTERFACE UNIT (BIU)-
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPP Beg. phi3 BDO,BPC Beg. phi3 None BDO = 20 ff (phi3) |
| Ct = 0.79 pf BPC = 140 ff (phi3) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_dr_wadr_h |====================xx========xxx======= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi3+4 BPC phi3+4 None BPC = 108 ff |
| Ct = 1.0 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_dr_wadr_lat_h |====================xxxxxxxx============ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi3+18 BDO,BIC Beg. phi4 None BDO = 60 ff (phi4) |
| Ct = 0.16 pf BIC = 50 ff (phi4) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_ds_en_h |xxxxxx==========xxx===================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPP Beg. phi3 BPC Beg. phi3 None BPC = 76 ff |
| Ct = 0.3 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_err_h |===================xxxxx========xxxxxxx| |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIE phi4+21 BPP Beg. phi2 None BPP = 194 ff |
| Ct = 0.55 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_fpa_sez_rdy_h |xxx===================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi1+10 BPP phi2-4 None BPP = 192 ff |
CVAX CPU CHIP DESIGN SPECIFICATION Page 316
BUS INTERFACE UNIT (BIU)-
| Ct = 0.7 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_inhib_dma_h |======xxx======================xxxxxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BPP phi2-4 None BPP = 192 ff |
| Ct = 0.8 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_ld_rd_lat_h |xxxxxx==========xxx===================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPP Beg. phi3 BDO Beg. phi3 None BDO = 200 ff |
| Ct = 0.42 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_ld_rd_lat_l |==xxxxxx===========xx=================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDO phi3+4 BCO phi3+4 None BCO = 540 ff |
| Ct = 1.7 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_next_retry_wait_h |=xxx================xxxx================ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDO phi3+12 BIE phi4-6 None BIE = 60 ff |
| Ct = 0.48 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_pulse_h |====================xxxxxx=========xxxx= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIE Beg. phi1 BPC Beg. phi1 None BPC = 125 ff |
| Ct = 0.77 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_rd_fpa_req_h |xxxx================xxxx================ |
CVAX CPU CHIP DESIGN SPECIFICATION Page 317
BUS INTERFACE UNIT (BIU)-
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi3+10 BPP phi2-4 None BPP = 192 ff |
| Ct = 0.73 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_rd_mul_retry_h |xxxxx===========================xxxxx=== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDI phi1+15 BCF Beg. phi2 None BCF = 100 ff |
| Ct = 0.44 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_rd_mul_w_h |xxx=================xxx================= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDO phi3+10 BIE phi4-5 125 ff No |
| Ct = 0.48 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_rd_req_h |xxxxx=================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDI phi1+15 BPP phi2-4 None BPP = 192 ff |
| Ct = 0.43 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_rd_retry_h |=xxxxx================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDI phi1+15 BCF Beg. phi2 None BCF = 100 ff |
| Ct = 0.4 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_retry_wait_h |=xxxxx================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
CVAX CPU CHIP DESIGN SPECIFICATION Page 318
BUS INTERFACE UNIT (BIU)-
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDI phi1+15 BCF,BTC Beg. phi2 300 ff BCF = 96 ff (phi2) |
| Ct = 0.67 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_wr_req_h |xxxxx===============xxxxx=====xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDI phi1+15 BPP phi2-4 None BPP = 192 ff |
| Ct = 0.72 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ds_wr_wait_h |xxxxx=================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDO phi1+15 BIC,BMA phi4 150 ff BIC = 144 ff (phi1) |
| Ct = 1.25 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%d_cache_en_h |==========xxxxx========================= Note: This signal changes in phi2 only |
| | | | | | when CADR is written |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCR phi2+15 BOC Beg. phi2 None BOC = 64 ff |
| Ct = 0.77 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%en_bm_h |==============================xx======== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi4+8 BPB phi4+9 None BPB = 600 ff |
| Ct = 2.7 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%en_dal_h |==========xxxxx=====xxx================= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi3+9 BCC,BDP,B_IO phi3+9 None BCC+BDP = 0.75 pf |
| Ct = 14.3 pf B_IO = 4.8 pf
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 319
BUS INTERFACE UNIT (BIU)-
| | | | | | |
| B_S%en_dbe_l |xxxxxx================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPC ph1+15 BDB Beg. phi2 No BDP = 68 ff |
| Ct = 1.15 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%en_dmg_h |====================xxx========xxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPC phi3+7 BDG phi3+7 None BDG = 80 ff |
| Ct = 0.72 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%en_ds_h |====================xxx========xxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPC phi3+7 BDS phi3+7 None BDS = 90 ff |
| Ct = 0.85 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%en_wr_h |====================xx========xxx======= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPC phi3+7 BWR phi3+7 None BWR = 80 ff |
| Ct = 1.4 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%err_h |====================xxxxx======xxxxx==== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/11/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BER phi4+15 BDC,BIC,BIE,BIP PHI4+15 None BDC = 72 ff (phi1) |
| BMA,BPE,BSL BIC = 82 ff (phi4+15) |
| BIE = 74 ff (phi4+15) |
| Ct = 4.6 pf BIP = 214 ff(phi1-1) |
| BMA = 36 ff (phi1) |
| BPE = 96 ff (phi4+15) |
| BSL = 32 ff (phi1) |
CVAX CPU CHIP DESIGN SPECIFICATION Page 320
BUS INTERFACE UNIT (BIU)-
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ext_parity_h<3:0> |==xxxxx=======================xxxx====== |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCC phi4+10 BPT phi4+11 None BPT = 104 ff |
| Ct = 0.89 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%fp_underflow_h |==========xxxx========================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCT phi2+15 BCD phi2+15 (next cy) None BCD = 66 ff |
| Ct = 0.63 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%fpa_read_h |====================xxxxxxxxxxxxx======== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi4+15 BIP phi1-1 None BIP = 214 ff |
| Ct = 1.18 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%idal_in_vec<3:0> |==============================xxx======= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+7 BIP phi1-1 None BIP = 214 ff |
| Ct = 1.45 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%idal_l<29> |==========xxxxxxxxx===========xxx======= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPT phi2+22 BGB,BOC Beg. phi3 None BGB = 126 ff (phi3) |
| Ct = 1.7 pf BOC = 28 ff (phi3) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%idal_out_vec<3:0> |======xxx=====================xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
CVAX CPU CHIP DESIGN SPECIFICATION Page 321
BUS INTERFACE UNIT (BIU)-
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BOC Beg. phi3 250 ff BOC = 236 ff |
| Ct = 0.9 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%idal_out_vec_lat_h |==============================xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi4+7 BIC phi1-1 250 ff No |
| Ct = 0.65 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%init_ib_req_lat_h |==========xxxx========================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+10 BIC phi4-5 None BIC = 34 ff |
| Ct = 1.11 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%invert_bit_3_l |xxxxxx========================xxx======= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi4+9 B_IO phi1-6 None B_IO = 84 ff |
| Ct = 2.35 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%io_end_h |x====================xxxxxx============x |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIE phi1+3 BPC phi1+3 None BPC = 256 ff |
| Ct = 0.92 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_arb1_h |==============================xxxxxx==== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+14 BCO,BST Beg. phi1 None BCO = 36 ff (phi1) |
CVAX CPU CHIP DESIGN SPECIFICATION Page 322
BUS INTERFACE UNIT (BIU)-
| Ct = 1.1 pf BST = 32 ff (phi1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_arm_as_h |=====xxxx=====================xxxxxx==== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BOC Beg. phi2 None BOC = 236 ff |
| Ct = 0.675 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_arm_ib_req_h |==============================xxxxxxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+23 BIP phi1-1 None BIP = 214 ff |
| Ct = 0.825 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_arm_rd_req_h |=========HHHHHHHHHH~~XXXXXXXXXXXX======| |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BOC Beg. phi2 None BOC = 116 ff |
| Ct = 0.56 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_as_asserted_h |==============================xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi4+10 BIP,BST phi1-1 None BIP = 214 ff (phi-1) |
| Ct = 1.1 pf BST = 32 ff (phi1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_basic_brdcst_h |====================xxxxx=====xxxxxxx=== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi4+17 BCB,BIP phi1-1 None BCB = 44 ff (phi1) |
| Ct = 1.6 pf BIP = 214 ff (phi1-1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_biu_trap_req_h |=====xxxx=====================xxxxxx==== Note: Goes to a transistor |
CVAX CPU CHIP DESIGN SPECIFICATION Page 323
BUS INTERFACE UNIT (BIU)-
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BMR,BTC Beg. phi2 300 ff BMR = 64 ff |
| Ct = 1.55 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_block_brdcst_h |==============================xxxxxxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+23 BIP,BIC phi1-1 None BIP = 214 ff (phi1-1) |
| Ct = 0.8 pf BIC = 68 ff (phi1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_brdcst_h |====================xxxx======xxxxxx==== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi4+17 BCB,BOC,BIP phi1-1 None BCB = 44 ff (phi1) |
| Ct = 1.6 pf BOC = 54 ff (phi2) |
| BIP = 214 ff (phi1-1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_brdcst_state_h |==========xxxxx========================= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+15 BCB Beg. phi4 None BCB = 64 ff |
| Ct = 0.95 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_cacheable_h |==============================xxxxxxxxx= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+23 BIP phi1-1 None BIP = 214 ff |
| Ct = 0.87 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_cache_addr_h<1:0> |=====xxxx=====================xxxxxx==== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
CVAX CPU CHIP DESIGN SPECIFICATION Page 324
BUS INTERFACE UNIT (BIU)-
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BOC Beg. phi2 None BOC = 176 ff |
| Ct = 0.68 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_cache_fcn_h<1:0> |=====xxxx=====================xxxxxx==== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BOC Beg. phi2 None BOC = 230 ff |
| Ct = 0.5 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_cache_par_err_h |x=============================xxxxxxxxxx |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPE phi4+27 BCF,BDC, phi1-1 None |
| BIC,BIP,BMA, BCF = 36 ff (phi2) |
| BMR BDC = 16 ff (phi1) |
| Ct = 2.5 pf BIC = 96 ff (phi1+5) |
| BIP = 214 ff(phi1-1) |
| BMA = 36 ff (phi2) |
| BMR = 32 ff (phi2) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_cache_rd_h |==========xxxxxx======================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+15 BCO,BIC,BMA Beg. phi3 None BCO = 42 ff (phi4) |
| Ct = 1.4 pf BIC = 38 ff (phi3) |
| BMA = 288ff (phi3) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_cache_r_nd_l |==========xxxx========================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+12 BIC phi4-4 None BIC = 48 ff |
| Ct = 1.28 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_clr_prev_ib_req_h |=====xxxx=====================xxxxxx==== |
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 325
BUS INTERFACE UNIT (BIU)-
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BCF Beg. phi2 250 ff No |
| Ct = 0.82 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_cp_err_h |==============================xxxxxxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCT phi4+20 BCB,BIP,BTC phi1-1 None BCB = 36 ff (phi1) |
| Ct = 3.9 pf BIP = 214ff (phi1-1) |
| BTC = 104ff (phi2) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_cp_ok_h |==============================xxxxxxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCT phi4+20 BCB,BIP phi1-1 None BCB = 28 ff (phi1) |
| Ct = 3.9 pf BIP = 214ff (phi1-1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_cp_rdy_h |==========xxxxxx======================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi2+15 BCB,BIP Beg. of phi4 None BCB = 28 ff (phi4) |
| Ct = 1.5 pf BIP = 214ff (phi1-1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_dal_par_err_h |x=============================xxxxxxxxxx Note: Goes to a transistor (BDC) |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPE phi4+27 BDC,BIC,BIP phi1-1 None BDC = 56 ff (phi1) |
| BIC = 96 ff (phi1+5) |
| Ct = 2.1 pf BIP = 214ff (phi1-1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_dma_inv_req_h |==============================xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
CVAX CPU CHIP DESIGN SPECIFICATION Page 326
BUS INTERFACE UNIT (BIU)-
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+13 BCO,BIP,BST phi1-1 None BCO = 36 ff (phi1) |
| Ct = 1.3 pf BIP = 214ff (phi1-1) |
| BST = 48 ff (phi1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_dma_or_wr_pnd_h |==============================xxxxxxxxx= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+23 BIP phi1-1 None BIP = 214 ff |
| Ct = 0.89 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_fpa_pnd_h |==========xxxx=================xxxxxx=== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi2+12 BIP phi1-1 None BIP = 214 ff |
| Ct = 0.86 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_fpa_read_h |====================xxxxx=====xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi4+12 BCB phi4+12 None BCB = 52 ff (phi4+12) |
| Ct = 0.68 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_ib_fill_err_h |=====xxxx=====================xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BOC Beg. phi2 None BOC = 54 ff |
| Ct = 0.97 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_init_ib_req_h |=====xxxx=====================xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BCG,BOC Beg. phi2 None BCG = 72 ff (phi2) |
CVAX CPU CHIP DESIGN SPECIFICATION Page 327
BUS INTERFACE UNIT (BIU)-
| Ct = 1.07 pf BOC = 54 ff (phi2) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_invalidate_h |==============================xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+14 BST Beg. phi1 None BST = 48 ff |
| Ct = 0.68 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_inv_rd_h |==========xxxx========================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi2+10 BCO Beg. phi4 None BCO = 150 ff |
| Ct = 0.36 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_ipr_h |xxxx==================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi1+12 BMA Beg. phi3 None BMA = 36 ff |
| Ct = 0.4 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_ld_radr_lat_h |=====xxxx=====================xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+5 BGB,BCO phi2+5 None BGB = 112 ff (phi3) |
| Ct = 1.63 pf BCO = 266 ff (phi2+5) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_ld_wadr_lat_h |=====xxxx=====================xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+5 BCO,BGB,BIC, phi2+5 None BGB = 72 ff (phi3) |
| BMA BCO = 200ff (phi2+5) |
| Ct = 1.96 pf BIC = 42 ff (phi2) |
| BMA = 36 ff (phi3) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 328
BUS INTERFACE UNIT (BIU)-
| | | | | | |
| B_S%is_ld_wdat_lat_h |=====xxxx=====================xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BCO Beg. phi2 None BCO = 288 ff |
| Ct = 1.2 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_ld_wdat_lat_phi4 |=====xxxx=====================xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+5 BCO phi2+10 None BCO = 50 ff |
| Ct = 0.72 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_mbox_stall_h |=====xxxx=====================xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BOC Beg. phi2 None BOC = 104 ff |
| Ct = 0.58 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_miss_h |==============================xxxxxxxxx= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+23 BIP phi1-1 None BIP = 214 ff |
| Ct = 0.56 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_mmgt_err_h |=xxxx===============xxxx================ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPC phi3+6 BDO,BIC,BPE phi4-5 None BDO = 60 ff (phi4) |
| Ct = 2.3 pf BIC = 152ff (phi4-5) |
| BPE = 48 ff (phi4) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_next_invalidate_h |==========xxxxxx======================== |
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 329
BUS INTERFACE UNIT (BIU)-
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+19 BCA Beg. phi3 None BCA = 80 ff |
| Ct = 1.37 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_next_resolve_h |==========xxxxx========================= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+15 BIE Beg. phi3 None BIE = 60 ff |
| Ct = 0.5 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_prev_ib_req_h |==============================xxxxxxx=== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+18 BCF,BCG,BCR, phi1-1 None BCF = 40 ff (phi2) |
| BDC,BIP,BST BCG = 90 ff (phi2) |
| Ct = 2.5 pf BCR = 36 ff (phi1-1) |
| BDC = 154ff (phi1) |
| BIP = 214ff (phi1-1) |
| BST = 88 ff (phi1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_rd_miss_2_h |==============================xxxxx===== |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 04/16/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+6 BCG,BCO,BIE phi2+6 100 ff BCG = 136 ff (phi2+6) |
| Ct = 1.2 pf BCO = 110 ff (phi2) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_rd_miss_h |==============================xxxxx===== |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 04/16/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+14 BDC,BST Beg. phi1 None BDC = 116 ff (phi1) |
| Ct = 1.03 pf BST = 36 ff (phi1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_read_h |====================xxxxx=====xxxxxx==== |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 04/16/86 |
| |
CVAX CPU CHIP DESIGN SPECIFICATION Page 330
BUS INTERFACE UNIT (BIU)-
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi4+17 BOC,BIP phi1-1 None BOC = 64 ff (phi2) |
| Ct = 1.33 pf BIP = 214ff (phi1-1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_read_iak_h |xxxx==================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi1+12 BMA Beg. phi3 None BMA = 36 ff |
| Ct = 0.48 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_read_miss_h |==============================xxxxxxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+20 BCB,BDC,BDI phi1-1 None |
| BIC,BIP,BMR,BPC BCB = 42 ff (phi1) |
| BST BDC = 122ff (phi1) |
| BDI = 240ff (phi1) |
| Ct = 4.25 pf BIC = 68 ff (phi+5) |
| BIP = 214ff (phi1-1) |
| BMR = 32 ff (phi1) |
| BPC = 42 ff (phi1) |
| BSL = 36 ff (phi1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_resolve_h |==============================xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+14 BST Beg. phi1 None BST = 36 ff |
| Ct = 0.71 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_signal_fpa_h |=====xxxx=====================xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BCB,BOC Beg. phi2 None BCB = 70 ff (phi2) |
| Ct = 1.4 pf BOC = 80 ff (phi2) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_stall_h |=====xxxx=====================xxxx====== |
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 331
BUS INTERFACE UNIT (BIU)-
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP Beg. phi2 BST Beg. phi2 None BST = 56 ff |
| Ct = 0.96 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%is_write_h |====================xxxxx=====xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi4+17 BIC,BIP phi1-1 None BIC = 90 ff (phi1-1) |
| Ct = 1.3 pf BIP = 214ff (phi1-1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%i_cache_en_h |==========xxxxxx======================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCR phi2+15 BOC Beg. phi2 None BOC = 68 ff |
| Ct = 0.82 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%lat_cpdata_h<2:0> |==============================xxxxxxxxxx |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCT phi4+25 BTC Beg. phi2 None BTC = 42 ff |
| Ct = 2.5 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ld_dma_addr_h | | | | | Asynchronous ignal |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO 12ns after internal B_IO 14ns after internal None BCC = 1.95 pf |
| value of AS_l pin value of AS_l pin |
| is valid Ct = 9.4 pf is valid |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ld_opcode_h |==========xxx========xxxx=============== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
CVAX CPU CHIP DESIGN SPECIFICATION Page 332
BUS INTERFACE UNIT (BIU)-
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCT phi2+10 BCD phi2+15 None BCD = 448 ff |
| Ct = 1.55 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ld_radr_lat_h |==========xxxx======xxxx================ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi2+12 BCC, B_IO phi2+15 None BCC = 304 ff |
| Ct = 9.9 pf B_IO= 1.92 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ld_rbm_lat_h |====================xxxx======xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi3+13.5 BPB phi3+15 None BPB = 240 ff |
| Ct = 2.2 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ld_rd_lat_h |=xxxx===============xxxxxx============== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi3+17 BCC,BDP,B_IO phi4+20 None BCC+BDP+B_IO = 1.628 pf (phi4) |
| BPD,BPE,BPT BPD = 64 ff (phi4) |
| Ct = 20.6 pf BPE = 36 ff (phi4) |
| BPT = 64 ff (phi4) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ld_wadr_lat_h |==========xxxx======xxxx================ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi2+12 BCC,B_IO phi2+15 None BCC+B_IO = 2.16 pf |
| Ct = 9.0 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ld_wbm_lat_h |====================xxxxx=====xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi3+13.5 BPB phi3+15 None BPB = 240 ff |
CVAX CPU CHIP DESIGN SPECIFICATION Page 333
BUS INTERFACE UNIT (BIU)-
| Ct = 2.1 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ld_wdat_lat_h |==========xxxx======xxxx================ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi2+12 B_IO phi2+15 None B_IO = 1.92 pf |
| Ct = 9.85 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ld_wpar_lat_h |====================xxx=======xxx======= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi3+7 BCC,BPD phi3+8 None BCC = 240 ff (phi3+10) |
| Ct = 2.5 pf BPD = 124 ff (phi3+8) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%mib_lat_virt_h |xxx===================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi1+10 BMA Beg. phi3 None BMA = 114 ff |
| Ct = 0.49 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%modify_bit_31_h |==========xxxx======xxxx================ |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+12 BCO phi2+12 None BCO = 480 ff |
| Ct = 0.87 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%modify_bit_31_l |==========xxxxx=====xxxxx=============== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi2+16 B_IO phi2+16 None B_IO = 138 ff |
| Ct = 6.0 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%modify_byte_0_h |==============================xxxxxxxx== |
CVAX CPU CHIP DESIGN SPECIFICATION Page 334
BUS INTERFACE UNIT (BIU)-
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 4/16/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPB phi4+21 BCC,B_IO Following phi4 None BCC+B_IO = 1.08 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%modify_byte_1_h |==============================xxxxxxxx== |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 04/16/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPB phi4+21 BCC,B_IO Following phi4 None BCC+B_IO = 1.08 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%modify_byte_2_h |==============================xxxxxxxx== |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 04/16/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPB phi4+21 BCC,B_IO Following phi4 None BCC+B_IO = 1.08 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%modify_byte_3_h |==============================xxxxxxxx== |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: 04/16/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPB phi4+21 BCC,B_IO Following phi4 None BCC+B_IO = 1.08 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%opcode_loaded_h |==========xxxxxx====xxxxxx============== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi2+16 BCT phi3-5 None BCT = 42 ff |
| Ct = 1.87 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%p4s2_cctl_h |==========xxxxxxxxxxxxxxxxxxxx========== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCA Beg. phi4 BIC Beg phi4 None BIC = 28 ff |
| Ct = 1.27 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%p4s2_dmr_h |==========xxxxxxxxxxxxxxxxxxx=========== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
CVAX CPU CHIP DESIGN SPECIFICATION Page 335
BUS INTERFACE UNIT (BIU)-
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BDM Beg. phi4 BDI,BIC Beg phi4 150 ff BIC = 40 ff |
| Ct = 1.4 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%rdy_h |====================xxxxx=====xxxxxx==== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BRY phi4+15 BCF,BIC,BIE,BIP phi2+15 135 ff BCF = 36 ff (phi2) |
| BDC,BMA,BPE,BPP (BTC) BIC = 116ff (phi4+15) |
| BST,BTC BIE = 160ff (phi4+15) |
| BDC = 120ff (phi1-3) |
| Ct = 4.76 pf BIP+BPP = 406 ff (phi1-1) |
| BMA = 44 ff (phi1) |
| BPE = 110ff (phi4+15) |
| BST = 72 ff (phi1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%rd_bas_brdcst_h |xxxxxx==============xxxxxx============== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi1+15 BCT Beg. phi2 None BCT = 96 ff |
| Ct = 2.2 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%rd_brdcst_h |xxxx======xxxx========================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BOC phi2+12 BCB,BCD,BIC phi2+15 None BCB = 44 ff (phi3-3) |
| Ct = 1.6 pf BCD = 28 ff (phi2+15) |
| BIC = 42 ff (phi4) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%rd_miss_2_h |==========xxx=======xxx================= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCO phi2+8 BCC,B_IO phi2+15 None BCC = 204 ff (phi2+15) |
| Ct = 1.0 pf B_IO = 56 ff (phi2+17) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 336
BUS INTERFACE UNIT (BIU)-
| B_S%rd_wr_ipr_l |xxxx==================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi1+14 BCG,BOC Beg. phi2 None BCG = 148 ff (phi2) |
| Ct = 1.23 pf BOC = 64 ff (phi2) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%rd_wr_lock_l |xxxx==================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi1+14 BCG,BOC Beg. phi2 None BCG = 64 ff (phi2) |
| Ct = 1.0 pf BOC = 64 ff (phi2) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%ready_h |====================xxxxx=====xxxxxxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+19 BDC,BMA,BST phi1 None BDC = 120 ff (phi1) |
| Ct = 0.94 pf BMA = 44 ff (phi1) |
| BST = 72 ff (phi1) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%read_cadr_h |xxx===================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi1+10 BCR Beg. phi3 None BCR = 90 ff |
| Ct = 0.77 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%read_hit_h |==============================xxxxxxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIC phi4+20 BCB,BCF,BDC Beg. phi1 None BCB = 34 ff (phi1) |
| BMA BCF = 40 ff (phi2-5) |
| Ct = 2.0 pf BDC = 40 ff (phi1) |
| BMA = 36 ff (phi2) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%read_iak_lat_h |====================xxxx======xxxx====== |
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 337
BUS INTERFACE UNIT (BIU)-
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMA phi3+10 BTC Beg. phi2 None BTC = 100 ff |
| Ct = 0.59 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%read_iak_l |xxxxx=================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi1+14 BCG,BOC Beg. phi2 None BCG = 64 ff (phi2) |
| Ct = 1.1 pf BOC = 64 ff (phi2) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%read_ipr_lat_h |====================xxxx======xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMA phi3+10 BTC Beg. phi2 None BTC = 100 ff |
| Ct = 0.67 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%read_miss_h |==============================xxxxxxxx== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BIP phi4+23 BAS phi1+3 None BAS = 100 ff |
Ct = 0.78 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%read_mser_h |xxxxxx================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi1+15 BMR Beg. phi3 None BMA = 170 ff |
| Ct = 0.73 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%read_physical_lat_h |====================xxxx======xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
CVAX CPU CHIP DESIGN SPECIFICATION Page 338
BUS INTERFACE UNIT (BIU)-
| BMA phi3+10 BTC Beg. phi2 None BTC = 100 ff |
| Ct = 0.44 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%read_virtual_lat_h |====================xxxx======xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMA phi3+10 BTC Beg. phi2 None BTC = 100 ff |
| Ct = 0.49 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%short_literal_h |====================xxxxx=====xxxxx===== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi4+14 BCB Beg. phi2 None BCB = 36 ff |
| Ct = 0.75 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%sht_lit_h |==============================xxxxxx==== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi4+16 BCD phi2+5 None BCD = 168 ff |
| Ct = 2.31 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%signal_fpa_h |==========xxxxx=====xxxxx=============== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi2+12 BCD,BCT phi2+15 None BCT = 42 ff (phi2+15) |
| Ct = 2.6 pf BCD = 104ff (phi2+20) |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%s_cctl_lat_h |====================xxxxx=====xxxxxx==== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCA phi4+15 BDI,BIE phi4+15 150 ff BIE = 204 ff |
| Ct = 2.0 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 339
BUS INTERFACE UNIT (BIU)-
| B_S%tri_state_pin_l |====================xxx================= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BPC phi3+8 BAS,BDB,BDS,BWR phi3+8 None BAS+BDB+BDS+BWR = 1.66 pf |
| Ct = 4.25 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%write_cadr_h |xxxx==================================== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMB phi1+10 BMA Beg. phi3 None BCR = 100 ff |
| Ct = 0.29 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%write_cadr_lat_h |====================xxxx======xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMA phi3+14 BCR Beg. phi1 None BCR = 100 ff |
| Ct = 0.8 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%write_physical_lat_h |====================xxxx======xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMA phi3+10 BTC Beg. phi2 None BTC = 100 ff |
| Ct = 0.42 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%write_virtual_lat_h |====================xxxx======xxxx====== |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BMA phi3+10 BTC Beg. phi2 None BTC = 100 ff |
| Ct = 0.42 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| B_S%w_bus_brdcst_h |xxxxxx==============xxxxxxx============= |
| | | | | | |
| | | | | | Last Updated: 4/16/86 |
| Spice Ref (Block/Text): Last Updated: 9/15/86 |
CVAX CPU CHIP DESIGN SPECIFICATION Page 340
BUS INTERFACE UNIT (BIU)-
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| BCB phi1+16 BCD phi2+20 None BCD = 64 ff |
| Ct = 2.7 pf |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 341
MICROSEQUENCER
7 MICROSEQUENCER
The Microsequencer produces the address of the next ROM location to be
read from the control store. There are six possible sources of this
address. The address could be:
o An address specified solely by the microinstruction
o An address partially specified by the microinstruction and
partially from the previous microaddress
o The top of the microstack
o A microtrap routine address
o An address specified by the I Box
o An externally generated test address
This description of the Microsequencer is divided into two parts: an
overview describing the busses, major components, and gross timing, and a
functional description at the microcode level.
A block diagram of the microsequencer is included at the end of this
section.
7.1 Busses
7.1.1 Microaddress Bus (MAB) <10:0> -
The Microaddress Bus is the Microsequencer's major output bus. It drives
the Control Store's row and column decoders with the address of the next
microinstruction to be accessed.
MAB <10:0> are valid during PHI2, PHI3, PHI4, and change during PHI1.
7.1.2 I Box Microaddress Bus (IMAB) <10:0> -
The I Box Microaddress Bus is driven by the I Box with microaddresses for
entry points into microcode flows. IMAB lines feed the MAB Mux.
IMAB<10:0> are valid before PHI2, during PHI2, PHI3, and PHI4 and change
during PHI1.
CVAX CPU CHIP DESIGN SPECIFICATION Page 342
MICROSEQUENCER
7.1.3 Microtest Bus (UTEST) <2:0> -
Microtest is a global control bus for the Microsequencer.
The Microsequencer precharges Microtest during PHI3. Sources to Microtest
discharge it in PHI1. The Microsequencer latches the value on UTEST<2:0>
during PHI1 and holds this value during PHI2 and PHI3. The UTEST bus is
active low. Values on the UTEST may determine the final values on MAB
<3:1>.
7.1.4 Microinstruction Bus (MIB) <40:0> -
The Microinstruction Bus is the major output bus of the Control Store.
The lower 13 bits of the 41 bit microinstruction are used for
Microsequencer control. MIB<6:0> are driven single rail since these bits
route to the Microsequencer only. MIB<40:7> are driven dual rail. Both
true and complement versions of the MIB are valid minimum 1ns setup time
before PHI4.
MIB<40:0> are valid 1 ns before PHI4, during PHI4, PHI1, and PHI2 and
change during PHI3.
7.1.5 Current Microaddress Bus (CMAB) <10:0> -
The MAB is latched during PHI3 (as long as STALL is not asserted) to
create the Current Microaddress Bus. Bits <10:0> of the CMAB connect to
the uStack Input Mux and the Current Microaddress Incrementer. CMAB<10:7>
also feed back to the MAB Mux.
CMAB<10:0> are valid during PHI4, PHI1, PHI2, and change during PHI3.
7.1.6 Incremented Current Microaddress Bus (ICMAB) <10:0> -
The ICMAB is the output of the Current Microaddress Incrementer and latch.
ICMAB<10:0> are valid during PHI3, PHI4, PHI1, and changes during PHI2.
7.1.7 Microstack Input Bus (USIB) <10:0> -
The Microstack Input Bus is driven by the Microstack Input Mux with data
from the Current Microaddress Bus (CMAB) or the Incremented Current
Microaddress Bus (ICMAB) as determined by the Microstack Input Mux
control.
USIB<10:0> are valid by the end of PHI4, during PHI1 and PHI2, and changes
during PHI3.
CVAX CPU CHIP DESIGN SPECIFICATION Page 343
MICROSEQUENCER
7.1.8 Microstack Data Bus (USDB) <10:0> -
The Microstack Data Bus is the internal bus of the Microstack register
file. During USTACK_WRITE operations USDB<10:0> is driven by the
Microstack Write Buffer (USWB). USTACK_WRITE operations enable the USWB
during PHI4. At all other times USDB<10:0> is driven with the top of the
Microstack during PHI4. The USDB is precharged during PHI3.
7.1.9 Microstack Output Bus (USOB) <10:0> -
The Microstack Output Bus is driven with the top of the Microstack during
USTACK_READ operations and with write data during USTACK_WRITE operations.
The USOB connects to the Microaddress Bus Mux (MAB Mux).
USOB<10:0> are valid for USTACK_READ or USTACK_WRITE operations during
PHI4, PHI1, and PHI2.
7.1.10 Test_MAB Bus (TEST_MAB) <10:0> -
The Test_MAB Bus supplies externally generated addresses to the MAB Mux.
Redefined I/O pins are driven externally with addresses of locations in
the Control Store to be accessed when the CVAX TEST pins are configured
for this mode of operation.
External logic generating these addresses must insure that TEST_MAB<10:0>
data is valid during PHI1 and PHI2.
7.1.11 Microtrap Address Bus (UTRAB) <6:4> -
The Microtrap Address Bus supplies base addresses to the MAB Mux when a
microtrap is taken.
Microtrap address bits <10:7,3:0> are hardwired in the MAB MUX. Microtrap
Addresses are valid during PHI1 and PHI2.
7.2 Microsequencer Sections
7.2.1 Microstack (USTACK) [0:7] -
The Microstack is a true circular LIFO stack of eight entries used for
storing return microaddresses. The contents of the top entry is always
presented to the MAB Mux.
A "push" consists of a pre-decrement of the USTACK entry pointer during
PHI3 followed by a USTACK_WRITE during PHI4.
CVAX CPU CHIP DESIGN SPECIFICATION Page 344
MICROSEQUENCER
A "pop" consists of a read during PHI4 followed by a post-increment of the
USTACK entry pointer during PHI3.
The USTACK entry pointer operates in a circular fashion. Shifting of the
USTACK entry pointer follows the following equations.
INCREMENT = .not.TRAP_PND .and. RETURN .and. .not.STALL .and. PHI3
DECREMENT = [ TRAP_PND .or.( CALL .and. .not.STALL ) ] .and. PHI3
RETURN = MIB<12> .and. BCS=4
CALL = .not.MIB<12> .and. MIB<11>
7.2.2 Current Microaddress Latch (CMAL) -
The Current Microaddress Latch latches MAB data during PHI3 each cycle
unless STALL is asserted, in which case the data present in the latch is
held. The outputs of the CMAL drive the CMAB lines, which connect to the
Stack Input Mux, the Current Microaddress Incrementer, and the MAB Mux.
7.2.3 Current Microaddress Incrementer And Latch (CMAI) -
The Current Microaddress Incrementer consists of a 7 bit incrementer and
an 11 bit latch. CMAB<6:0> are incremented by one each cycle during PHI4.
This incremented value and CMAB<10:7> are latched during PHI2 and drive
the Microstack Input Mux via the Incremented Current Microaddress Bus
(ICMAB) <10:0>.
7.2.3.1 Microcode Notes (MICROCODE ALLOCATION RESTRICTION) -
The Current Microaddress Incrementer increments only the 7 least
significant bits of the CMAB. Therefore the last microinstruction in a
128 word block cannot cause a subroutine call.
7.2.4 Microstack Input Mux (USIM) -
The Microstack Input Mux selects one of two sources to be presented to the
Microstack Write Buffer. The Current Latched Microaddress Bus and the
Incremented Current Microaddress Bus are the two sources to the Microstack
Input Mux. Control signal USTACK_INPUT_SEL chooses which source will be
presented to the Microstack Input Latch. The outputs of the USIM are
valid during PHI4,PHI1, and PHI2.
The control for the USIM selection is simply:
if UTRAP_PND then select CMAB
if .not.UTRAP_PND then select ICMAB
CVAX CPU CHIP DESIGN SPECIFICATION Page 345
MICROSEQUENCER
7.2.5 Microstack Write Buffer (USWB) -
This tristate buffer drives true and complement data into the Microstack
register file via USDB<10:0> during PHI4 if a USTACK_WRITE has been
selected. USTACK_WRITE asserts for Microtraps and Subroutine Calls.
USTACK_WRITE = [ ( .not.MIB<12> .and MIB<11> .and. .not.STALL ) .or.
TRAPPND ] .and.PHI4
7.2.6 Microaddress Bus Mux (MAB Mux) -
The Microaddress Bus Mux selects one of six sources to be passed to the
MAB Latch. The MAB Latch in turn then drives MAB<10:0>. MAB Mux output
bits <10:4,0> directly become MAB<10:4,0>. MAB Mux output bits <3:1> are
logically OR'ed with UTEST<2:0> to create MAB<3:1> except when the signal
G_S%TEST_EXTMAB_L is asserted. In this case G_S%MLO_L<3:1> are passed
directly through the OR logic to define G_S%MAB_H<3:1>.
CVAX CPU CHIP DESIGN SPECIFICATION Page 346
MICROSEQUENCER
The following table shows all of the combinations of sources that the MAB
Mux outputs:
<----------------------MAB--------------------------->
MAB Mux Decode | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
----------------------------------------------------------------------------
JUMP | MIB<10:0> |
----------------------------------------------------------------------------
I Box DISPATCH | IMAB<10:0> |
----------------------------------------------------------------------------
CASE * | CMAB<10:7> | MIB<6:0> |
----------------------------------------------------------------------------
MICROTRAP * | UTRAB<10:0> |
----------------------------------------------------------------------------
RETURN | USOB<10:0> |
----------------------------------------------------------------------------
TEST MODE | TEST_MAB<10:0> |
----------------------------------------------------------------------------
* UTEST<2:0> value will cause final determination on MAB<3:1>.
7.2.7 Microaddress Bus Latch (MAB Latch) -
The MAB Latch for MAB <10:0> is updated during PHI1 and holds the address
valid during PHI2, PHI3, and PHI4.
7.2.8 Microtrap Address Generator (UTRAG) -
The Microtrap Address Generator receives trap request signals from the
BIU, M Box, E Box, and FPA, prioritizes these these requests and outputs a
Base Microtrap Address for the highest priority request pending. This
address is supplied to the MAB Mux via the Microtrap Address Bus and is
valid during PHI1 and PHI2. The UTRAG also generates TRAP_PND the
inclusive or of all the trap request lines.
UTRAP PRIORITIES: 3-0 (3 = highest prority): 3 BIU * (STALL ASSERTED)
2 FPA * (STALL ASSERTED)
1 M Box * (STALL ASSERTED)
0 E Box branch taken (STALL NOT ASSERTED)
0 E Box integer overflow (STALL ASSERTED)
* Only microtraps which drive UTEST<2:0> to select specific dispatch.
All other microtraps go to one fixed address.
7.2.9 STALL Latch (SL) -
The STALL Latch opens during PHI3 to record the value of STALL at that
CVAX CPU CHIP DESIGN SPECIFICATION Page 347
MICROSEQUENCER
time and hold that value valid until the next update during the following
PHI3.
7.3 Control Logic
7.3.1 MAB Mux Control Logic -
The MAB Mux control logic decides which one of the six sources to the MAB
Mux will be allowed to pass through to the MAB Latch.
The following table describes the MAB Mux Control Logic:
MAB Mux Source Equation
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MIB<10:0> .not.TRAP_PND .and. .not.TEST_EXT_MAB .and. .not.MIB<12>
IMAB<10:0> .not.TRAP_PND .and. .not.TEST_EXT_MAB .and. MIB<12> .and.
( BCS=8 .or.
BCS=A .and. DL=BWL .and. AT=RVM .or.
BCS=B .and. AT=RVM .or.
BCS=C .and. DL=BWL .and. AT=R .or.
BCS=D .and. AT= R .or.
BCS=E .and. AT=AV .or.
BCS=F .and. DL=BWL )
MIB<6:0>, .not.TRAP_PND .and. .not.TEST_EXT_MAB .and. MIB<12> .and.
CMAB<10:7> ( BCS=A .and. ( DL=.not.BWL .or. AT=A) .or.
BCS=B .and. AT=A .or.
BCS=C .and. ( DL=.not.BWL .or. AT=.not.R ) .or.
BCS=D .and. AT=.not.R .or.
BCS=E .and. AT=.not.AV .or.
BCS=F .and. DL=.not.BWL .or.
MIB<11> )
NOTE: MIB<11> = BCS codes 10 to 1F
BCS codes 14,1F not used
UTRAB<10:0> TRAP_PND .and. .not.TEST_EXT_MAB
USOB<10:0> .not.TRAP_PND .and. .not.TEST_EXT_MAB .and. MIB<12> .and. BCS=4
TEST_MAB<10:0> TEST_EXTMAB_H
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DL= DATA LENGTH (byte,word,long,quad)
BWL= BYTE .or. WORD .or. LONG
AT= ACCESS TYPE
BCS= BRANCH CONDITION SELECT
X = DON'T CARE
CVAX CPU CHIP DESIGN SPECIFICATION Page 348
MICROSEQUENCER
7.4 Timing Summary
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Phase 1 - All sources to MAB Mux become valid
- MAB Latches are opened
- UTEST Latches are opened
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Phase 2 - MAB Latches are closed
- CMAI output latch is opened
- UTEST Latches are closed
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Phase 3 - TRAP_PND becomes valid
- Precharge Microstack Data Bus
- Current Microaddress Latch opened (if Stall not asserted)
- STALL Latch opens
- Microstack increment or decrement conditionally occurs
- CMAI output latch is closed
- Precharge UTEST
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Phase 4 - Current Microaddress Latch closed
- Current Microaddress Incrementer
increments the CMAB and drives the new
value on the ICMAB
- STALL Latch closes
- WRITE Microstack conditionally occurs
- READ Microstack always
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
7.5 Functional Description
This section describes the microinstruction control of the Microsequencer,
the microtrap mechanism, and finally, test mode.
7.5.1 Microsequencer Control Interpretation -
For all microinstructions, the lower 13 bits are used to control the
Microsequencer. Bit<12> selects between one of two formats:
12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+
| | BRANCH | |
BRANCH | 1| COND. SEL | BRANCH OFFSET |
+--+--+--+--+--+--+--+--+--+--+--+--+--+
12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+
| | | |
JUMP | 0|SB| JUMP ADDRESS |
CVAX CPU CHIP DESIGN SPECIFICATION Page 349
MICROSEQUENCER
+--+--+--+--+--+--+--+--+--+--+--+--+--+
7.5.2 Branch Format -
The branch format is used when microinstruction bit<12> = 1. It allows
two, four, or eight way CASE branches within a 128 word page.
7.5.3 Branch Offset (BO) MIB<6:0> -
The Branch Offset field contains an offset that is presented to the MAB
Mux as the seven least significant next address bit. The five remaining
next address bits are supplied to the MAB Mux via CMAB<10:7>.
CVAX CPU CHIP DESIGN SPECIFICATION Page 350
MICROSEQUENCER
7.5.4 Branch Condition Select (BCS) MIB<11:7> -
The BCS field defines the branch function to be performed by the
Microsequencer.
BCS Value Function
~~~~~~~~~ ~~~~~~~~~~~~~
0
1
2
3
4 RETURN
5
6
7
8 decode next specifier
9
0A if DL.BWL and AT.RVM then DEC.NEXT else goto
0B if AT.RVM then DEC.NEXT else goto
0C if DL.BWL and AT.R then DEC.NEXT else goto
0D if AT.R then DEC.NEXT else goto
0E if AT.AV DEC.NEXT else goto
0F if DL.BWL DEC.NEXT else goto
10 ALU.NZV case
11 ALU.NZC case
12 SC<2:0> case
13 SC<5:3> case
14
15 PSL<26:24> case
16 STATE<2:0> case
17 STATE<5:3> case
18 Mem Mgt1 status case
19 Mem Mgt2 status case
1A Mem Mgt3 status case
1B FPA, DL case
1C interrupt,rmode case
1D OPCODE<2:0> case
1E AT, ID load case
1F
7.5.5 Jump Format -
The jump format is used when microinstruction bit<12> = 0. It allows
unconditional jumps and subroutine calls to anywhere in the 1600 word
Control Store.
CVAX CPU CHIP DESIGN SPECIFICATION Page 351
MICROSEQUENCER
7.5.6 Subroutine Control Bit (SB) MIB<11> -
The Subroutine Control Bit controls pushing the Microsubroutine Stack. If
it is set, then Microstack Input Bus data is pushed onto the
Microsubroutine Stack.
7.5.7 Jump Address Field MIB<10:0> -
The Jump Address field specifies the eleven microaddress bits directly.
This allows freedom to jump anywhere in the Control Store.
7.5.8 Microtrap Mechanism -
The microtrap mechanism provides a means of diverting the normal microcode
flow in response to a hardware event.
During each microcycle, the Microsequencer examines the microtrap request
inputs. If a request is pending, the Microsequencer asserts TRAP_PND
which signals the Control Store to force the next microinstruction to
contain zero in all fields. Zero is a NOP microinstuction. During the
next PHI1, UTRAB<10:0> is driven with a base address for the microtrap
routine. The MAB Mux selects UTRAB<10:0> as the source to MAB<10:0>. The
BIU, FPA, and M Box, as sources of the microtrap can generate multiple
microtrap dispatches (up to eight possible) by driving UTEST<2:0> with the
appropriate code. The E Box sends two separate lines to the
microsequencer to request two different microtrap dispatches. The
microaddress which is generated is based on a priority encoding of the
microtrap requests. The signal TRAP_PND is the inclusive OR of all the
microtrap request lines.
Microtrap UTRAG Base Microtrap Dispatch
Priority Request Input Address (HEX) Address (HEX) Class Microcode Location
+--------+----------------+---+----------------+----------------------+-------------------------+--------------------------+
3 BIU 130 130 READ VIRTUAL IE.BUSERR.READ.VIRT
BIU 130 132 READ PHYSICAL IE.BUSERR.READ.PHYS
BIU 130 138 WRITE VIRTUAL IE.BUSERR.WRITE.VIRT
BIU 130 13A WRITE PHYSICAL IE.BUSERR.WRITE.PHYS
BIU 130 136 INTERRUPT VECTOR READ IE.BUSERR.INT.VEC
BIU 130 134 EXTERNAL REGISTER READ IE.BUSERR.READ.IPR
2 FPA 140 140 PROTOCAL ERROR FP.PROT.ERROR
FPA 140 142 RESERVED INSTRUCTION FP.RSRV.INST
FPA 140 144 RESERVED OPERAND FP.RSRV.OPER
FPA 140 146 FLOATING DIVIDE BY ZERO FP.DIVIDE.BY.ZERO
FPA 140 148 FLOATING POINT UNDERFLOW FP.UNDERFLOW
FPA 140 14A FLOATING POINT OVERFLOW FP.OVERFLOW
1 M Box 120 122 M = 0 MM.M0
M Box 120 126 CROSS-PAGE MM.CPB
M Box 120 124 ACV/TNV MM.ACV.TNV
CVAX CPU CHIP DESIGN SPECIFICATION Page 352
MICROSEQUENCER
M Box 120 120 TB.MISS MM.TBM
0 E Box 100 100 BRANCH TAKEN IE.COND.BRANCH
E Box 110 110 OPTIMIZED INTEGER IE.INTOV
OVERFLOW
7.5.9 Microsequencer Test Mode -
When Microsequencer Test Mode is selected the Microsequencer accepts an
externally supplied value as the next microaddress. The signal
T_S%EXT_MAB_H indicates when Test Mode has been selected.
7.6 Microsequencer Test Hooks
The TEST_MAB Bus supplies externally generated addresses to the
Microsequencer's MAB Mux. When in Microsequencer Test Mode, this address
is used to access the Control Store. In addition, when in this mode
values driven on the Microtest Bus have no affect on MAB<3:1>. Refer to
the TESTSPEC for external I/O pin redefinition when forcing external MAB
addresses.
CVAX CPU CHIP DESIGN SPECIFICATION Page 353
MICROSEQUENCER
7.7 Microsequencer Global Signal Dictionary
G = GLOBAL SIGNAL L = PRECHARGING LOW
S = STATIC H = PRECHARGING HIGH
P = PIN SIGNAL = = VALID SIGNAL
PL = PRECHARGED LOW x = NOT VALID
PH = PRECHARGED HIGH _ = LOW ~ = HIGH
C = CLOCK
USEQ_GLOBAL_DICTIONARY +----------+---------+---------+----------+
updated 8-APR-86 | PHI1 | PHI2 | PHI3 | PHI4 |
+---------------V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| Signal | FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name | Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| ACCESS_TYPE | G_S%ACCESS_TYPE_H<1:0> |===================xxxxxxxxxxx=========| ACCESS_TYPE REGISTER CONTENTS |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | valid PHI4 - 1nS to PHI3 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| BIU_TRAP | G_S%BIU_TRAP_L |=========xxxxxxxxx=====================| BIU TRAP CONDITION DETECTED |
| | | | | | | C load = 3.8 pF |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - MBOX,USEQ,IBOX |
| | | | | | | Valid PHI2 + 18ns |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| BRANCH_TRAP | G_S%BRANCH_TAKEN_TRAP_L |xxxxxxxxxxxxxxxxxx====================x| BRANCH TAKEN TRAP LINE |
| | | | | | | |
| | | | | | | C load = 2.5pF |
| | | | | | | |
| | | | | | | Source - EBOX |
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | |
| | | | | | | valid PHI3 - 6nS to PHI1 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| DL | G_S%DL_H<1:0> |=====================xxxxxxxxx=========| DATA LENGTH REGISTER CONTENTS |
| | | | | | | |
| | | | | | | C load = 5.4pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX,MBOX,USEQ |
CVAX CPU CHIP DESIGN SPECIFICATION Page 354
MICROSEQUENCER
| | | | | | | valid PHI4 + 2nS to PHI3 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| FPU_TRAP | G_S%FPU_TRAP_L |=========xxxxxx========================| FPU TRAP REQUEST LINE |
| | | | | | | C load = 2.2 pF |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - USEQ,IBOX |
| | | | | | | Valid PHI2 + 15ns |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| INT_OVF | G_S%INT_OVFL_L |HHHHHHHHHH~~xxxxxx=====================| INTEGER OVERFLOW LINE |
| | | | | | | |
| | | | | | | C load = 2.1pF |
| | | | | | | |
| | | | | | | Source - EBOX |
| | | | | | | |
| | | | | | | Dest - IBOX, USEQ |
| | | | | | | |
| | | | | | | precharged PHI1 valid PHI3 - 6nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MAB | G_S%MAB_H<10:0> |xxxxxxxx===============================| MICRO ADDRESS BUS |
| | | | | | | C load = 1pF |
| | | | | | | Source - USEQ |
| | | | | | | |
| | | | | | | Dest - CONTROL STORE |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MIB | G_S%MIB_H<12:0> |===================xxxxxxxxx===========| MICRO-INSTRUCTION BUS |
| | G_S%MIB_L<12:7> | | | | | |
| | | | | | | |
| | | | | | | C load = 5pF |
| | | | | | | |
| | | | | | | Source - CONTROL STORE |
| | | | | | | |
| | | | | | | Valid low 1 nS before rising edge of PHI4 |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MLO_L | G_S%MLO_L<3:1> |xxxxxxxx===============================| MAB LATCH OUT TO UTEST "OR" LOGIC |
| | | | | | | C load .7pF |
| | | | | | | Source - USEQ |
| | | | | | | |
| | | | | | | Dest - CONTROL STORE |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MMGT_TRAP | G_PH%MMGT_TRAP_L |HHHHHHHHHH~~xxxxxxx====================| MEMORY MANAGEMENT TRAP |
| | | | | | | C load = 3pF |
| | | | | | | Source - MBOX |
| | | | | | | |
| | | | | | | Dest - USEQ,IBOX |
CVAX CPU CHIP DESIGN SPECIFICATION Page 355
MICROSEQUENCER
| | | | | | | Valid PHI2 + 21ns |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PHI1 | G_C%PHI1_H |/~~~~~~~\\\____________________________| PHASE 1 CLOCK |
| | | | | | | |
| | | | | | | C load = 140 pF |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PHI2 | G_C%PHI2_H |_________/~~~~~~~~\\\__________________| PHASE 2 CLOCK |
| | | | | | | |
| | | | | | | C load = 114 pF |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PHI3 | G_C%PHI3_H |___________________/~~~~~~~~\\\________| PHASE 3 CLOCK |
| | | | | | | |
| | | | | | | C load = 117 pF |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PHI4 | G_C%PHI4_H |\\___________________________/~~~~~~~~~| PHASE 4 CLOCK |
| | | | | | | |
| | | | | | | C load = 133 pF |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| RESET_S | G_S%RESET_S_H |~~\____________________________________| RESET Stretched |
| | | | | | | |
| | | | | | | Source - CLOCK LOGIC |
| | | | | | | |
| | | | | | | C load = 5pF assertion is asynchronous |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| STALL | G_PH%STALL_L |HHHHHHHHHH~~xxxxxx=====================| CHIP-WIDE STALL SIGNAL |
| | | | | | | |
| | | | | | | Source - MBOX,BIU,EBOX,IBOX,uSEQ |
| | | | | | | |
| | | | | | | C load = 12pF |
| | | | | | | valid PHI2 + 21ns |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| TEST_EXTMAB | G_S%TEST_EXTMAB_L |============xxxxxxxx===================| DRIVE MAB WITH EXTERNAL MAB FROM PINS |
| | | | | | | |
| | | | | | | Source - TEST LOGIC |
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | C load = 2.4 pF |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| TEST_MAB | G_S%TEST_MAB_H<10:0> |==================xxxxxxxxxxx==========| EXTERNAL TEST MAB FROM PINS |
| | | | | | | |
| | | | | | | Source - TEST LOGIC |
CVAX CPU CHIP DESIGN SPECIFICATION Page 356
MICROSEQUENCER
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | C load = 2.2 pF |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| TRAP_PND | G_S%TRAP_PND_L |~~~~~~~~~~~~~~~~~~~~~\\\_______/~~~~~~~| Trap Pending - Zero MIB's |
| | | | | | | |
| | | | | | | Source - USEQ |
| | | | | | | |
| | | | | | | Dest - Control Store |
| | | | | | | C load = 1.7 pF |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| UTEST | G_PH%UTEST_L<2:0> |~xxxx===============HHHHHHHHHH~~~~~~~~~| MICRO-TEST BUS |
| | | | | | | |
| | | | | | | Source - BIU, IBOX, MBOX, EBOX |
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | |
| | | | | | | C load = 4. |
| | | | | | | |
| | | | | | | Precharged during PHI3 |
| | | | | | | Conditionally discharged during PHI1 |
| | | | | | | Latched on falling edge of PHI1 |
| | | | | | | Must be valid 15 nS after rising edge |
| | | | | | | of PHI1. |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
7.8 Microsequencer Internal Signal Dictionary
+----------+---------+---------+----------+
USEQ INTERNAL DICTIONARY | PHI1 | PHI2 | PHI3 | PHI4 |
V---------------------------V----------+---------+---------+----------V--------------------------------------------V
| FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| NAME |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| U_S%CALL_H |XXX====================================| CALL microinstruction decoded |
| | | | | | |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| UMD PHI2, 3, 4 USK BY L.E. PHI3 None No |
| |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| U_S%CMAB_H<10:7> |====================XXX================| Current Microaddress Bus |
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 357
MICROSEQUENCER
| | | | | | |
| Spice Ref (Block/Text): Last Updated: |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| USK PHI4, 1, 2 USK PHI4 USIM NO |
| UMM PHI1 UMM |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| U_S%MABMUX_SEL_CMAB |_/========\____________________________| Select address source to the MAB MUX |
| U_S%MABMUX_SEL_IMAB | | | | | |
| U_S%MABMUX_SEL_MIB | | | | | |
| U_S%MABMUX_SEL_TEST |
| U_S%MABMUX_SEL_USOB |
| U_S%MABMUX_SEL_UTRAB |
| |
| Spice Ref (Block/Text): USEQ_MIB_DECODES/SPICE_DECODES_SIM_NOTES Last Updated: 28-MAR-86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| UMD PHI1 + 7ns UMM Early PHI1 None NMOS pass |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| U_S%RETURN_H |XXX====================================| RETURN microinstruction decoded |
| | | | | | |
| | | | | | |
| Spice Ref (Block/Text): Last Updated: |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| UMD PHI1, 2, 3 USK BY L.E. PHI3 None No |
| |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| U_S%TRAP_PND_L |~~~~~~~~~~~~~~\\\\\___________/////////| Inclusive OR of all UTRAP requests |
| | | | | | |
| | | | | | |
| Spice Ref (Block/Text): USEQ_MAB_MUX/SPICE_UTRAP_SIM_NOTES Last Updated: 26-MAR-86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| UMD before PHI3 L.E. USK by PHI3 L.E. UTRAPLAT No |
| for BRANCH_TAKEN trap |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| U_S%TRAP_PND_LATCHED_L |====================XXX================| PHI3 latched TRAP_PND |
| | | | | | |
| | | | | | |
| Spice Ref (Block/Text): USEQ_MAB_MUX/SPICE_UTRAP_SIM_NOTES Last Updated: 26_MAR_86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| USK PHI3 + 12 ns, USK, UMD before PHI4 L.E. None No |
| PHI4, 1, 2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| U_S%USOB_H<10:0> |====================\___________/======| Microstack Output Bus |
| | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 358
MICROSEQUENCER
| | | | | | |
| Spice Ref (Block/Text): USTACK_SIM/SPICE_USTACK_SIM_NOTES Last Updated: 17-APR-86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| USK PHI4 + 22 ns UMM all of PHI1 UMM NO |
| PHI1, 2 |
^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | |
| U_S%UTRAB_H<6:4> |====================XX=================| Microtrap Address Bus |
| | | | | | |
| | | | | | |
| Spice Ref (Block/Text): USEQ_MAB_MUX/SPICE_UTRAP_SIM_NOTES Last Updated: 20-MAR-86 |
| |
| Driven by: When Valid: Used by: When Needed: Hidden Cap: Drives Pull up/down: |
| UMD PHI4, 1, 2 UMM all of PHI1 UMM NO |
| |
^------------------------------------------------------------------------------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 359
MICROSEQUENCER
7.9 Microsequencer Block Diagram
TRAP REQUESTS | | |
| | | |
V |IMAB<10:0>| |MIB<10:0>
BIU +----------------+ | | |
--------------| uTrap Request | TRAP_PND | |TEST_MAB<10:0>
M Box | Prioritize |---------- | | | USOB<10:0> +-------------------------+ +-----+
--------------| and | | | | +-------------| Microstack |-| CNTL|
E Box <1:0> | Address | | | | | | 8 Words Deep | | |
--------------| Generate |-----+ | | | | +-------------------------+ +-----+
FPA | | | | | | | |USDB<10:0>
--------------| | |UTRAB<6:4> | | | | +-------------------------+
| | | | | | | | USTACK WRITE BUFFER |--USTACK_
| | | | | | | +-------------------------+ WRITE
| | | | | | | |
| | | | | | | |
+----------------+ | | | | | |
| | | | | |
| | | | | +-------+ |USIB<10:0>
| | | | | | |CMAB<10:7> |
V V V V V V | +-------------------------+ +-----+
+-------------+ +-----------------------------------------------------------------+ | | Stack Input Mux |-| SIM |
| Mux Control |------| MAB Mux, | | +-------------------------+ | CNTL|
+-------------+ | Latch and Drivers | | |CMAB<10:0> | +-----+
+-----------------------------------------------------------------+ | | |CIMAB<10:0>
PHI1 +-----------+ | |MAB<10:4,0> +--------------------+ | | PHI2 +--------------------+
---------| UTEST | |ORMAB<3:1> |-------------->|Current Microaddress| | | ----| ICMAB Latch |
| LATCH |+----+ | +--------|-------------->| Latch |->-------------+ +--------------------+
+-----------+ | | | | +--------------------+ | |Current Microaddress|
UTEST<2:0> | +---------+ | | .not.STALL .and. PHI3 | +----| Incrementer |
>--------------+ | .or. | | | >-----------------------+ | |
| | LOGIC | | | +--------------------+
| +---------+ | |
+--------------+ |MAB<3:1> | |MAB<10:4,0>
| UTEST |--+ |-------------+ |
| PRECHARGE | | | |
+--------------+ | V V
PHI3 |
-----------------------+
E Box <0> = E Box branch taken
E Box <1> = E Box optimized integer overflow
CVAX CPU CHIP DESIGN SPECIFICATION Page 360
MICROSEQUENCER
7.10 Change Requests ( ECO )
The following change requests have been reflected in this revision of the
spec:
o 6APR04DRD.1
7.11 ISSUES
1. Does microsequencer test mode affect the microsequencer in any
way other than the source of the next address? Does the
microstack operate differently in this mode?
ANS: 8-APR-85 D.R.D. UTEST<2:0> have no control over MAB<3:1>
values when in Test mode. Microstack operations are unchanged.
2. Does TRAP_PND or RESET force all 41 bits of the microinstuction
to zero or just certain fields?
ANS: 8-APR-85 D.R.D. All 41 bits will be zeroed by TRAP_PND or
RESET.
3. Will STALL be valid only during PHI3?
ANS: 2-May-85 P.I.R. Yes - STALL should only be looked at
during (early) PHI3.
4. Microtrap priorities and base addresses need definition and
inclusion in this specification.
ANS: 1-MAY-85 D.R.D. Added to spec.
5. Will BIU send up one trap request line which includes FPA traps
or two separate lines?
ANS: 8-APR-85 D.R.D. Two lines must be sent up.
6. Should the increment of the CMAB ripple through all eleven bits
or can it ripple through bit seven only?
ANS: 1-MAY-85 D.R.D Current Microaddress Incrementer will
increment seven bits only. The allocation restriction is not a
problem.
7. Will UTEST<2:0> be valid during PHI1,PHI2,PHI3 or must
Microsequencer sustain values on UTEST<2:0>?
ANS: 8-APR-85 D.R.D. The Microsequencer latches values sampled
from UTEST<2:0>.
CVAX CPU CHIP DESIGN SPECIFICATION Page 361
MICROSEQUENCER
8. How late can UTEST<2:0> become valid and still make the 1 ns
MIB<40:0> setup time to PHI4?
ANS: 9-APR-86 D.R.D. UTEST must be valid 15 ns maximum into
PHI1.
9. Are there scanner/reducers on the MAB ? If so, do they reside in
the Microsequencer? Same questions for UTEST<2:0>.
ANS: 2-May-85 P.I.R. There are scanner/reducers on both the MAB
and UTEST<2:0>. These are in the microsequencer.
CVAX CPU CHIP DESIGN SPECIFICATION Page 362
CONTROL STORE
8 CONTROL STORE
The Control Store consists of 1600 41 bit words of read only memory (ROM).
Each 41-bit word is divided into a 28-bit portion which controls the data
path, and a 13-bit portion which controls the Microsequencer. For details
on the microinstruction format, see the "Control Fields Summary" section.
8.1 Functional Summary
Access to the Control Store is under the control of the Microsequencer.
The Microsequencer drives the address of the ROM row to be accessed onto
the Microaddress Bus (MAB<10:4,0). MAB<3:1>, also supplied by the
Microsequencer, selects the desired COLUMN. At the start of PHI2, the
Control Store accesses the ROM row specified by MAB<10:4,0>,and then the
COLUMN specified by MAB<3:1>. Microinstruction data is accessed, latched,
and driven on the Microinstruction Bus (MIB<40:0>). The new
microinstruction is valid on the MIB<40:0> 1ns minimum before PHI4, during
PHI4, PHI1, and PHI2. Note that the Control Store access is pipelined
with respect to execution, i.e., the Control Store is accessing the next
microinstruction while the current microinstruction is being executed.
Physically, the Control Store is organized as a ROM array of 200 x 328
bits. Eight microwords (8 X 41 = 328) are interleaved per row of the
array. The rows are fed into a local multiplexors/sense amps to create
the 41-bit microinstruction output. There is one sense amp for each of
the 41 bits of the microword. The Column Mux selects one of the eight
words to be sensed by a sense amp via control from a 3 to 8 decoder
looking at MAB<3:1>. Each of the 41 sense amps looks at one bit position
of the Microword. For example, the sense amp for MIB<0> is fed by a
Column Mux that has 8 "bit zeroes" from 8 different microwords driving its
data inputs each time a row is selected. One of these 8 "bit zeroes" is
passed through to the sense amp. The new microinstruction is latched in
the 41-bit MIB Latch, unless the signal STALL is asserted , in which case
the MIB Latch continues to hold present data. The MIB Latch is overriden
to a NOP (MIB<40:0>=0) if the Microsequencer asserts signal TRAP_PND or
RESET asserts.
Eleven Microaddress Bus lines are used to address the contents of the ROM.
This allows for a maximum of 2048 unique addresses to the ROM. The ROM
itself is 1600 words in size, therefore 448 addresses are decoded as
"outside" of the ROM. In other words if one of these addresses is used to
access the ROM the ROM will not select any word line and will return all
zeroes on the MIB by default. In order to simplify design in the IBOX the
actual addressing of the ROM contents is as shown below.
Microaddresses (HEX) ROM contents returned
---------------------------------------------------------
0 thru 61F microcode (1568 words)
620 thru 7DF all zeroes returned on MIB
7E0 thru 7FF microcode (32 words)
CVAX CPU CHIP DESIGN SPECIFICATION Page 363
CONTROL STORE
8.2 MIB Latch/MIB Drivers
The MIB latch has three modes of operation:
Function Description
-------- -----------
capture sense amps PHI3 .and. ( .not. STALL .and. .not. TRAP_PND .and. .not. RESET)
zero latch RESET .or. ( TRAP_pnd .and. PHI3 )
keep old data STALL .and. ( .not. TRAP_PND .and. .not. RESET )
zeroing the latch forces a NOP microinstruction on the MIBS.
The sense amps are captured during normal operation, i.e., no microtrap
pending and the chip is not being reset. The latch is zeroed during a
microtrap in order to force a NOP on the MIBs; and during RESET in order
to force a NOP jump to 0 (powerup microcode) on the MIBs. The old
microinstruction is recycled any time some section of the chip issues
STALL to hold off execution (no microtrap). Irrespective of the operation
mode, the MIB Latch drivers guarantee that the microinstruction is valid
1ns before PHI4.
8.3 Control Store Test Hooks
A 44-bit scanner/reducer on the Microinstruction Bus and UTEST Bus allows
external monitoring of microinstruction data read out of the Control Store
ROM and values recorded from the UTEST bus. Two modes of operation make
the scanner/reducer a very useful test and debug tool. Scan mode involves
parallel loading MIB data into a 44-bit shift register and then shifting
the data out serially to external observers via a redifined I/O pin.
Reducer mode allows "at speed" signature analysis of the MIB/UTEST data.
OPERATING MODES OF THE SCANNER/REDUCER
+---------------------------------+
| RED/SCAN | RS_LOAD | MODE | Feedback tap positions for the 44 stages of the MIB/UTEST
+---------------------------------+ scanner/reducers occur at the outputs of stages 10, 11, and 36. Refer
| 0 | 0 | REDUCER | to the TEST LOGIC section of the CVAX Chip Spec. for
+---------------------------------+ a more detailed description of the scanner/reducer.
| 1 | 0 | SCANNER |
+---------------------------------+
| X | 1 | LOAD |
+---------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 364
CONTROL STORE
8.4 Control Store Block Diagram
MAB<10:0> from microsequencer
| | |
|MAB<3:1> |MAB<4,0> |MAB<10:5>
| | |
| +--------------+ +-------------------------+
| | FINAL | | PREDECODE |
| | PREDECODE | | |
| +--------------+ +-------------------------+
COL_SEL_ENB +------------------+ |FPREDEC<3:0> |PREDEC<11:0>
------------| COLUMN SELECT | | +-------------------------+
TRAP_PND +------------------+ | | ROW DECODE |
-----------------------+ | WORD_SEL<7:0> | +-------------------------+
MIB_UPDATE | | | |
--------------------+ | | | +-------------------------+
| | | 328 bit lines +----------| WORD LINE DRIVERS |
| | | | 200 word lines +-------------------------+
+------+ +------+ +------+ V ------> ||||||||||||||||||||||||| +-------+
| M | | S | | 8:1 |--------------------------------+++++++++++++++++++++++++---| B |
| I | | E | | M |--------------------------------+++++++++++++++++++++++++---| I |
| B | | N | | U |--------------------------------+++++++++++++++++++++++++---| T |
| | | S | | X |--------------------------------+++++++++++++++++++++++++---| |
| L | | E | | |--------------------------------+++++++++++++++++++++++++---| L |
| A | | | | |--------------------------------+++++++++++++++++++++++++---| I |
| T | | A | | |--------------------------------+++++++++++++++++++++++++---| N |
MIB<40:0> | C | | M | | |--------------------------------+++++++++++++++++++++++++---| E |
<-----------------| H | | P | | |--------------------------------+++++++++++++++++++++++++---| |
| | / | | S | | |--------------------------------+++++++++++++++++++++++++---| P |
| | D | | | | |--------------------------------+++++++++++++++++++++++++---| R |
| | R | | | | |--------------------------------+++++++++++++++++++++++++---| E |
| | I | | | | |--------------------------------+++++++++++++++++++++++++---| C |
| | V | | | | |--------------------------------+++++++++++++++++++++++++---| H |
| | E | | | | |--------------------------------+++++++++++++++++++++++++---| A |
| | R | | | | |--------------------------------+++++++++++++++++++++++++---| R |
| | S | | | | |--------------------------------+++++++++++++++++++++++++---| G |
| | | | | | | | E |
| +------+ +------+ +------+ +-------+
BLP | | |
--------+---------------------+-----------------------------------------------------------------------------+
|
| +------------------------+
+-----------| |
| | RS_MIB/UTEST
UTEST<2:0> | SCANNER/REDUCER |----------------->
--------------------| |
+------------------------+
RS_LOAD | | |
--------------------------+ | |
RED_SCAN | |
-----------------------------+ |
RS_CLK_1,RS_CLK_2 |
CVAX CPU CHIP DESIGN SPECIFICATION Page 365
CONTROL STORE
--------------------------------+
8.5 Control Store Signal Dictionary
UPDATED: 9-SEP-86 +----------+---------+---------+----------+
from Global Signal Dictionary | PHI1 | PHI2 | PHI3 | PHI4 |
V--------------------------V-----------V----------+---------+---------+----------V---------------------------------------------+
| Signal | I/O, |0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 0| DESCRIPTION OF SIGNAL |
| Name | Section |0-5-0-5-0-5-0-5-0-5-0-5-0-5-0-5-0-5-0-5-0| |
+--------------------------+-----------++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+^---------------------------------------------+
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| LOAD_REDUCERS | G_S%LOAD_REDUCERS_L |/~~~~~~~~~~~~~~~~~~~~~~~~~~~~\=========| Parallel load reducers |
| | | | | | | C load = 5.4 pF |
| | | | | | | Source - Test Logic |
| | | | | | | |
| | | | | | | Dest - IBOX, uSeq, Control Store |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MAB | G_S%MAB_H<10:0> |xxxxxxxx===============================| MICRO ADDRESS BUS |
| | | | | | | C load = 1pF |
| | | | | | | Source - USEQ |
| | | | | | | |
| | | | | | | Dest - CONTROL STORE |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MIB | G_S%MIB_H<40:0> |===================xxxxxxxxx===========| MICRO-INSTRUCTION BUS |
| | G_S%MIB_L<40:7> | | | | | |
| | | | | | | |
| | | | | | | C load = 5pF |
| | | | | | | |
| | | | | | | Source - CONTROL STORE |
| | | | | | | |
| | | | | | | Valid low 1 nS before rising edge of PHI4 |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MLO_L | G_S%MLO_L<3:1> |xxxxxxxx===============================| MAB LATCH OUT TO UTEST "OR" LOGIC |
| | | | | | | C load = .7 pF |
| | | | | | | Source - USEQ |
| | | | | | | |
| | | | | | | Dest - CONTROL STORE |
| | | | | | | |
---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+----------------------------------------------+
| | | | | | | |
| PHI1 | G_C%PHI1_H |/~~~~~~~\\\____________________________| PHASE 1 CLOCK |
| | | | | | | |
| | | | | | | C load = 150 pF |
CVAX CPU CHIP DESIGN SPECIFICATION Page 366
CONTROL STORE
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PHI2 | G_C%PHI2_H |_________/~~~~~~~~\\\__________________| PHASE 2 CLOCK |
| | | | | | | |
| | | | | | | C load = 150 pF |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PHI3 | G_C%PHI3_H |___________________/~~~~~~~~\\\________| PHASE 3 CLOCK |
| | | | | | | |
| | | | | | | C load = 150 pF |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PHI4 | G_C%PHI4_H |\\___________________________/~~~~~~~~~| PHASE 4 CLOCK |
| | | | | | | |
| | | | | | | C load = 150 pF |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| R_RED_OUT | G_S%R_RED_OUT_H |===================xxxxxxxx============| MIB reducer output |
| | | | | | | C load = 1.8 pF |
| | | | | | | Source - Control Store |
| | | | | | | |
| | | | | | | Dest - Test Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| REDUCE_PHI1 | G_C%REDUCE_PHI1_H |/========\_____________________________| REDUCE mode clock |
| | | | | | | |
| | | | | | | Source - Test Logic |
| | | | | | | |
| | | | | | | Dest - IBOX, uSeq, Control Store |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| RESET_S | G_S%RESET_S_H |~~\____________________________________| RESET Stretched |
| | | | | | | |
| | | | | | | Source - CLOCK LOGIC |
| | | | | | | |
| | | | | | | C load = 5pF assertion is asynchronous |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| SCAN_PHI1 | G_C%SCAN_PHI1_H |/========\_____________________________| SCAN mode clock |
| | | | | | | |
| | | | | | | Source - Test Logic |
| | | | | | | |
| | | | | | | Dest - IBOX, uSeq, Control Store |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| STALL | G_PH%STALL_L |============xxxxxx=====================| CHIP-WIDE STALL SIGNAL |
CVAX CPU CHIP DESIGN SPECIFICATION Page 367
CONTROL STORE
| | | | | | | |
| | | | | | | Source - MBOX,BIU,EBOX,IBOX,uSEQ |
| | | | | | | |
| | | | | | | C load = 12pF |
| | | | | | | valid PHI2 + 21ns |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| TRAP_PND | G_S%TRAP_PND_L |~~~~~~~~~~~~~~~~~~~~~\\\_______/~~~~~~~| Trap Pending - Zero MIB's |
| | | | | | | C load = 1.7 pF |
| | | | | | | Source - USEQ |
| | | | | | | |
| | | | | | | Dest - Control Store |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| UTEST | G_PH%UTEST_L<2:0> |~xxxx===============HHHHHHHHHH~~~~~~~~~| MICRO-TEST BUS |
| | | | | | | |
| | | | | | | Source - BIU, MBOX, IBOX, EBOX |
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | |
| | | | | | | C load = 4.5pF |
| | | | | | | |
| | | | | | | Precharged during PHI3 |
| | | | | | | Conditionally discharged during PHI1 |
| | | | | | | Latched on falling edge of PHI1 |
| | | | | | | Must be valid 15 nS after rising edge |
| | | | | | | of PHI1. |
------------------------------------------------------------------------------------------------------------------------------------
8.6 Change Requests ( ECO )
The following change requests have been reflected in this revision of the
spec:
o 5DEC05DWA.1
8.7 Issues
1. Should the Control Store include an extra bit for parity? The
V-11 Control Store (which is external) includes parity; the
MicroVAX Control Store (which is internal) does not.
RESOLVED 2-8-85 NO PARITY BIT D.R.D.
CVAX CPU CHIP DESIGN SPECIFICATION Page 368
CONTROL STORE
2. Is the Control Store properly sized? ZMOS MicroVAX only required
1600 words of microcode. The presumption here is that CMOS
MicroVAX will do substantially more warm floating point
processing that its predecessor.
RESOLVED 2-8-85 1600 WORDS ADEQUATE, ADDITIONAL WORDS WILL COST IN
AREA AND INCREASED ACCESS TIME D.R.D
3. Is a patch capability needed? The V-11 (which is a full VAX
implementation) includes patch capability; the MicroVAX (which is
a microVAX implementation) does not.
RESOLVED 2-8-85 NO PATCH CAPABILITY D.R.D
4. Can the access time requirement (two phases, approx 50 ns) be
met? With how large a control store?
RESOLVED 4-8-86 simulation show that access time can be met D.R.D
5. E Box would like MIB to be valid at least 3 nanoseconds prior to
PHI4 leading edge. "Valid" < .3V from VCC or GND.
RESOLVED 7-19-85 MIB WILL BE VALID MINIMUM 2ns BEFORE PHI4. D.R.D.
CVAX CPU CHIP DESIGN SPECIFICATION Page 369
INTERRUPT LOGIC
9 INTERRUPT LOGIC
The Interrupt Logic mediates hardware and software interrupt requests
against the current IPL and generates an interrupt request to the I Box,
if necessary. It also identifies the highest priority outstanding
interrupt to the microcode.
The Interrupt Logic also contains the logic to support a minimal Interval
Clock Control register (ICCS - processor register #24). External logic
provides a free running clock to the INTTIM L pin (this clock should be a
100Hz clock for software compatibility with VAX operating systems); the
ICCS register enables and disables clock interrupts. Access to the Next
Interval Count (NICR #25), the Interval Count (ICR #26), and the Time of
Year (TODR #27) is passed to external logic via an external processor
register cycle. If these registers are not implemented, the microcode
supports the rest of the clock processor registers as read as zero, write
is nop for software compatibility with other VAX systems.
The Interrupt Logic consists of the interrupt latches and edge detectors,
Software Interrupt Register, the interrupt priority encoder, and the
interrupt IPL and comparator.
9.1 Interrupt Latches
The interrupt latches are double-buffered latches which sample and
synchronize the interrupt inputs (HALT L, PWRFL L, INTTIM L, MEMERR L, CRD
L, and IRQ<3:0>). The IRQ lines are level sensitive: if asserted and
then deasserted before the interrupt is acknowledged, the interrupt is
ignored. The other five interrupt inputs (HALT L, PWRFL L, MEMERR L, CRD
L and INTTIM L) are pseudo edge sensitive. They are sampled,
synchronized, and input to flip-flops. Each flip-flop is set when its
input is asserted, and cleared when IRESET_H is asserted or when the
MXPS[INT.ID] register is read and matches the request level corresponding
to the flip-flop. The HALT interrupt is always enabled but will only be
arbitrated for between instructions (HALT will not cause a FPD instruction
to packup). The INTTIM flop is enabled/disabled with MACRO MTPR to ICCS
(#24) that sets/clears bit <6> (IE). When set, an interrupt request is
generated every time INTTIM_L transitions low (ie. every time the TIM
interrupt is set). When clear no interrupt is requested. Similarly if a
TIM interrupt is set and the software sets ICCS<6> an interrupt is
generated. The remaining bits in the MACRO ICCS register read as zero and
are ignored on write. In the micro machine the ICCS bit <6> is read and
written by an MXPS[ICCS]. The interrupt enable bit is bit <6> of the ICCS
register. The remaining bits are undefined on read and don't care on
write. The interval timer is a level 16 interrupt.
9.2 Highest Software Interrupt Register (HSIR).
The highest pending software interrupt is recorded in the HSIR. The HSIR
CVAX CPU CHIP DESIGN SPECIFICATION Page 370
INTERRUPT LOGIC
is read and written via an MXPS[HSIR] (WSPUR<3:0>=HSIR,WSPUR<7:4>=111).
9.3 Interrupt Priority Encoder
The CVAX architecture has 31 interrupt priority levels (IPL), used as
follows:
IPL levels interrupt condition
---------- -------------------
1F unused
1E PWRFL L asserted
1D MEMERR L asserted
1B - 1C unused
1A CRD L asserted
18 - 19 unused
17 IRQ<3> L asserted
16 IRQ<2> L asserted
16 INTTIM L asserted
15 IRQ<1> L asserted
14 IRQ<0> L asserted
10 - 13 unused
01 - 0F software interrupt request
The latched interrupt inputs are prioritized to generate a unique code for
the highest level outstanding interrupt. This code is compared to the
current IPL. If it is greater than the IPL, the interrupt identification
reads in accordance with the following table. If it is less than or equal
to the IPL, the interrupt identification reads as 0. MXPS[INT.ID] is read
onto bits<4:0> of the W_BUS by an MXPS READ microinstruction.
IPL HALT PWRFL MEMERR CRD IRQ<3> IRQ<2> INTTIM IRQ<1> IRQ<0> HSIR int ident (hex)
---- ---- ----- ------ --- ------ ------ ------ ------ ------ ---- ---------------
XXX L x x x x x x x x xxxx 1F
<1E H L x x x x x x x xxxx 1E
<1D H H L x x x x x x xxxx 1D
<1A H H H L x x x x x xxxx 1A
<17 H H H H L x x x x xxxx 17
<16 H H H H H L x x x xxxx 16
<16 H H H H H H L x x xxxx 1C
<15 H H H H H H H L x xxxx 15
<14 H H H H H H H H L xxxx 14
0F H H H H H H H H H xxxx 00
<0F H H H H H H H H H 1111 0F
<0E H H H H H H H H H 1110 0E
<0D H H H H H H H H H 1101 0D
<0C H H H H H H H H H 1100 0C
<0B H H H H H H H H H 1011 0B
<0A H H H H H H H H H 1010 0A
<09 H H H H H H H H H 1001 09
<08 H H H H H H H H H 1000 08
CVAX CPU CHIP DESIGN SPECIFICATION Page 371
INTERRUPT LOGIC
<07 H H H H H H H H H 0111 07
<06 H H H H H H H H H 0110 06
<05 H H H H H H H H H 0101 05
<04 H H H H H H H H H 0100 04
<03 H H H H H H H H H 0011 03
<02 H H H H H H H H H 0010 02
00 H H H H H H H H H 0001 01
00 H H H H H H H H H 0000 00
9.4 Interrupt IPL And Comparator
The Interrupt Logic includes a write-only copy of the PSL<IPL> field.
This copy is loaded from WSPUR<4:0> (bits<20:16> of the W_BUS) whenever
the PSL is written. The Interrupt Logic also includes an IPL comparator.
During every microcycle, the output of the interrupt priority encoder is
compared to the stored copy of the IPL. If the output of the priority
encoder is greater than the IPL, then signal FPD_INT_PENDING_H is asserted
for the I Box. If either FPD_INT_PENDING_H is asserted, or HALT is
asserted, then signal IID_IRQ_H is asserted to the I Box.
The decode of the IMIBs for the MXPS read INT.ID and ICCS and the MXPS
write ICCS is done in the E Box, and the signals MXPS_READ_INT.ID,
MXPS_READ_ICCS, and MXPS_WRITE_ICCS are driven to the Interrupt Logic.
This eliminates having to route the MIBs across the I Box to the Interrupt
Logic.
9.5 Microcode Notes
The Interrupt Logic must compare the IPL to the interrupt request and
update FPD_INT_PENDING_H and IID_IRQ_H. This means that microcode cannot
take a branch that uses the FPD_INT_PENDING_H or IID_IRQ_H signals for two
cycles after the PSL is written. In other words writes that CHANGE the
IPL, HSIR, and ICCS<6> should not be followed in either of the next two
cycles by a BRANCH IID.
MXPS Register Access Data
------------- ------ --------
INT.ID Read Only <4:0>
ICCS Read/Write <6>
HSIR Read/Write <3:0>
note: all non-data bits are don't care on WRITE and '1' on READ
The flops for HALT, PWRFL, MEMERR, INTTIM, and CRD interrupts are cleared
by an MXPS[INT.ID] and the interrupt identification being 1F(hex) for
HALT, 1E(hex) for PWRFL, 1D(hex) for MEMERR, 1C(hex) for INTTIM, and
1A(hex) for CRD. The chip does not externally acknowledge these
interrupts, therefore no MEMREQ READ MEM.PHYS.VAP.INTVEC should be issued
for these five interrupts. Because of logic delays from READ INT.ID to
clearing the interrupt out of the priority encoder, a READ INT.ID can not
CVAX CPU CHIP DESIGN SPECIFICATION Page 372
INTERRUPT LOGIC
be followed in the either of the next 2 cycles by another READ INT.ID, and
for the same reason IID_IRQ_H and FPD_INT_PENDING_H may not be valid
during those cycles. Software interrupts caused by the HSIR are cleared
via microcode. Hardware interrupts caused by the IRQ's are cleared via a
MEM.PHYS.VAP.INTVEC.
9.6 Microcode Restrictions
1. Microcode cannot take a branch that uses the FPD_INT_PENDING_H or
IID_IRQ_H signals for two cycles after the PSL is written. In
other words writes that CHANGE the IPL, HSIR, and ICCS<6> should
not be followed in either of the next two cycles by a BRANCH IID.
2. All non-data bits in HSIR, ICCS, and INT.ID are don't care on
WRITE and '1' on READ
3. Because of logic delays from READ INT.ID to clearing the
interrupt out of the priority encoder, a READ INT.ID can not be
followed in the next two cycles by another READ INT.ID, and for
the same reason IID_IRQ_H and FPD_INT_PENDING_H may not be valid
during the next two cycles.
CVAX CPU CHIP DESIGN SPECIFICATION Page 373
INTERRUPT LOGIC
9.7 Block Diagram
Interrupt Logic Block Diagram
W_SPUR<6>
----------------------------------------+
MXPS_WRITE_ICCS |
--------------------------------------+ |
MXPS_READ_ICCS | |
------------------------------------+ | |
| | |
| | |
HALT L PWRFL L | | | INTTIM L MEMERR L CRD L IRQ<3> L IRQ<2> L IRQ<1> L IRQ<0> L
| | | | | | | | | | | |
V V V V V V V V V V V V
+----------+ +----------+ +----------+ +----------+ +----------+ +-----+ +-----+ +-----+ +-----+
| edge det | | edge det | | edge det | | edge det | | edge det | |sync | |sync | |sync | |sync |
| latch | | latch | | latch | | latch | | latch | |latch| |latch| |latch| |latch|
+----------+ +----------+ +----------+ +----------+ +----------+ +-----+ +-----+ +-----+ +-----+
A | A | A | A | A | | | | |
| | | | | | | | | | | | | |
| | | | | | | | | | | | | |
| | | | | | | | | | | | | |
+----|----+----+-----|------------+--|--------+--|---------+ | | | | |
| | +--+ | | | | | | |
| | | +--------------+ | | | | | |
| | | | +----------------------+ | | | | |
| | | | | +-------------------------------+ | | | |
| | | | | | +----------------------------------------+ | | |
| | | | | | | +----------------------------------------------------+ | |
| | | | | | | | +----------------------------------------------------------------+ |
| | | | | | | | | +-----------------------------------------------------------------------+
| | | | | | | | | |
| | V V V V V V V V
| | +------------------------------+ +---------------------+ +--------------------+
| | | Interrupt Priority Encoder |--------->| IPL/ interrupt | <--| Interrupt section |<------+
| | | and HSIR |~highest | comparator | | copy of IPL | |
| | +------------------------------+ request +---------------------+ +--------------------+ |
| | | A A A | A |
+----|----------+ | | | | | | |
| | V V | | | | | |
| | +------------+ | | |MXPS_READ_HSIR | | |
| | +--->| encoder/ | | | | | |
| | | | driver | | |MXPS_WRITE_HSIR | from W_SPUR<4:0> |
| | | +------------+ | | |
| | | | | W_SPUR<3:0> +-------------------> FPD_INT_PENDING_H |
| | | V | |
| | | to W_SPUR<4:0> +--\''\ |
| | | )or>--> IID_IRQ_H |
+----|--|-----------------------------------------------/,,/ |
| | |
| | |
IRESET_H | |MXPS_READ_INT.ID LOAD_PSL |
CVAX CPU CHIP DESIGN SPECIFICATION Page 374
INTERRUPT LOGIC
9.8 OPEN ISSUES
1. Is the PSL<IPL> field read off the WBUS or the WSPUR ?
ANS: Mar-85 D.R.D. - PSL<20:16> (IPL) is read off the
W_SPUR<4:0>.
CVAX CPU CHIP DESIGN SPECIFICATION Page 375
CLOCK LOGIC
10 CLOCK LOGIC
The CVAX CPU chip receives two 20 Mhz, CMOS level, out of phase inputs
from the ClK_A and CLK_B pins. These inputs feed two separate
divide-by-two circuits which generate control signals used to separate the
individual phases from the inputs. The control signals feed NAND gates
which create the four internal chip clocks: PHI1, PHI2, PHI3, and PHI4.
Loading on the phase clocks can range up to 150pF.
The clock logic is also responsible for reset synchronization using the
external RESET_L pin as an input. To provide on-chip initialization, the
clock logic generates a reset signal, RESET_S, which will remain active
until the seventh rising edge of CLKA following the deassertion of
RESET_L. During reset time the internal clock phases will maintain the
synchronization they had before RESET_L was asserted. The first rising
edge of CLK_A after the dessertion of RESET will be PHI1, this is used for
system wide phase synchronization. If the internal clock phases do not
agree with the PHI1 indicated by the deassertion of RESET_L then there
will be a two phase dead period following the next phase 4 before the
rising edge of the next phase 1 (see waveform).
It is assumed that the control logic will present no DC loading on the
clock phases.
RESYNC WAVEFORMS CASE 1 - resync required
PHI1 __/~~~~~\________________________________/~~~~~\_____________________/~~~~~\_____________________/~~~~~\____________
| |
PHI2 ______/~~~~~\___________________________________/~~~~~\_____________________/~~~~~\_____________________/~~~~~\_____
| |
PHI3 _____________/~~~~~\___________________________________/~~~~~\_____________________/~~~~~\_____________________/~~~
| |
PHI4 ____________________/~~~~~\__________________________________/~~~~~\______________________/~~~~~\___________________
| |
RESET ____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
RESET_S ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\__________________
CASE 2 - no resync required
PHI1 __/~~~~~\__________________/~~~~~\_____________________/~~~~~\_____________________/~~~~~\_____________________/~~~
PHI2 ______/~~~~~\_____________________/~~~~~\_____________________/~~~~~\_____________________/~~~~~\__________________
PHI3 _____________/~~~~~\_____________________/~~~~~\_____________________/~~~~~\_____________________/~~~~~\___________
PHI4 ____________________/~~~~~\_____________________/~~~~~\_____________________/~~~~~\_____________________/~~~~~\____
RESET ________________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
RESET_S ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\___
CVAX CPU CHIP DESIGN SPECIFICATION Page 376
CLOCK LOGIC
10.1 Clock Input Buffer - Phase Separator
This circuit consists of 4 matched CMOS input level NAND gates followed by
a buffer capable of driving the capacitive load of the individual clock
phase. One input of the NAND gate will be either CLK_A or CLK_B and the
other a control line from the Phase Select logic.
10.2 RESET_L Input Buffer
This circuit consists of a TTL level converter and driver.
10.3 Phase Select Logic
The Phase Select Logic sends control signals to the 4 NAND gates which are
used to generate the 4 internal phases from the two external clocks. This
logic consists of two toggle flops, separately clocked by .not.CLK_A and
.not.CLK_B, it is forced to synchronization upon the deassertion of
RESET_L.
CVAX CPU CHIP DESIGN SPECIFICATION Page 377
CONTROL FIELDS SUMMARY
11 CONTROL FIELDS SUMMARY
The 41-bit microinstruction is divided into two major sections. The first
28 bits, Data Path Control, control the I Box, E Box, and Memory
Interface. This portion is encoded into five microinstruction formats.
The next 13 bits control the Microsequencer. This portion is encoded in
two formats.
11.1 Data Path Control Formats
BASIC
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 0 1 1| BASIC.FNC | L| B | DST | CC | MISC | A |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
CONSTANT
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 1| POS |CONS.FNC| CONST.BYTE |DS| CC | MISC | A |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
SHIFT
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 0 1 0| SHIFT.VAL |DR| B | DST | CC | MISC | A |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
MEM REQ
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 0 0 1| MEMREQ.FNC | L|RW|MREQ.ACC| DST | CC | MISC | A |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
SPECIAL
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 0 0 0| MISC1 |M2| MISC3 | DST | CC | MISC | A |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
11.2 Microsequencer Control Formats
CVAX CPU CHIP DESIGN SPECIFICATION Page 378
CONTROL FIELDS SUMMARY
12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+
BRANCH | 1|BRNCH COND SEL| BRANCH OFFSET |
+--+--+--+--+--+--+--+--+--+--+--+--+--+
12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+
JUMP | 0|SB| JUMP ADDRESS |
+--+--+--+--+--+--+--+--+--+--+--+--+--+
CVAX CPU CHIP DESIGN SPECIFICATION Page 379
CONTROL FIELDS SUMMARY
11.3 General Fields
The following fields appear in several of the microinstruction formats.
When they appear, they have the following meanings.
11.3.1 B_Bus Select (B) Field -
This field selects a register from the subfiles addressible on the B port
of the register file ([Wb]). It also addresses functions in the I Box and
the K Mux ([MID.BUFF], [MKDL]).
B port B = 0:7 select W[0:7] W[7] is SC
8 select WSN
9 select WSN.plus.1
A select MID.BUFF
B select MKDL
C select VA
D select VAP
E select VIBA
F unused
11.3.2 Destination (DST) Field -
This field determines whether the ALU result is dumped in the bit bucket,
written back to the register selected on the A port, written back to the
register selected on the B port, or written to W[sn].
tp 6
Code Function
---- --------
0 no destination
1 destination is A port select
2 destination is W[sn]
3 destination is B port select
11.3.3 Condition Code (CC) Field -
This field controls the condition code logic.
Code Function
---- --------
0 do not change condition codes
1 load ALU condition codes
2 load PSL condition codes
3 load ALU and PSL condition codes
Constant, shift and special microinstructions always evaluate the
condition codes based on longword data. Memory request and basic
CVAX CPU CHIP DESIGN SPECIFICATION Page 380
CONTROL FIELDS SUMMARY
microinstructions evaluated the condition codes based on the selected data
length.
11.3.4 A_Bus Select (A) Field -
This field selects a register from the subfiles addressible on the A port
of the register file ([Ga], [Wa], [Ta]). It also addresses functions in
the K Mux ([K1], [SEXTN]).
A port A = 0:E select G[0:E]
F select PC
10:1F select T[0:F]
20:27 select W[0:7] W[7] is SC
28 select WSN
29 select WSN.plus.1
2A select GRN G[rn]
2B select PSL
2C select Q register
2D
2E select K1 constant 1
2F select SEXTN (0 if alu.n = 0, -1 if 1)
30:37
38 select WSN Broadcast WBUS to FPA
39 select WSN.plus.1 Broadcast WBUS to FPA
3A select GRN G[rn] Broadcast WBUS to FPA
3B
3C
3D
3E
3F bit bucket WBUS
11.3.5 Miscellaneous (MISC) Field -
This field allows operations to happen in parallel with another data path
operation.
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CONTROL FIELDS SUMMARY
Code Function
---- --------
0 nop
1 write VA
2 write VAP
3 write SC
4 clear write buffer
5 restart prefetch
6 enable IB prefetch
7 disable IB prefetch
8 RN <-- 0
9 RN <-- RN-1
A RN <-- RN+1
B RN <-- RN+1 if DL = quad
C DL <-- byte
D DL <-- word
E DL <-- long
F DL <-- quad
10 clear STATE<2:0>
11 set STATE<0>
12 set STATE<1>
13 set STATE<2>
14 set REEXECUTE
15 clear MMGT.TD
16 unconditional load VIBA and PC
17 swap RN and RN.old
18 if BCOND load VIBA and PC and trap
19 if BCOND load VIBA and PC
1A old.z
1B shift.dl
1C RLOG
1D set PSL map to jizj
1E set PSL map to iiii
1F set PSL map to iiij
CVAX CPU CHIP DESIGN SPECIFICATION Page 382
CONTROL FIELDS SUMMARY
11.4 BASIC Microinstruction
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 0 1 1| BASIC.FNC | L| B | DST | CC | MISC | A |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
This microinstruction format is used for most of the specifier evaluation
and computation flows.
11.4.1 BASIC Function (BASIC.FNC) Field -
This field controls the B_Bus sign extension logic, the ALU, the ALU
shifter, and possibly the SC register.
Code Function
---- --------
0 A.PLUS.B
1 A.OR.B
2 A.PLUS.B.PLUS.(PSL.C)
3 A.MINUS.1
4 PASS.B
5 A.MINUS.B.PLUS.(.NOT.PSL.C)
6 A.AND.(.NOT.B)
7
8 .NOT.B
9 A.XOR.B
A PASS.A
B
C A.AND.B
D SMUL.STEP
E
F
10
11 A.PLUS.B.PLUS.1
12
13
14 A.MINUS.B
15
16 UDIV.STEP
17
18 B.MINUS.A
19 A.PLUS.1
1A .NEG.B
1B
1D
1E
1F
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CONTROL FIELDS SUMMARY
11.4.2 Length (L) Field -
This fields determines the effective data length for the microinstruction.
GPR can be written as a byte, word or longword; all other registers are
written as a longword and the data is zero extended based on L.
tp 5
Code Function
---- --------
0 length is longword
1 length is determined by the DL register
CVAX CPU CHIP DESIGN SPECIFICATION Page 384
CONTROL FIELDS SUMMARY
11.5 CONSTANT Microinstruction
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 1| POS |CONS.FNC| CONSTANT |DS| CC | MISC | A |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
This microinstruction allows operations on registers by 32-bit constants.
The effective data length is always LONG.
11.5.1 CONSTANT Position (POS) Field -
This field selects the position of the 8-bit constant within the 32-bit
longword.
POS <31:24> <23:16> <15:8> <7:0>
--- ------- ------- ------ -----
0 00000000 00000000 00000000 CONSTANT
1 00000000 00000000 CONSTANT 00000000
2 00000000 CONSTANT 00000000 00000000
3 CONSTANT 00000000 00000000 00000000
11.5.2 CONSTANT Destination (DS) Field -
This field determines whether the ALU result is dumped in the bit bucket
or written back to the register selected on the A-port.
tp 5
Code Function
---- --------
0 no destination
1 destination is A-port select
11.5.3 CONSTANT Function (CONST.FNC) Field -
This field selects the ALU function that operates on the contents of the
A_Bus and the constant.
Code Function
---- --------
0 A.MINUS.CONST
1 CONST.MINUS.A
2 A.PLUS.CONST
3 A.AND.CONST
4 A.OR.CONST
5 PASS.CONST
6 A.AND.NOT.CONST
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CONTROL FIELDS SUMMARY
7 A.XOR.CONST
This microinstruction allows operations on registers by 32-bit constants.
The effective data length is always LONG.
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CONTROL FIELDS SUMMARY
11.6 SHIFT Microinstruction
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 0 1 0| SHIFT.VAL |DR| B | DST | CC | MISC | A |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
This microinstruction, unlike all others, disables the ALU from driving
the W_Bus and enables the Shifter.
11.6.1 SHIFT Value (SHIFT.VAL) Field -
This field, when used, is the number of bits to shift.
11.6.2 SHIFT Function Fields (SHIFT.DIR, DST) -
These field determines the drivers of the A_ and B_Busses and the write
destination.
Dir Dst A_Bus B_Bus Dest Dir Shift Reg if SV = 0
--- --- ----- ----- ---- --- ----- -------------
0 0 A B none right SV SC
1 0 A B none left 32-SV SC
0 1 #0 B A right SV SC
1 1 A B A left 32-SV SC
0 2 A B WSN right SV SC
1 2 A B WSN left 32-SV SC
0 3 A B B right SV SC
1 3 A #0 B left 32-SV SC
When the Shift Value field is non-zero, SV is the Shift Value field.
Otherwise, SV is SC<4:0>, or, if the MISC field specifies USE.DL, is
DL<1:0>. This microinstruction allows operations on registers by 32-bit
constants. The effective data length is always LONG.
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CONTROL FIELDS SUMMARY
11.7 MEM REQ Microinstruction
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 0 0 1| MEMREQ.FNC | L|RW|MREQ.ACC| DST | CC | MISC | A |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
This microinstruction allows the E Box to transfer data to or from the
other parts of the chip, to other chips in the set, or to memory.
11.7.1 MEM REQ Function (MEMREQ.FNC) Field -
Reference Address VA' After
MEMREQ.FNC Function Type Source Reference
---------- -------- --------- ------- ---------
00 mem req virtual virtual VA VA+4
01
02 mem req virtual lock virtual VA VA+4
03
04 mem req virtual virtual VA' VA'+4
05 mem req virtual pte virtual VA' VA'+4
06 mem req virtual lock virtual VA' VA'+4
07
08 mem req physical physical VA VA+4
09
0A mem req physical lock physical VA VA+4
0B mem req physical ipr physical VA VA+4
0C mem req physical physical VA' VA'+4
0D mem req physical pte physical VA' VA'+4
0E mem req physical lock physical VA' VA'+4
0F mem req int vec physical VA' VA'+4
10 probe virtual virtual VA unchanged
11
12
13
14 probe virtual virtual VA' unchanged
15
16
17
18 FPA read unchanged
19
1A
1B
1C
1D MXPR unchanged
1E MXPS0 unchanged
1F MXPS1 unchanged
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CONTROL FIELDS SUMMARY
11.7.2 MEM REQ Length (L) Field -
This fields determines the effective data length for the microinstruction.
GPR can be written as a byte, word or longword; all other registers are
written as a longword and the data is zero extended based on L. Memory
data length is also determined by L.
Code Function
---- --------
0 length is longword
1 length is determined by the DL register
11.7.3 MEM REQ Read/Write (RW) Field -
This field defines the direction (read or write) of the memory request
operation.
Code Function
---- --------
0 read
1 write
11.7.4 MEM REQ Access Control (MEMREQ.ACC) Field -
For a virtual memory request or probe, this field defines the access
checks to be performed.
MEMREQ.ACC Priv Check Access Mode
---------- ---------- -----------
0 none current
1
2 read current
3 read mode
4 write current
5 write mode
6 AT = m current
7
For a MXPR microinstruction, this fields supplies the register number of
the internal register to or from which data is transferred.
Code R/W Register
---- --- --------
0
1 rw P0LR P0 length register
2 rw P1LR P1 length register
3 rw SLR System length register
4
5
6
7
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CONTROL FIELDS SUMMARY
For a read MXPS0 microinstruction, this fields supplies the register
number of the internal register from which data is transfered.
Code R/W Register
---- --- --------
0
1 r-w.clr MSER MSER<7:0> (write clears register)
2 ro INT highest interrupt in bits<4:0>
3 ro OPCODE opcode register in bits<7:0>
4 ro-rw SPEC.RN specifier in bits<7:4>(ro) - RN in <3:0>(rw)
5
6 rw HSIR highest software interrupt in <7:0>
7
For a read MXPS1 microinstruction, this fields supplies the register
number of the internal register from which data is transfered.
Code R/W Register
---- --- --------
0 rw ICCS ICCS<6> in bit<6>
1 rw CADR cache disable register
2 ro EBOX.STATE STATE<5:0> in bits <5:0>
3 ro EBOX.CCS restart, ALU CC's in bits <7,3:0>
4 ro RLOG.STACK RLOG[0]<7:0> in bits <7:0>
5 rw MAPEN MAPEN in bit<0>
6
7
For a write MXPS0 microinstruction, this fields supplies the register
number of the internal register to which data is transfered.
Code R/W Register
---- --- --------
0
1 r-w.clr MSER MSER is clear
2
3
4 ro-rw SPEC.RN RN in <3:0>, specifier bits in <7:4> unchanged
5
6 rw HSIR highest software interrupt in <7:0>
7
For a write MXPS1 microinstruction, this fields supplies the register
number of the internal register to which data is transfered.
Code R/W Register
---- --- --------
0 rw ICCS ICCS<6> in bit<6>
1 rw CADR cache disable register
2
3
4
5 rw MAPEN MAPEN in bit<0>
6 wo MMGT.STATUS MMGT.STATUS in bits <2:0>
CVAX CPU CHIP DESIGN SPECIFICATION Page 390
CONTROL FIELDS SUMMARY
7 wo PROBE.MODE alternate probe mode in bits<1:0>
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CONTROL FIELDS SUMMARY
11.8 SPECIAL Microinstruction
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| 0 0 0| MISC1 |M2| MISC3 | DST | CC | MISC | A |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
This microinstruction implements certain non-time critical functions. The
microword is broken up into three encoded fields plus the standard MISC
field.
11.8.1 SPECIAL Condition Code (MISC1) Field -
Code(bin) Function
---- --------
0 0000 nop
0 XXX1 invalidate translation buffer
0 XX1X set VAX TRAP REQUEST
0 X1XX set reprobe
0 1XXX set MMGT.TD
1 0000 simulator HALT
1 XXX1 invalidate translation buffer entry if hit
1 XX1X clear VAX TRAP REQUEST
11.8.2 SPECIAL Function (MISC2) Field -
Code Function
---- --------
0 nop
1 copy backup PC to PC
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CONTROL FIELDS SUMMARY
11.8.3 SPECIAL Control Flags (MISC3) Field -
Code Function
---- --------
0 nop
1 clear STATE<5:3>
2 set STATE<3>
3
4 set STATE<4>
5
6
7
8 set STATE<5>
9-F
CVAX CPU CHIP DESIGN SPECIFICATION Page 393
CONTROL FIELDS SUMMARY
11.9 BRANCH Microinstruction
12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+
BRANCH | 1|BRNCH COND SEL| BRANCH OFFSET |
+--+--+--+--+--+--+--+--+--+--+--+--+--+
This format (of the Microsequencer Control portion of the microword) is
used when CS<12> = 0. It allows relative branching on condition,
return-from-subroutine, and case branching.
11.9.1 Branch Condition Select (BCS) Field -
This field selects the branch condition or special function to be used in
generating the next microaddress.
Code Function
---- --------
0
1
2
3
4 return
5
6
7
8 DEC.NEXT decode next specifier
9
A If (DL=BWL) AND (AT=RVM) then DEC.NEXT, else CASE
B If (AT=RVM) then DEC.NEXT, else CASE
C If (DL=BWL) AND (AT=R) then DEC.NEXT, else CASE
D If (AT=R) then DEC.NEXT, else CASE
E If (AT=A) OR (AT=V) then DEC.NEXT, else CASE
F If DL=BWL then DEC.NEXT, else CASE
10 ALU.NZV case
11 ALU.NZC case
12 SC<2:0> case
13 SC<5:3> case
14
15 PSL<26:24> case
16 STATE<2:0> case
17 STATE<5:3> case
18 Mem Mgt1 status case (read/write'p0/p1/sys/lnv)
19 Mem Mgt2 status case
1A Mem Ref status case (RT/CVAX vs. CVAX'VIBA ok'mem ref ok)
1B FPA.DL case (FPA present'dl<1:0>)
1C INT.Reg Mode case (interrupt'prev. rmode'curr. rmode)
1D OPCODE<2:0> case
CVAX CPU CHIP DESIGN SPECIFICATION Page 394
CONTROL FIELDS SUMMARY
1E ID.LOAD case (at<1>'id<--ib.len(dl)<1:0>)
1F
11.9.2 Branch Offset (BO) Field -
This field contains the offset that is appended to uPC<10:8> when a branch
is taken.
CVAX CPU CHIP DESIGN SPECIFICATION Page 395
CONTROL FIELDS SUMMARY
11.10 JUMP Microinstruction
12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+
JUMP | 0|SB| JUMP ADDRESS |
+--+--+--+--+--+--+--+--+--+--+--+--+--+
This format (of the Microsequencer Control portion of the microword) is
used when CS<12> = 1. It allows absolute unconditional branching and
subroutine calling.
11.10.1 Subroutine (SB) Field -
This bit controls pushing the microstack. If it is SET, the address of
the microword plus one is pushed onto the microstack (a jump to subroutine
is done). If not, the microstack is unaffected.
11.10.2 Jump Address Field -
This field is used when JUMP microinstructions are being done. It
provides the 11 bits of the jump microaddress. This allows freedom to
jump anywhere in the 2K microcode space.
CVAX CPU CHIP DESIGN SPECIFICATION Page 396
TEST LOGIC
12 TEST LOGIC
The Test Logic enables test hardware to read internal CVAX state that is
not normally observable on the external pins. It also allows a tester to
force an external address applied to 11 redefined chip pins as the next
address for the control store. Test Logic can be conceptually divided
into logic that aids observability and logic that controls the test
operation.
12.1 Observability Logic
The Observability logic consists of four (4) parallel-in serial-out shift
registers which allow parallel loading of internal signals and serial
shifting of this data to the TEST_OUT pin (scan). In an alternate mode
(reduce) the shift registers become linear feedback shift registers, that
is instead of merely shifting the parallel loaded data out as a snapshot
of the machine state, an EXOR is inserted between each shift register bit
allowing the machine state to continuously affect the data being shifted,
producing a 1 bit per cycle signature at the TEST_OUT pin (CWB is
redefined as TEST_OUT if TEST=1). Three of these shift registers feed the
fourth register (main reducer) which further reduces the output of the
other three shift registers.
12.1.1 CWB Logic -
Clear Write Buffer (CWB) is asserted if the MISC field of the
microinstruction is decoded as 04 and STALL is not asserted. This signal
is updated during PHI3 and driven out the CWB/TESTOUT PIN if TEST is not
asserted, if TEST is asserted the pin is driven by the output of the
selected shift register.
12.2 Control Logic
A configuration latch selects which of the shift registers (or the main
reducer) drives TEST_OUT, if the shift registers should 'scan' or
'reduce', and if a BROADCAST should be forced. (see block diagram)
The micro-sequencer next address mux has a test state in which it passes
data applied to external pins directly to the MAB, allowing a tester to
specify the next micro-instruction totally independent of the value of the
next address specified by the previous micro-instruction (the micro-test
bus is ignored).
CVAX CPU CHIP DESIGN SPECIFICATION Page 397
TEST LOGIC
12.2.1 Normal State -
The Test Logic is in the 'normal' state when TEST=0. No pins are
redefined. The configuration latch is cleared and the TEST pin acts as
the ground for the ASL pin.
12.2.2 Test State -
12.2.2.1 TEST Pin - The Test Logic is in the 'test' state when TEST=1.
Since the TEST pin serves as ASL ground, ASL will be 'high' when in the
'test' state. Normally the chip couldn't do memory references in test
mode because rdy and err are ignored if AS is high. In the 'test' state
logic is enabled to allow sampling of ready and error pins irrespective of
the actual level of the ASL pin.
12.2.2.2 Internal MAB -
The Test Logic is in the 'test' state when TEST=1. CWB is redefined as
TEST_OUT, the POWER_FAIL pin is redefined to LOAD which is used to control
the parallel loading of all the shift registers (during PHI4), and HALT is
redefined to INT_EXT which controls whether the MAB is driven by external
pins or the normal internal paths. When INT_EXT=0, MAB<10:0> is
controlled by the normal (internal) paths.
12.2.2.3 External MAB -
When TEST=1 and INT_EXT=1 (should change during PHI2 only), MAB<10:0> is
driven by external redefined pins. IRQ<3:0>,CP_STAT<1:0> and CP_DAT<5:0>
are redefined to TEST_MAB<10:0> and CONFIGURE (see TEST CONTROL PINS).
TEST_MAB<10:0> are driven on MAB<10:0> and latched at the end of PHI1
(redefined pins must be valid by beginning of PHI4). The signal
G_S%INHIB_CP_OUT_H is asserted to block the use of the CP_DAT and CP_STAT
pins by the BIU.
12.2.2.4 Force Broadcast -
If the BROADCAST bit in the configuration latch is SET, the BIU asserts
G_S%BRDCST_BASIC_H causing the contents of the WBUS to be driven on the
DAL in the next cycle.
CVAX CPU CHIP DESIGN SPECIFICATION Page 398
TEST LOGIC
12.2.2.5 Configuration Latch -
+---+---+---+---+
| B | S | |
| R | - | SELECT|
| O | R | | |
+---+---+---+---+
BRO - force BASIC BROADCAST 0=no broadcast
S-R - Scan/Reduce select 0=reduce
SELECT - select which shift register to observe 00=main reducer
01=register #1
11=register #2
10=register #3
when TEST=0 configuration latch is reset to 0000
12.2.2.6 Loading Configuration Latch -
CONFIGURE controls loading of the configuration latch. When TEST=1,
INT_EXT=1, and CONFIGURE=1 the configuration latch is loaded with the data
on four (4) of the TEST_MAB pins during PHI3.
12.3 Shift Register Locations
12.3.1 MIB (Shift Register #1) -
Register #1 is located on the MIB. It will look at all of the MIB_H<40:0>
signals and the UTEST<2:0>. Sampling will occur on PHI1.
Inputs and bit positions are as follows:
1 - G_S%MIB_H<40>
2 - G_S%MIB_H<39>
3 - G_S%MIB_H<38>
4 - G_S%MIB_H<37>
5 - G_S%MIB_H<36>
6 - G_S%MIB_H<35>
7 - G_S%MIB_H<34>
8 - G_S%MIB_H<33>
9 - G_S%MIB_H<32>
10 - G_S%MIB_H<31>
11 - G_S%MIB_H<30>
12 - G_S%MIB_H<29>
13 - G_S%MIB_H<28>
14 - G_S%MIB_H<27>
15 - G_S%MIB_H<26>
CVAX CPU CHIP DESIGN SPECIFICATION Page 399
TEST LOGIC
16 - G_S%MIB_H<25>
17 - G_S%MIB_H<24>
18 - G_S%MIB_H<23>
19 - G_S%MIB_H<22>
20 - G_S%MIB_H<21>
21 - G_S%MIB_H<20>
22 - G_S%MIB_H<19>
23 - G_S%MIB_H<12>
24 - G_S%MIB_H<11>
25 - G_S%MIB_H<10>
26 - G_S%MIB_H<9>
27 - G_S%MIB_H<8>
28 - G_S%MIB_H<7>
29 - G_S%MIB_H<6>
30 - G_S%MIB_H<5>
31 - G_S%MIB_H<4>
32 - G_S%MIB_H<3>
33 - G_S%MIB_H<2>
34 - G_S%MIB_H<17>
35 - G_S%MIB_H<13>
36 - G_S%MIB_H<14>
37 - G_S%MIB_H<15>
38 - G_S%MIB_H<16>
39 - G_S%MIB_H<18>
40 - G_S%MIB_H<1>
41 - G_S%MIB_H<0>
42 - G_PH%UTEST_H<2>
43 - G_PH%UTEST_H<1>
44 - G_PH%UTEST_H<0>
Feedback taps for the reducer are located at bit positions 8, 33, 34 and
44.
12.3.2 I Box IPLA (Shift Register #2) -
Register #2 is located at the output of the IBOX IPLA. Sampling of its 24
outputs will occur on PHI1. The reducer only looks at 12 of the 24
outputs during any one cycle. A flip-flop toggled on PHI3 controls a 2 to
1 mux at the inputs of the reducer, allowing all 24 bits of the IPLA
output to be reduced with only 12 bits of reducer. The flip-flop is reset
to Group 1 by G_S%RESET_S.
Inputs and bit positions for the two groups are as follows:
Group 1 Group 2
1 - I_S%NEW_FPO_INSTR_H I_S%NEW_FPA_INSTR_H
2 - I_S%IPLA_EXE_ADDRESS_H<6> I_S%IPLA_EXE_ADDRESS_H<5>
3 - I_S%IPLA_EXE_ADDRESS_H<4> I_S%IPLA_EXE_ADDRESS_H<3>
4 - I_S%IPLA_EXE_ADDRESS_H<2> I_S%IPLA_EXE_ADDRESS_H<1>
5 - I_S%IPLA_EXE_ADDRESS_H<0> I_S%IPLA_DL_0_H<1>
6 - I_S%IPLA_DL_0_H<0> I_S%IPLA_DL_1_H<1>
CVAX CPU CHIP DESIGN SPECIFICATION Page 400
TEST LOGIC
7 - I_S%IPLA_DL_1_H<0> I_S%IPLA_DL_2_H<1>
8 - I_S%IPLA_DL_2_H<0> I_S%IPLA_AT_0_H<1>
9 - I_S%IPLA_AT_0_H<0> I_S%IPLA_AT_1_H<1>
10 - I_S%IPLA_AT_1_H<0> I_S%IPLA_AT_2_H<1>
11 - I_S%IPLA_AT_2_H<0> I_S%IPLA_SPECS_H<2>
12 - I_S%IPLA_SPECS_H<1> I_S%IPLA_SPECS_H<0>
Feedback taps for the reducer are located at bit positions 2, 3, 9 and 12.
12.3.3 Cache Refresh Address Generator/Reducer (Shift Register #3) -
The Cache uses a linear feedback shift register (reducer) to generate the
refresh address for the dynamic RAM. The MSB of this address
(G_S%C_RED_OUT_H) is fed to bit 4 of the Main Reducer.
12.3.4 Main Reducer (Shift Register #4) -
Register #4 is fed by the outputs of registers #1-3, sampling occurs on
PHI1. This register is only capable of operating in the 'reduce' mode.
Inputs and bit positions are as follows:
1 - Shift Register #1 output
2 - Shift Register #2 output
3 - Shift Register #3 output
4-7 dummy bits fed with zero's
Feedback taps for the reducer are located at bit positions 3 and 7.
CVAX CPU CHIP DESIGN SPECIFICATION Page 401
TEST LOGIC
12.4 Test Control Pins
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| H | P | I | I | I | I | C | C | C | C | C | C | C | C | C |
TEST = 0 | A | W | R | R | R | R | P | P | P | P | P | P | P | P | W | NORMAL
| L | R | Q | Q | Q | Q | . | . | . | . | . | . | . | . | B | OPERATION
| T | F | 0 | 1 | 2 | 3 | S | S | D | D | D | D | D | D | |
| | | | | | | T | T | A | A | A | A | A | A | |
| | | | | | | A | A | T | T | T | T | T | T | |
| | | | | | | 0 | 1 | 0 | 1 | 2 | 3 | 4 | 5 | |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| I | L | I | I | I | I | C | C | C | C | C | C | C | C | T |
TEST = 1 | - | O | R | R | R | R | P | P | P | P | P | P | P | P | E | TEST STATE - INTERNAL MAB
I/E = 0 | E | A | Q | Q | Q | Q | . | . | . | . | . | . | . | . | S |
| | D | 0 | 1 | 2 | 3 | S | S | D | D | D | D | D | D | T |
| | | | | | | T | T | A | A | A | A | A | A | - |
| | | | | | | A | A | T | T | T | T | T | T | O |
| | | | | | | 0 | 1 | 0 | 1 | 2 | 3 | 4 | 5 | U |
| | | | | | | | | | | | | | | T |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| I | L | C | | T |
TEST = 1 | - | O | O | TEST_MAB<10:0> | E | TEST STATE - EXTERAL MAB
I/E = 1 | E | A | N | | S | TEST_MAB SAMPLED DURING PHI1
| | D | F | 10| 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | T |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| B | S | | | TEST STATE - EXTERNAL MAB
CONF = 1 | R | - | | SELECT| TEST_MAB SAMPLED DURING PHI1
| O | R | |1 |0 | VALUE OF THESE PINS ARE LATCHED
+---+---+ +---+---+ INTO THE CONFIGURATION LATCH BITS
DURING PHI3
I-E - External/Internal MAB (INT_EXT) 0=internal
LOAD - Parallel load scan shift registers with scan data. 1=load
CONFIGURE - Parallel load configuration latch from TEST_MAB<3:0>. 1=configure
CVAX CPU CHIP DESIGN SPECIFICATION Page 402
TEST LOGIC
12.5 Block Diagram
S-R control --------|---------------|--------------|
| | |
CLOCK ----------|---------------|--------------| |
| | | | | |
S_R LOAD ---|---------------|--------------| | | SELECT<1:0>
| | | | | | | | | |
V V V V V V V V V |
+------------+ +------------+ +------------+ |
| SCANNER/ | | SCANNER/ | | | / 2
| REDUCER | | REDUCER | | REDUCER | |
| REGISTER #1| | REGISTER #2| | REGISTER #3| |
+------------+ +------------+ +------------+ |\|
| | | | \
| | |--------------------------------------->| |
| | | | |
| |------------------------------------------------------->| M|
| | | | U|-------------------------- TEST_OUT
|----------------------------------------------------------------------->| X|
| | | | |
V V V | |
+-----------------------------------------------------------------+ | |
| MAIN REDUCER (REGISTER #4) |---------------->| /
+-----------------------------------------------------------------+ |/
CVAX CPU CHIP DESIGN SPECIFICATION Page 403
APPENDIX: GLOBAL SIGNAL DICTIONARY
13 APPENDIX: GLOBAL SIGNAL DICTIONARY
G = GLOBAL SIGNAL L = PRECHARGING LOW
S = STATIC H = PRECHARGING HIGH
C = CLOCK = = VALID SIGNAL
PL = PRECHARGED LOW x = NOT VALID
PH = PRECHARGED HIGH _ = LOW ~ = HIGH
+----------+---------+---------+----------+
| PHI1 | PHI2 | PHI3 | PHI4 |
+---------------V---------------------------V----------+---------+---------+----------V--------------------------------------------+
| Signal | FULL | | |1|1|2|2|3|3|4|4|5|5|6|6|7|7|8|8|9|9|0| DESCRIPTION OF SIGNAL |
| Name | Name |0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0|5|0| |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| ACCESS_TYPE | G_S%ACCESS_TYPE_H<1:0> |===================xxxxxxxxxxx=========| ACCESS_TYPE REGISTER CONTENTS |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | valid PHI4 - 1nS to PHI3 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | 1= SET 2 HIT, 0= SET 1 HIT |
| ALLOC_SET | G_S%ALLOC_SET_H |========xxxxxxxxxx=====================| Assumed loading = 4pf |
| | | | | | | |
| | | | | | | Source - CACHE |
| | | | | | | |
| | | | | | | Dest - BIU |
| | | | | | | valid to 2.5 volts 16ns into PHI2 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| AT_EQ_MOD | G_S%AT_EQ_MOD_H |===================xxxxxxxxxxxx========| ACCESS_TYPE = MODIFY (WRITE) |
| | | | | | | |
| | | | | | | C load = 3.8pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - MBOX |
| | | | | | | valid PHI4 + 3nS to PHI3 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| B_BUS | G_PH%B_BUS_H<31:0> |~~xxxxxx======================HHHHHHHHH| B_BUS |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - EBOX,MBOX,IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | valid before PHI2 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 404
APPENDIX: GLOBAL SIGNAL DICTIONARY
| BIU_NOP | G_S%BIU_NOP_H |\\\______xxxxxxxxx=====================| BIU SHOULD NOP THIS MICROINSTRUCTION |
| | | | | | | |
| | | | | | | C load = 2.2pF |
| | | | | | | |
| | | | | | | Source - MBOX |
| | | | | | | |
| | | | | | | Dest - BIU |
| | | | | | | valid PHI2 + 21nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| BIU_TRAP | G_S%BIU_TRAP_L |==========xxxxxxx======================| BIU TRAP CONDITION DETECTED |
| | | | | | | |
| | | | | | | C load = 3.8pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - MBOX,USEQ,IBOX |
| | | | | | | valid PHI2 + 18nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| BRANCH_TRAP | G_S%BRANCH_TAKEN_TRAP_L |xxxxxxxxxxxxxxxxxx====================x| BRANCH TAKEN TRAP LINE |
| | | | | | | |
| | | | | | | C load = 2.5pF |
| | | | | | | |
| | | | | | | Source - EBOX |
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | |
| | | | | | | valid PHI3 - 6nS to PHI1 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| BRDCST_BASIC | G_S%BRDCST_BASIC_H |x============================xxxxxxxxxx| BASIC BROADCAST CYCLE |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - MBOX |
| | | | | | | valid PHI4 + 23nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| BRDCST_OK | G_S%BRDCST_OK_H |====================xxxxxxxxxx=========| FPU BROADCAST OK FLAG |
| | | | | | | |
| | | | | | | C load = 4.2pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - BIU, MBOX |
| | | | | | | valid PHI3 + 21nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| C_RED_OUT | G_S%C_RED_OUT_H |===================xxxxxxxx============| CACHE reducer output |
| | | | | | | |
| | | | | | | Source - CACHE |
CVAX CPU CHIP DESIGN SPECIFICATION Page 405
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | |
| | | | | | | Dest - Test Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| CASH_BUS | G_PL%CASH_BUS_H<5:0> |__xx==========================LLLLLLLLL| PRIVATE CACHE ADDRESS BUS WITH LOWER |
| | | | | | | ORDER BITS |
| | | | | | | |
| | | | | | | C load = 2pF |
| | | | | | | |
| | | | | | | Source - MBOX |
| | | | | | | |
| | | | | | | Dest - CACHE |
| | | | | | | valid PHI1 + 14nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| CACHE_ADDR_SRC| G_S%CACHE_ADDR_SRC_H<1:0> |__xxxxxxxxx==================\_________| INDICATES THE ADDRESS SOURCE THE CACHE |
| | | | | | | SHOULD BE USING |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - CACHE |
| | | | | | | valid PHI1 + 24nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| CACHE_FCN | G_S%CACHE_FCN_H<1:0> |__xxxxxxxxx==================\_________| CACHE FUNCTION CONTROL |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - CACHE |
| | | | | | | valid PHI1 + 24nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| CACHE_HIT | G_S%CACHE_HIT_L |============xxxxxxxxxxxxxxxxxxxxxxx====| CACHE READ SUCCESSFUL |
| | | | | | | |
| | | | | | | Source - CACHE |
| | | | | | | |
| | | | | | | Dest - BIU |
| | | | | | | valid PHI4 + 12nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| CONFIG | G_S%CONFIG_H |xxxxxxxxxxxxxxxxxx=============xxxxxxxx| IRQ<0> during test mode, load configuration|
| | | | | | | register |
| | | | | | | C load = 1pF |
| | | | | | | |
| | | | | | | Source - Interrupt Logic |
| | | | | | | |
| | | | | | | Dest - Test Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 406
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | |
| COPY_TRACE | G_S%COPY_TRACE_H |___/=====\_____________________________| COPY TRACE BITS FLAG |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | |
| | | | | | | note: conditioned by STALL in the IBOX |
| | | | | | | asserted PHI1 + 9nS to PHI2 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| CWB | P_S%CWB_L |===================xxxxxxxxx===========| Clear Write Buffer / Test output |
| | | | | | | |
| | | | | | | Source - |
| | | | | | | |
| | | | | | | Dest - PIN |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| DELTA_PC | G_S%DELTA_PC_L<2:0> |xxxx=================xxxxxxxxxxxxxxxxxx| NUMBER BYTES RETIRED BY IBOX |
| | | | | | | |
| | | | | | | C load = 2pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | valid PHI1 + 20nS to end of PHI2 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| DL | G_S%DL_H<1:0> |====================xxxxxxxxxx=========| DATA LENGTH REGISTER CONTENTS |
| | | | | | | |
| | | | | | | C load = 5.4pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX,MBOX,USEQ |
| | | | | | | valid PHI4 + 2nS to PHI3 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| DMA_INV_ADDR | G_S%DMA_INV_ADDR_H<5:0> | asynchronous | LOW ORDER ADDRESS BITS DURING A DMA |
| | | | | | | INVALIDATE CYCLE |
| | | | | | | |
| | | | | | | C load = 2pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - CACHE |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| FD_BIT | G_S%FD_BIT_L |xxxxxxxxxxxxx==========================| F or D Type Floating Point Instruction |
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 407
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | C load = 1.25pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - FPA LOGIC |
| | | | | | | valid PHI2 + 9nS to PHI4 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| FLUSH | G_S%FLUSH_H |=xxxxxx================================| FLUSH the CACHE |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - CACHE |
| | | | | | | valid PHI1 + 18nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| FP_INTEGER | G_S%FP_INTEGER_L |xxxxxxxxxxxxx==========================| INDICATES FLOATING POINT INTEGER INSTR |
| | | | | | | |
| | | | | | | C load = 1.2pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - FPA LOGIC |
| | | | | | | valid PHI2 + 9nS to PHI4 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| FPA_OPCODE | G_S%FPA_OPCODE_H<5:0> |xxxx===================================| Opcode for FPA interface |
| | | | | | | |
| | | | | | | C load = .9pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - FPA LOGIC |
| | | | | | | valid PHI2 + 13nS to PHI1 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| FPD_INT_PENDING G_S%FPD_INT_PENDING_H |\\\__________/=========================| INTERRUPT PENDING FLAG |
| | | | | | | |
| | | | | | | C load = 1.8pF |
| | | | | | | |
| | | | | | | Source - INTCTL |
| | | | | | | |
| | | | | | | Dest - IBOX (needed during PHI3 only) |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| FPU_CCZ | G_S%FPU_CCZ_H |xxxxxxxx===============================| CONDITION CODES FROM FPU |
| FPU_CCV | G_S%FPU_CCV_H | | | | | |
| FPU_CCN | G_S%FPU_CCN_H | | | | | C load = 2.9pF |
| | | | | | | |
| | | | | | | Source - FPA LOGIC |
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 408
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | Dest - EBOX |
| | | | | | | valid PHI1 + 20nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| FPU_IS_THERE | G_S%FPU_IS_THERE_H |=======================================| VALID ONLY DURING RESET, SETS FPU.PRES |
| | | | | | | |
| | | | | | | C load = 1pF |
| | | | | | | |
| | | | | | | Source - FPA LOGIC |
| | | | | | | |
| | | | | | | Dest - IBOX |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| FPU_TRAP | G_S%FPU_TRAP_L |==========xxxxxx=======================| FPU TRAP REQUEST LINE |
| | | | | | | |
| | | | | | | C load = 2.2pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - USEQ,IBOX |
| | | | | | | valid PHI2 + 15nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| HSIR_RD | G_S%HSIR_RD_L |=================xxxxxxxxxxxxxxxxxxxx==| read HSIR |
| | | | | | | |
| | | | | | | C load = .8pF |
| | | | | | | |
| | | | | | | Source - interrupt decode logic |
| | | | | | | |
| | | | | | | Dest - Interrupt Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| HSIR_WR | G_S%HSIR_WR_H |=================xxxxxxxxxxxxxxxxxxxx==| write HSIR |
| | | | | | | |
| | | | | | | C load = .9pF |
| | | | | | | |
| | | | | | | Source - interrupt decode logic |
| | | | | | | |
| | | | | | | Dest - Interrupt Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| I_E_SEL | G_S%I_E_SEL_H |=======================================| HALT during test, select int or ext MAB |
| | | | | | | |
| | | | | | | C load = 1.3pF |
| | | | | | | |
| | | | | | | Source - Interrupt Logic |
| | | | | | | |
| | | | | | | Dest - Test Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 409
APPENDIX: GLOBAL SIGNAL DICTIONARY
| I_RED_OUT | G_S%I_RED_OUT_H |===================xxxxxxxx============| IBOX reducer output |
| | | | | | | |
| | | | | | | C load = 1.4pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - Test Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| IB_DATA_PRS | G_S%IB_DATA_PRS_H |xxx___/=======================\________| IB DATA PRESENT ON IDAL |
| | | | | | | |
| | | | | | | C load = 4.4pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - IBOX |
| | | | | | | needed by PHI1 + 15 to PHI4 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| IB_FILL_ERR | G_PH%IB_FILL_ERR_L |HHHHHHHHHHxxxxxx=======================| ERROR SIGNAL FOR IB FILL PROBLEMS |
| | | | | | | |
| | | | | | | C load = 4pF |
| | | | | | | |
| | | | | | | Source - BIU,MBOX |
| | | | | | | |
| | | | | | | Dest - IBOX |
| | | | | | | |
| | | | | | | note: BIU assertion valid PHI2 + 15nS |
| | | | | | | MBOX assertion valid PHI2 + 21nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| IB_FILL_REQ | G_S%IB_FILL_REQ_H |=========xxxxxxxxxxxxxxxxxxxx==========| IB FILL REQUEST LINE |
| | | | | | | |
| | | | | | | C load = 3.1pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - MBOX |
| | | | | | | valid PHI3 + 21nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| IB_FILL_VALID | G_S%IB_FILL_VALID_H |=============================xxxxxx====| VALID IB FILL REQUEST TO BIU |
| | | | | | | |
| | | | | | | C load = 2.1pF |
| | | | | | | |
| | | | | | | Source - MBOX |
| | | | | | | |
| | | | | | | Dest - BIU |
| | | | | | | valid PHI4 + 13nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| ICCS_6 | G_S%ICCS_6_L |========xxxxxxx========================| INTERRUPT TIMER ENABLE BIT |
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 410
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | C load = .5pF |
| | | | | | | |
| | | | | | | Source - Interrupt MIB decoder in EBOX |
| | | | | | | |
| | | | | | | Dest - Interrupt Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| IDAL | G_S%IDAL_H<31:0> WRITE |==========xxxxxxxx=====================| INTERNAL DAL |
| | | | | | | |
| | READ |=============================xxxxx=====| C load = 10pF |
| | | | | | | |
| | | | | | | Source - CACHE,BIU,MBOX |
| | | | | | | |
| | | | | | | Dest - CACHE,BIU,MBOX,IBOX |
| | | | | | | valid PHI2 + 19nS WRITE |
| | | | | | | PHI4 + 8nS READ |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| IID_IRQ | G_S%IID_IRQ_H |\\\__________/=========================| INTERRUPT CASE FLAG |
| | | | | | | |
| | | | | | | C load = 1.6pF |
| | | | | | | |
| | | | | | | Source - Interrupt Logic |
| | | | | | | |
| | | | | | | Dest - IBOX |
| | | | | | | needed PHI2 + 16 to PHI1 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| IID_LD | G_S%IID_LD_H |_______________________/===============| IID SIGNAL TO CHIP |
| | | | | | | |
| | | | | | | C load = 4.1pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX, MBOX |
| | | | | | | valid PHI3 + 17 to PHI1 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| IMAB | G_S%IMAB_H<10:0> |xxxx=========================xxxxxxxxxx| IBOX MICRO-ADDRESS BUS |
| | | | | | | |
| | | | | | | C load = .9pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | valid PHI1 + 9 to PHI4 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| INHIB_CP_OUT | G_S%INHIB_CP_OUT_H |==========xxxxxxxx=====================| Tristate the CP_DAT and CP_STAT outputs|
| | | | | | | |
| | | | | | | C load = 1.5pF |
| | | | | | | |
| | | | | | | Source - Test Logic |
CVAX CPU CHIP DESIGN SPECIFICATION Page 411
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | |
| | | | | | | Dest - Interrupt Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| INT_BM | G_S%INT_BM_L<3:0> |=====================xxxx==============| BYTE MASK BITS FOR DAL DATA |
| | | | | | | |
| | | | | | | C load = 4pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - Cache |
| | | | | | | valid PHI3 + 13nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| INT_DP | G_S%INT_DP_H<3:0> | | | | | PARITY BITS FOR IDAL DATA |
| | WRITE |xxxxxxxxxxxxxxxxxxxxxxxxxx==========xxx| |
| | | | | | | C load = 5pF |
| | READ |x=====xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx| |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - CACHE |
| | | | | | | valid PHI3 + 15nS (WRITE) PHI4 + 23 (READ)|
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| INT_ID_RD | G_S%INT_ID_RD_L |=================xxxxxxxxxxxxxxxxxxxx==| read INT.ID |
| | | | | | | |
| | | | | | | C load = 1.2pF |
| | | | | | | |
| | | | | | | Source - interrupt decode logic |
| | | | | | | |
| | | | | | | Dest - Interrupt Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| INT_OVF | G_S%INT_OVFL_L |HHHHHHHHHH~~xxxxxx=====================| INTEGER OVERFLOW LINE |
| | | | | | | |
| | | | | | | C load = 2.1pF |
| | | | | | | |
| | | | | | | Source - EBOX |
| | | | | | | |
| | | | | | | Dest - IBOX, USEQ |
| | | | | | | |
| | | | | | | precharged PHI1 valid PHI3 - 6nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| LD_VIBA_AND_PC| G_S%LD_VIBA_AND_PC_H |==========xxxxxxxxxxxxxxx==============| GOING TO LOAD VIBA and PC |
| | | | | | | |
| | | | | | | C load = 9.6pF |
| | | | | | | |
| | | | | | | Source - EBOX |
| | | | | | | |
| | | | | | | Dest - IBOX,MBOX,BIU |
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 412
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | note: NOT conditioned with STALL |
| | | | | | | valid PHI3 + 6nS (can be improved) |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| LOAD | G_S%LOAD_H |============xxxxxxxxxxxxxxx============| PWRFL during test, parallel load the |
| | | | | | | reducers |
| | | | | | | |
| | | | | | | C load = .9pF |
| | | | | | | |
| | | | | | | Source - Interrupt Logic |
| | | | | | | |
| | | | | | | Dest - Test Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| LOAD_MASTER | G_S%LOAD_MASTER_OPCODE_H |____/=====\____________________________| LOADING OPCODE IN MASTER |
| | | | | | | |
| | | | | | | C load = 2.2pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | valid PHI1 + 12 to PHI2 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| LOAD_PSL | G_S%LOAD_PSL_H |__________/========\___________________| LOADING PSL ENABLE |
| | | | | | | |
| | | | | | | C load = 5.6pF |
| | | | | | | |
| | | | | | | Source - EBOX |
| | | | | | | |
| | | | | | | Dest - MBOX,IBOX,INT LOGIC,BIU |
| | | | | | | |
| | | | | | | note: conditioned with STALL |
| | | | | | | valid 6nS after PHI2 is valid thru |
| | | | | | | end of PHI2 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| LOAD_REDUCERS | G_S%LOAD_REDUCERS_L |/~~~~~~~~~~~~~~~~~~~~~~~~~~~~\=========| Parallel load reducers |
| | | | | | | |
| | | | | | | C load = 5.4pF |
| | | | | | | |
| | | | | | | Source - Test Logic |
| | | | | | | |
| | | | | | | Dest - IBOX, uSeq, Control Store |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| LOAD_SLAVE | G_S%LOAD_SLAVE_OPCODE_H |_____________________/========\________| LOAD SLAVE OF OPCODE REG |
| | | | | | | |
| | | | | | | C load = 1.2 pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 413
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | Dest - EBOX |
| | | | | | | |
| | | | | | | valid PHI3 + 16nS thru PHI4 + 10nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| M_STALL | G_S%M_STALL_H |xxxxxxxx=====================xxxxxxxxxx| MBOX CAN NOT USE THE IDAL |
| | | | | | | |
| | | | | | | C load = 5.2pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - MBOX |
| | | | | | | PHI1 + 24nS <<<<<<???? should be earlier |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MAB | G_S%MAB_H<10:0> |xxxxxxxx===============================| MICRO ADDRESS BUS |
| | | | | | | |
| | | | | | | C load = 1pF |
| | | | | | | |
| | | | | | | Source - USEQ |
| | | | | | | |
| | | | | | | Dest - CONTROL STORE |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MBOX_BM | G_S%MBOX_BM_L<3:0> |=xxxxxxxxxxxxx=========================| MBOX GENERATED BYTE MASK |
| | | | | | | |
| | | | | | | C load = 1pF |
| | | | | | | |
| | | | | | | Source - MBOX |
| | | | | | | |
| | | | | | | Dest - BIU |
| | | | | | | valid PHI2 + 15nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MIB | G_S%MIB_H<40:0> |===================xxxxxxxxx===========| MICRO-INSTRUCTION BUS |
| | G_S%MIB_L<40:7> | | | | | |
| | | | | | | |
| | | | | | | C load = 5pF |
| | | | | | | |
| | | | | | | Source - CONTROL STORE |
| | | | | | | |
| | | | | | | Valid low 1 nS before rising edge of PHI4 |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MLO_L | G_S%MLO_L<3:1> |xxxxxxxx===============================| MAB LATCH OUT TO UTEST "OR" LOGIC |
| | | | | | | |
| | | | | | | C load = .7pF |
| | | | | | | |
| | | | | | | Source - USEQ |
| | | | | | | |
| | | | | | | Dest - CONTROL STORE |
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 414
APPENDIX: GLOBAL SIGNAL DICTIONARY
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MMGT_TRAP | G_PH%MMGT_TRAP_L |HHHHHHHHHH~~xxxxxxx====================| MEMORY MANAGEMENT TRAP |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - MBOX |
| | | | | | | |
| | | | | | | Dest - USEQ,IBOX |
| | | | | | | valid PHI2 + 21nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MOD_INTENT | G_S%MOD_INTENT_H |xxxxxxxxxxx=========xxxxxxxxxxxxxxxxxxx| Modify Intent |
| | | | | | | |
| | | | | | | C load = 1pF |
| | | | | | | |
| | | | | | | Source - MBOX |
| | | | | | | |
| | | | | | | Dest - BIU |
| | | | | | | valid PHI2 + 5nS to BPHI3 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MW_BUS | G_PH%MW_BUS_H<31:0> | | THE BIDIRECTIONAL BUS BETWEEN THE IDAL |
| | | | | | | AND THE WBUS THAT IS AN INPUT TO THE |
| | | | | | | WBUS DRIVER |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - MBOX,EBOX |
| | | | | | | |
| | | | | | | Dest - EBOX,MBOX |
| | | | | | | valid PHI4 + 10nS on READ |
| | | | | | | valid PHI1 + 21nS on WRITE |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MW_DRIVE | G_S%MW_DRIVE_H |===================xxxxxx/=============| WHEN ASSERTED ENABLES THE EBOX TO DRIVE |
| | | | | | | THE MW_BUS |
| | | | | | | |
| | | | | | | C load = 1.7pF (((4.2pF))) |
| | | | | | | |
| | | | | | | Source - MBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | valid PHI3 + 12nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| MW_TO_W | G_S%MW_TO_W_H |=========xxxxxxxxxxx/==================| WHEN ASSERTED SELECTS THE MW_BUS AS |
| | | | | | | THE DATA SOURCE FOR DRIVING THE W_BUS |
| | | | | | | |
| | | | | | | C load = 1.9pF |
| | | | | | | |
| | | | | | | Source - MBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
CVAX CPU CHIP DESIGN SPECIFICATION Page 415
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | valid PHI3 + 1nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| NEW_IB_PTR | G_S%NEW_IB_PTR_H<1:0> |=========xxxxxx========================| LOW TWO BITS OF PC REGISTER |
| | | | | | | |
| | | | | | | C load = 1.9pF |
| | | | | | | |
| | | | | | | Source - EBOX |
| | | | | | | |
| | | | | | | Dest - IBOX |
| | | | | | | valid PHI2 + 14nS to next PHI2 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| ONE_SLOT_FREE | G_S%ONE_SLOT_FREE_H |=========xxxxxxxxxxxxx=================| Only one slot in the prefetch queue |
| | | | | | | is empty |
| | | | | | | |
| | | | | | | C load = 2.7pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - MBOX |
| | | | | | | valid PHI3 + 5nS to PHI2 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+===========
| | | | | | | |
| OPCODE | G_S%OPCODE_H<7:0> |~~~~~\\\\\\\\\==================/~~~~~~| EIGHT BITS TO OPCODE REGISTER |
| | | | | | | |
| | | | | | | C load = 1.75pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | Valid PHI2 + 11 to PHI4 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PHI1 | G_C%PHI1_H |/~~~~~~~\\\____________________________| PHASE 1 CLOCK |
| | | | | | | |
| | | | | | | C load = 140 pF |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PHI2 | G_C%PHI2_H |_________/~~~~~~~~\\\__________________| PHASE 2 CLOCK |
| | | | | | | |
| | | | | | | C load = 114 pF |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PHI3 | G_C%PHI3_H |___________________/~~~~~~~~\\\________| PHASE 3 CLOCK |
| | | | | | | |
| | | | | | | C load = 117 pF |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PHI4 | G_C%PHI4_H |\\___________________________/~~~~~~~~~| PHASE 4 CLOCK |
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 416
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | C load = 133 pF |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| PSL_T | G_S%PSL_T_H | | | | | PSL Trace bit (buffered W Bus) |
| | | | | | | |
| | | | | | | C load = 2.4pF |
| | | | | | | |
| | | | | | | Source - EBOX |
| | | | | | | |
| | | | | | | Dest - IBOX |
| | | | | | | valid while LOAD_PSL asserted |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| R_RED_OUT | G_S%R_RED_OUT_H |===================xxxxxxxx============| MIB reducer output |
| | | | | | | |
| | | | | | | C load = 1.8pF |
| | | | | | | |
| | | | | | | Source - Control Store |
| | | | | | | |
| | | | | | | Dest - Test Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| READ_DATA_PRS | G_S%READ_DATA_PRS_H |___/===============xxxxxxxxxxxxxxxxxxxx| IDAL HAS READ DATA |
| | | | | | | |
| | | | | | | C load = 2.1pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - MBOX |
| | | | | | | valid PHI1 + 8nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| READ_HIT | G_S%READ_HIT_H |_/=================xxxxxxxxxxxxxxxxxx\_| Cache Hit gated by BIU |
| | | | | | | |
| | | | | | | C load = 3.3pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - MBOX |
| | | | | | | valid PHI4 + 24nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| REDUCE_PHI1 | G_C%REDUCE_PHI1_H |/========\_____________________________| REDUCE mode clock |
| | | | | | | |
| | | | | | | Source - Test Logic |
| | | | | | | |
| | | | | | | Dest - IBOX, uSeq, Control Store |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| REG_WRITE | G_S%REG_WRITE_H |===================xxxxx===============| WRITE REGISTER ENABLED IN EBOX |
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 417
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | C load = 4.2pF |
| | | | | | | |
| | | | | | | Source - MBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | valid PHI3 + 11nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| RESET_S | G_S%RESET_S_H |~~\____________________________________| RESET Stretched |
| | | | | | | |
| | | | | | | Source - CLOCK LOGIC |
| | | | | | | |
| | | | | | | C load = 5pF assertion is asynchronous |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| RD_ICCS | G_S%RD_ICCS_H |~~~~~~\=============xxxxxxxxxHHHHHHHHHH| decoded read ICCS |
| | | | | | | |
| | | | | | | C load = .9pF |
| | | | | | | |
| | | | | | | Source - Interrupt Logic |
| | | | | | | |
| | | | | | | Dest - Interrupt Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| RN | G_S%RN_H<3:0> |====================xxxxxxxxxx=========| RN PART OF SPECIFIER BYTE |
| | | | | | | |
| | | | | | | C load = 2.3pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | valid PHI4 + 2 to PHI3 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| SCAN_PHI1 | G_C%SCAN_PHI1_H |/========\_____________________________| SCAN mode clock |
| | | | | | | |
| | | | | | | Source - Test Logic |
| | | | | | | |
| | | | | | | Dest - IBOX, uSeq, Control Store |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| SET_RESTART | G_S%SET_RESTART_H |===================xxxxxx==============| NO MMGT_ERROR ON WRITE |
| | | | | | | |
| | | | | | | C load = 4.2pF |
| | | | | | | |
| | | | | | | Source - MBOX latched with PHI3 |
| | | | | | | |
| | | | | | | Dest - EBOX strobed with PHI4 |
| | | | | | | valid PHI3 + 12nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 418
APPENDIX: GLOBAL SIGNAL DICTIONARY
| SET1_EN | G_S%SET1_EN_H |=========xxxxxxx=======================| ENABLE CACHE SET 1 |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - CACHE |
| | | | | | | valid PHI2 + 15nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| SET2_EN | G_S%SET2_EN_H |=========xxxxxxx=======================| ENABLE CACHE SET 2 |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - CACHE |
| | | | | | | valid PHI2 + 15nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| SN | G_S%SN_H<2:0> |===================xxxxxxxxxx==========| WORKING REGISTER NUMBER |
| | | | | | | |
| | | | | | | C load = 1.8pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | valid PHI4 - 1 to PHI3 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| SPUR_GETS_OP | G_S%SPUR_GETS_OPCODE_H |xxxxxxxxx==============================| Drive WSPUR with OPCODE |
| | | | | | | |
| | | | | | | C load = 1.1 pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | valid PHI2 thru PHI1 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| STALL | G_PH%STALL_L |HHHHHHHHHH~~xxxxxx=====================| CHIP-WIDE STALL SIGNAL |
| | | | | | | |
| | | | | | | Source - MBOX,BIU,EBOX,IBOX,uSEQ |
| | | | | | | |
| | | | | | | C load = 12pF |
| | | | | | | valid PHI2 + 21nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| T_RED_OUT | G_S%T_RED_OUT_H |===================xxxxxxxx============| Test reducer output |
| | | | | | | |
| | | | | | | C load = 1.8pF |
| | | | | | | |
| | | | | | | Source - Test Logic |
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 419
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | Dest - CWB Pad |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| TAG_PAR_ERR | G_S%TAG_PAR_ERR_H |==========xxxxxxxxxxxxxxxxxxxxxxxxx====| PARITY ERROR DETECTED IN TAG ON READ |
| | | | | | | |
| | | | | | | Source - CACHE |
| | | | | | | |
| | | | | | | Dest - BIU |
| | | | | | | Valid PHI4 + 13ns into 3pf |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| TEST | G_S%TEST_H |=xxxxxxxxxxxxxxxxxx====================| Test Control Input Buffered |
| | | | | | | |
| | | | | | | C load = 3pF |
| | | | | | | |
| | | | | | | Source - PIN Input Buffer |
| | | | | | | |
| | | | | | | Dest - TEST LOGIC |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| TEST_BRO | G_S%TEST_BRO_H |==================xxxxxxxxxxx==========| Force a basic broadcast |
| | | | | | | |
| | | | | | | Source - TEST LOGIC |
| | | | | | | |
| | | | | | | Dest - BIU |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| TEST_EXTMAB | G_S%TEST_EXTMAB_L |=============xxxxx=====================| DRIVE MAB WITH EXTERNAL MAB FROM PINS |
| | | | | | | |
| | | | | | | C load = 2.4pF |
| | | | | | | |
| | | | | | | Source - TEST LOGIC |
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| TEST_MAB | G_S%TEST_MAB_H<10:0> |==================xxxxxxxxxxx==========| EXTERNAL TEST MAB FROM PINS |
| | | | | | | |
| | | | | | | C load = 2.2pF |
| | | | | | | |
| | | | | | | Source - TEST LOGIC |
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| TRAP_PND | G_S%TRAP_PND_L |~~~~~~~~~~~~~~~~~~~~~\\\_______/~~~~~~~| Trap Pending - Zero MIB's |
| | | | | | | |
| | | | | | | C load = 1.7pF |
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 420
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | Source - USEQ |
| | | | | | | |
| | | | | | | Dest - Control Store |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| UTEST | G_PH%UTEST_L<2:0> |~xxxx===============HHHHHHHHHH~~~~~~~~~| MICRO-TEST BUS |
| | | | | | | |
| | | | | | | Source - |
| | | | | | | |
| | | | | | | Dest - USEQ |
| | | | | | | |
| | | | | | | C load = 4.5pF |
| | | | | | | |
| | | | | | | Precharged during PHI3 |
| | | | | | | Conditionally discharged during PHI1 |
| | | | | | | Latched on falling edge of PHI1 |
| | | | | | | Must be valid 15 nS after rising edge |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| UTEST_GETS_OP | G_S%UTEST_GETS_OPCODE_H |===================/~~~~~~~~~~xxxxxxxxx| Drive uTEST with OPCODE |
| | | | | | | |
| | | | | | | C load = .5pF |
| | | | | | | |
| | | | | | | Source - IBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | valid PHI1 thru PHI2 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| W_BUS | G_S%W_BUS_H<31:0> |=============================xxxxxxxxx=| W-BUS |
| | | | | | | |
| | | | | | | C load = 4.4pF |
| | | | | | | |
| | | | | | | Source - EBOX |
| | | | | | | |
| | | | | | | Dest - MBOX |
| | | | | | | valid PHI1 to beginning PHI4 |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| W_SPUR | G_PH%W_SPUR_H<7:0> | | | | | W-BUS SPUR |
| | WRITE |HHH~xxxxx=====================HHHHHHHHH| |
| | | | | | | C load = 6.5pF |
| | READ |==========HHHHHHHHHHHHH~xxxxxxxxxx=====| |
| | | | | | | Source - EBOX |
| | | | | | | |
| | | | | | | WRITE valid PHI1 + 21nS |
| | | | | | | READ valid PHI4 + 10nS |
| | | | | | | note: precharge is not removed until |
| | | | | | | 9.5 nS after PHI2 (or PHI4) |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| WR_ICCS | G_S%WR_ICCS_H |~~~~~\==============xxxxxxxxxxHHHHHHHHH| decoded write ICCS reg |
| | | | | | | |
CVAX CPU CHIP DESIGN SPECIFICATION Page 421
APPENDIX: GLOBAL SIGNAL DICTIONARY
| | | | | | | C load = .9pF |
| | | | | | | |
| | | | | | | Source - Interrupt Logic |
| | | | | | | |
| | | | | | | Dest - Interrupt Logic |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| WRONG_PAR | G_S%WRONG_PAR_H |==========xxxxxxx======================| INSERT WRONG PARITY IN CACHE |
| | | | | | | |
| | | | | | | C load = 5pF |
| | | | | | | |
| | | | | | | Source - BIU |
| | | | | | | |
| | | | | | | Dest - CACHE |
| | | | | | | |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
| | | | | | | |
| WSEL_UPDATE | G_S%WSEL_UPDATE_H |xxxxxxxxx==============================| UPDATE WSEL LATCHES IN EBOX |
| | | | | | | |
| | | | | | | C load = 2.7pF |
| | | | | | | |
| | | | | | | Source - MBOX |
| | | | | | | |
| | | | | | | Dest - EBOX |
| | | | | | | valid PHI1 + 21nS |
+---------------^----------------------------+-+-+1+-+-+-+-+2+-+-+-+-+3+-+-+-+-+4+-+-+---------------------------------------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 422
APPENDIX: BLOCK DIAGRAM
14 APPENDIX: BLOCK DIAGRAM
INTIM----------------+ MEM ERR--------+
PWRFL-------------+ | CRD-----+ |
HALT-----------+ | | IRQ<3:0>--+ | |
| | | | | |
IDAL<31:0> +-----------------+ V V V V V V
+---------------------------------+ | +----------+ | +-----------------------------+
| | | | | +-------IID.IRQ-----------------| |
| V V V +----------FPD.IRQ-----------------| Interrupts |
| +----+ +---------+ +-----------------+ |<-------->| |
| | BP | | | | |<--------------------------->| | |
<7:0>+----->| 0A | | 1 | | I-box |<--------------------+ | +-----------------------------+
D | | R |-->| K | | AT|---------------->| | |
P+--|----->| I | | B | | DL|------------>| | | |
^| | |<--| T | | | | <30,27,4>|<--------+ | | | |
3| | | | Y | | C | | |---->| | | | | | +-----------------------------+
:| | | +----+ | A | | IMIB|-----|---|---|---|---|-------|----------->| |
0| | | | C | +-----------------+ | | | | +-------|----------->| Microsequencer |
V| | | +----+ | H | | | | | | +---|----------->| |
| | | | BP | | E | +-----------------+<----+ | | | | | | | |
<15:8>+--|-->| 1A | | | | |<----|-->| | | | | | | |
| | | | R |-->| | | |<----|---|---+ | | | | | |
+--|--|-->| I | | | | |<----|---|---|---|---+ | | | |
| | |<--| T | | | | E-box |<----|---|---|---|---|---|-->| +-----------------------------+
| | | | Y | | | | | B| W| D| A| M| U| W| M|
| | | +----+ | | | | ^| ^| L| T| I| T| S| A|
| | | | | | | 3| 3| ^| ^| B| S| P| B|
| | | +----+ | | | | 1| 1| 1| 1| ^| E| U| ^|
| | | | BP | | | +-----------------+ :| :| :| :| 3| T| R| 1|
<23:16>+--|-->| 2A | | | 0| 0| 0| 0| 1| ^| ^| 0|
| | | | R |-->| | +-----------------+ V| V| V| V| :| 2| 7| :|
+--|--|-->| I | | | | |---->| | | | 0| :| :| 0|
| | |<--| T | | | | |<--------+ | | V| 0| 0| V|
| | | | Y | | | | |<------------+ | | V| V| +-----------------------------+
| | | +----+ | | | |<------------|---+ | | | | |
| | | | | | M-box |<------------|---|---+ | | | Control Store |
| | | +----+ | | | |-------------|---|---|-->| | | |
| | | | BP | | | | |<------------------------|-->| | |
<31:24>+--|-->| 3A | | | | | | | |<--|---|------------| |
| | | | R |-->| | | | | | | | | | |
+--|--|-->| I | | | +-----------------+ | | | | | | |
| | |<--| T | | | | ^ | | | | | | |
| | | | Y | | VA<8:3>|<---+ | | | | | | | |
| | | +----+ | DMA<8:3>|<------|----------------------+ | | | | | | |
| | | | | | | | | | | | | |
|<-|--|----------->|Parity | | | | | | | | +-----------------------------+
| | | | | | | | | | | |
| |<-|----------->|DIO | | | | | | | |
| | | +---------+ |
CVAX CPU CHIP DESIGN SPECIFICATION Page 423
APPENDIX: BLOCK DIAGRAM
| | | | | | | | | |
| | | | | | | | | |
| | | | | | | | | ^
| | | | | v v v ^ v
| | | | +--------------------------------------------------------+
| | +------------------------------|--->|IDAL PERR |
| +---------------------------------+<-->|IDAL | +-------------------+
+---------------------------------------->|IDAL Parity BIU | | |
CPSTA<1:0><---->| | | Clocks |
CPDAT<5:0><---->| | | |
+--------------------------------------------------------+ +-------------------+
^ ^ ^ | | | | | ^ | | ^ ^ ^ ^ ^ ^
| | | | | | | | | | | | | | | | |
DAL<31:0><----+ | | | | DBE<--+ | | | | BR<--+ | | | CLKA---+ | |
CS/DP<3:0><-------+ | | | WR<-----+ | | | CCTL<----+ | | CLKB------+ |
AS<----------+ | | CM<--------+ | | ERR--------+ | RESET---------+
DS<-------------+ | DMR------------+ | RDY-----------+
BM<3:0><----------------+ DMG<--------------+
CVAX CPU CHIP DESIGN SPECIFICATION Page 424
APPENDIX: CHIP INTERCONNECT DIAGRAM
15 APPENDIX: CHIP INTERCONNECT DIAGRAM
CLKA---------+
|
CLKB-------+ |
| |
VCC -----+ | | +----- GND
| | | |
V V V V
+-------+
IRQ<3:0> L ------------------->| |<---------------------+-----------------------------> AS L
| | |
| | | +-------+
INTTIM L ------------------->| | |------->| |
| | DAL<31:00> | | |
| |<--------------+-------------->| latch |------------> BA<29:00>
| | | | | |
| | | | +-------+
| | | |
PWRFL L ------------------->| | | | +-------+
| | | | |trans- |
| | +-------------->|ceiver |<-----------> BD<31:00>
CRD L ------------------->| | | | |
| CVAX | | +-------+
| CPU | | ^ ^
BR L <-------------------| Chip | | | |
| |---------------------------------+---|--------------> DBE L
| | | | |
MEMERR L ------------------->| | | | |
| |-------------------------------------+--------------> WR L
| | | | |
HALT L ------------------->| | | | |
| |----------------------------------------------------> DS L
| | | | |
ERR L ------------------->| | | | |
| | | v v
| | | +-------+
RDY L ------------------->| | CS/DP<3:0> L | |trans- |
| |<--------------+-------------->|eiver |<-----------> Parity
| | | | | |
CCTL L ------------------->| | | | +-------+
| | | |
| | | | +-------+
RESET L ------------------->| | | +------->| |
| | | | latch |
| | +-------------->| |<-----------> Cycle status
DMR L ------------------->| | +-------+
| |
| |
DMG L <-------------------| |----------------------------------------------------> BM <3:0> L
| |
| |
CM L <-------------------| |<----------------------------------------------------> coprocessor functions
+-------+