IBM Netfinity 5000 POST/BIOS Remote Flash Diskette
                    Version 1.07
               Installation README File


This README file contains the latest information about installing
the IBM Netfinity 5000 POST/BIOS.


CONTENTS
________

1.0  Updating IBM Netfinity 5000 POST/BIOS
2.0  Version Changes
3.0  Trademarks and Notices


1.0  Updating IBM Netfinity 5000 POST/BIOS
______________________________________________

   This remote flash diskette contains the POST / BIOS update
   file for use with Netfinity manager.
   Please refer to your Netfinity Manager documentation for
   instructions on use.


2.0  Version Changes
____________________

1.07    New release - BIOS level 10.

- ISA VGA support.
- Zero memory between 480 and 640k.
- Setup item to enable / disable boot fail check.
- Update flash code to support new Intel device.

1.06    New release - BIOS level 9.

- New patch file for C0 step Pentium III
- Fix VPD save problem

1.05    New release - BIOS level 8.

- Unreported I/O fix
- Not flushing data from SP data port
- S3 SSVID Update
- RS485 Updates for remote flash
- Diags Flash fix KYBD Emulator
- Support for multiple PCI video adapters
- Fix DMI invalid handle error
- Remove beeps from remote flash update
- Reintroduce A1 Step Processor support

1.04    New release - BIOS level 7.

- Fix intermittent hang during SMI install
- Fix intermittent hang during autoconfig
- AMD reset fix - pass 9 planars
- Turn off memory prefetch
- Final ACPI code implemented
- Fix support for video in 2nd PCI bus with new chipset rev

1.03     New release - BIOS level 4.

- Add support for Katmai processors
- Add support for remote bootblock recovery
- Add menu to allow PCI Master Write Streaming to be disabled for debug purposes
- Add bug fix for failed RIPL boots.
- Modified VID detection to take account of pass 8 or 9 planar.

1.02     New release - BIOS level 3.

- Fixed support for Artic and 5250 adapters.
- Added error handling for VRM fails.
- Modified SMI action table to put clock synchronisation at the end.
- Added setup option to support PCI 2.1 non compliant adapters.

1.01     New release - BIOS level 2.

- Bypass clock synchronisation when service processor busy

-------  ------------------------
1.00     First release - BIOS level 1.

- Fixed update of editable VPD information
- Fixed reporting of POST halt to service processor
- Removed some core chipset setup items and fixed some setup screen
  corruption


3.0  Trademarks and Notices
___________________________

THIS DOCUMENT IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
KIND. IBM DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS OR
IMPLIED, INCLUDING WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE AND
MERCHANTABILITY WITH RESPECT TO THE INFORMATION IN THIS
DOCUMENT. BY FURNISHING THIS DOCUMENT, IBM GRANTS NO LICENSES
TO ANY PATENTS OR COPYRIGHTS.

Note to U.S. Government Users -- Documentation related to restricted
rights -- Use, duplication or disclosure is subject to restrictions
set forth in GSA ADP Schedule Contract with IBM Corp.